Group : i2c_env_pkg::i2c_fifo_reset_cg
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Group : i2c_env_pkg::i2c_fifo_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
81.82 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv



Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 2 18 90.00
Crosses 24 6 18 75.00


Variables for Group i2c_env_pkg::i2c_fifo_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_overflow 2 1 1 50.00 100 1 1 2
cp_acq_threshold 2 0 2 100.00 100 1 1 2
cp_acqrst 2 0 2 100.00 100 1 1 2
cp_fmt_threshold 2 0 2 100.00 100 1 1 2
cp_fmtrst 2 0 2 100.00 100 1 1 2
cp_rx_overflow 2 1 1 50.00 100 1 1 2
cp_rx_threshold 2 0 2 100.00 100 1 1 2
cp_rxrst 2 0 2 100.00 100 1 1 2
cp_tx_threshold 2 0 2 100.00 100 1 1 2
cp_txrst 2 0 2 100.00 100 1 1 2


Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_fmt_threshold_cross 4 0 4 100.00 100 1 1 0
cp_rx_threshold_cross 4 1 3 75.00 100 1 1 0
cp_acq_threshold_cross 4 1 3 75.00 100 1 1 0
cp_rx_overflow_cross 4 2 2 50.00 100 1 1 0
cp_acq_overflow_cross 4 2 2 50.00 100 1 1 0
cp_tx_threshold_cross 4 0 4 100.00 100 1 1 0


Summary for Variable cp_acq_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_acq_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3625 1 T1 6 T2 6 T3 1



Summary for Variable cp_acq_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acq_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3613 1 T1 6 T2 6 T3 1
auto[1] 12 1 T60 5 T207 2 T208 5



Summary for Variable cp_acqrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_acqrst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1066 1 T1 5 T2 5 T6 2
auto[1] 2559 1 T1 1 T2 1 T3 1



Summary for Variable cp_fmt_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmt_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2962 1 T1 1 T2 1 T3 1
auto[1] 663 1 T1 5 T2 5 T6 2



Summary for Variable cp_fmtrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_fmtrst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 936 1 T1 5 T2 5 T6 2
auto[1] 2689 1 T1 1 T2 1 T3 1



Summary for Variable cp_rx_overflow

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_rx_overflow

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3625 1 T1 6 T2 6 T3 1



Summary for Variable cp_rx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3597 1 T1 6 T2 6 T3 1
auto[1] 28 1 T6 1 T47 1 T79 1



Summary for Variable cp_rxrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rxrst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1288 1 T1 5 T2 5 T6 1
auto[1] 2337 1 T1 1 T2 1 T3 1



Summary for Variable cp_tx_threshold

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tx_threshold

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3163 1 T1 2 T2 1 T3 1
auto[1] 462 1 T1 4 T2 5 T6 2



Summary for Variable cp_txrst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_txrst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1066 1 T6 2 T47 2 T79 2
auto[1] 2559 1 T1 6 T2 6 T3 1



Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins
cp_fmt_thresholdcp_fmtrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 380 1 T71 6 T72 9 T73 5
auto[0] auto[1] 2582 1 T1 1 T2 1 T3 1
auto[1] auto[0] 556 1 T1 5 T2 5 T6 2
auto[1] auto[1] 107 1 T49 4 T46 1 T35 1



Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_rx_threshold_cross

Uncovered bins
cp_rx_thresholdcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_rx_thresholdcp_rxrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1288 1 T1 5 T2 5 T6 1
auto[0] auto[1] 2309 1 T1 1 T2 1 T3 1
auto[1] auto[1] 28 1 T6 1 T47 1 T79 1



Summary for Cross cp_acq_threshold_cross

Samples crossed: cp_acq_threshold cp_fmtrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cp_acq_threshold_cross

Uncovered bins
cp_acq_thresholdcp_fmtrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_acq_thresholdcp_fmtrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 924 1 T1 5 T2 5 T6 2
auto[0] auto[1] 2689 1 T1 1 T2 1 T3 1
auto[1] auto[0] 12 1 T60 5 T207 2 T208 5



Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes
cp_rx_overflowcp_rxrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_rx_overflowcp_rxrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1288 1 T1 5 T2 5 T6 1
auto[0] auto[1] 2337 1 T1 1 T2 1 T3 1



Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cp_acq_overflow_cross

Element holes
cp_acq_overflowcp_acqrstCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_acq_overflowcp_acqrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1066 1 T1 5 T2 5 T6 2
auto[0] auto[1] 2559 1 T1 1 T2 1 T3 1



Summary for Cross cp_tx_threshold_cross

Samples crossed: cp_tx_threshold cp_txrst
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_tx_threshold_cross

Bins
cp_tx_thresholdcp_txrstCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 876 1 T27 2 T31 2 T71 12
auto[0] auto[1] 2287 1 T1 2 T2 1 T3 1
auto[1] auto[0] 190 1 T6 2 T47 2 T79 2
auto[1] auto[1] 272 1 T1 4 T2 5 T49 4

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