Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	780167	1			T1	3		T2	3		T3	40
all_pins[1]	780167	1			T1	3		T2	3		T3	40
all_pins[2]	780167	1			T1	3		T2	3		T3	40
all_pins[3]	780167	1			T1	3		T2	3		T3	40
all_pins[4]	780167	1			T1	3		T2	3		T3	40
all_pins[5]	780167	1			T1	3		T2	3		T3	40
all_pins[6]	780167	1			T1	3		T2	3		T3	40
all_pins[7]	780167	1			T1	3		T2	3		T3	40
all_pins[8]	780167	1			T1	3		T2	3		T3	40
all_pins[9]	780167	1			T1	3		T2	3		T3	40
all_pins[10]	780167	1			T1	3		T2	3		T3	40
all_pins[11]	780167	1			T1	3		T2	3		T3	40
all_pins[12]	780167	1			T1	3		T2	3		T3	40
all_pins[13]	780167	1			T1	3		T2	3		T3	40
all_pins[14]	780167	1			T1	3		T2	3		T3	40

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8386211	1			T1	38		T2	40		T3	600
values[0x1]	3316294	1			T1	7		T2	5		T4	613
transitions[0x0=>0x1]	2679234	1			T1	7		T2	5		T4	594
transitions[0x1=>0x0]	2678201	1			T1	6		T2	4		T4	593

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84653	1			T3	40		T4	3		T6	1
all_pins[0]	values[0x1]	695514	1			T1	3		T2	3		T4	260
all_pins[0]	transitions[0x0=>0x1]	694925	1			T1	3		T2	3		T4	260
all_pins[0]	transitions[0x1=>0x0]	185	1			T49	4		T46	2		T35	2
all_pins[1]	values[0x0]	779393	1			T1	3		T2	3		T3	40
all_pins[1]	values[0x1]	774	1			T49	4		T46	2		T187	3
all_pins[1]	transitions[0x0=>0x1]	742	1			T49	3		T46	1		T187	3
all_pins[1]	transitions[0x1=>0x0]	72	1			T49	3		T46	4		T35	1
all_pins[2]	values[0x0]	780063	1			T1	3		T2	3		T3	40
all_pins[2]	values[0x1]	104	1			T49	4		T46	5		T35	2
all_pins[2]	transitions[0x0=>0x1]	80	1			T49	3		T46	4		T35	1
all_pins[2]	transitions[0x1=>0x0]	77	1			T49	4		T46	1		T35	3
all_pins[3]	values[0x0]	780066	1			T1	3		T2	3		T3	40
all_pins[3]	values[0x1]	101	1			T49	5		T46	2		T35	4
all_pins[3]	transitions[0x0=>0x1]	86	1			T49	4		T46	2		T35	3
all_pins[3]	transitions[0x1=>0x0]	98	1			T49	2		T46	1		T35	2
all_pins[4]	values[0x0]	780054	1			T1	3		T2	3		T3	40
all_pins[4]	values[0x1]	113	1			T49	3		T46	1		T35	3
all_pins[4]	transitions[0x0=>0x1]	86	1			T49	2		T35	2		T68	3
all_pins[4]	transitions[0x1=>0x0]	87	1			T49	3		T46	3		T35	2
all_pins[5]	values[0x0]	780053	1			T1	3		T2	3		T3	40
all_pins[5]	values[0x1]	114	1			T49	4		T46	4		T35	3
all_pins[5]	transitions[0x0=>0x1]	91	1			T49	4		T46	4		T37	1
all_pins[5]	transitions[0x1=>0x0]	592370	1			T4	12		T8	7		T10	7
all_pins[6]	values[0x0]	187774	1			T1	3		T2	3		T3	40
all_pins[6]	values[0x1]	592393	1			T4	12		T8	7		T10	7
all_pins[6]	transitions[0x0=>0x1]	575272	1			T4	9		T8	4		T10	7
all_pins[6]	transitions[0x1=>0x0]	12910	1			T4	39		T8	34		T10	30
all_pins[7]	values[0x0]	750136	1			T1	3		T2	3		T3	40
all_pins[7]	values[0x1]	30031	1			T4	42		T8	37		T10	30
all_pins[7]	transitions[0x0=>0x1]	10836	1			T4	33		T8	33		T10	25
all_pins[7]	transitions[0x1=>0x0]	601994	1			T4	13		T6	1		T8	10
all_pins[8]	values[0x0]	158978	1			T1	3		T2	3		T3	40
all_pins[8]	values[0x1]	621189	1			T4	22		T6	1		T8	14
all_pins[8]	transitions[0x0=>0x1]	21292	1			T4	15		T8	9		T10	14
all_pins[8]	transitions[0x1=>0x0]	2041	1			T1	1		T2	1		T4	10
all_pins[9]	values[0x0]	178229	1			T1	2		T2	2		T3	40
all_pins[9]	values[0x1]	601938	1			T1	1		T2	1		T4	17
all_pins[9]	transitions[0x0=>0x1]	601920	1			T1	1		T2	1		T4	17
all_pins[9]	transitions[0x1=>0x0]	64	1			T49	1		T46	2		T35	2
all_pins[10]	values[0x0]	780085	1			T1	3		T2	3		T3	40
all_pins[10]	values[0x1]	82	1			T49	2		T46	2		T35	2
all_pins[10]	transitions[0x0=>0x1]	66	1			T49	1		T46	2		T35	1
all_pins[10]	transitions[0x1=>0x0]	773601	1			T1	3		T2	1		T4	260
all_pins[11]	values[0x0]	6550	1			T2	2		T3	40		T4	3
all_pins[11]	values[0x1]	773617	1			T1	3		T2	1		T4	260
all_pins[11]	transitions[0x0=>0x1]	773594	1			T1	3		T2	1		T4	260
all_pins[11]	transitions[0x1=>0x0]	81	1			T49	3		T46	4		T35	1
all_pins[12]	values[0x0]	780063	1			T1	3		T2	3		T3	40
all_pins[12]	values[0x1]	104	1			T49	3		T46	5		T35	2
all_pins[12]	transitions[0x0=>0x1]	80	1			T49	3		T46	4		T35	1
all_pins[12]	transitions[0x1=>0x0]	91	1			T49	2		T77	1		T216	1
all_pins[13]	values[0x0]	780052	1			T1	3		T2	3		T3	40
all_pins[13]	values[0x1]	115	1			T49	2		T46	1		T35	1
all_pins[13]	transitions[0x0=>0x1]	89	1			T49	2		T46	1		T35	1
all_pins[13]	transitions[0x1=>0x0]	79	1			T49	3		T46	3		T35	1
all_pins[14]	values[0x0]	780062	1			T1	3		T2	3		T3	40
all_pins[14]	values[0x1]	105	1			T49	3		T46	3		T35	1
all_pins[14]	transitions[0x0=>0x1]	75	1			T49	3		T46	1		T77	1
all_pins[14]	transitions[0x1=>0x0]	694451	1			T1	2		T2	2		T4	259