Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	465	1			T49	11		T46	15		T35	11
all_values[1]	465	1			T49	11		T46	15		T35	11
all_values[2]	465	1			T49	11		T46	15		T35	11
all_values[3]	465	1			T49	11		T46	15		T35	11
all_values[4]	465	1			T49	11		T46	15		T35	11
all_values[5]	465	1			T49	11		T46	15		T35	11
all_values[6]	465	1			T49	11		T46	15		T35	11
all_values[7]	465	1			T49	11		T46	15		T35	11
all_values[8]	465	1			T49	11		T46	15		T35	11
all_values[9]	465	1			T49	11		T46	15		T35	11
all_values[10]	465	1			T49	11		T46	15		T35	11
all_values[11]	465	1			T49	11		T46	15		T35	11
all_values[12]	465	1			T49	11		T46	15		T35	11
all_values[13]	465	1			T49	11		T46	15		T35	11
all_values[14]	465	1			T49	11		T46	15		T35	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3687

1

T49

79

T46

129

T35

80

auto[1]

3288

1

T49

86

T46

96

T35

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1208

1

T49

22

T46

23

T35

15

auto[1]

5767

1

T49

143

T46

202

T35

150

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4164

1

T49

110

T46

143

T35

101

auto[1]

2811

1

T49

55

T46

82

T35

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T49	2		T46	1		T205	2
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T49	4		T46	4		T35	2
all_values[0]	auto[0]	auto[1]	auto[0]	31	1			T49	1		T35	2		T244	1
all_values[0]	auto[0]	auto[1]	auto[1]	103	1			T46	4		T35	1		T174	1
all_values[0]	auto[1]	auto[0]	auto[1]	94	1			T49	3		T46	3		T35	4
all_values[0]	auto[1]	auto[1]	auto[1]	91	1			T49	1		T46	3		T35	2
all_values[1]	auto[0]	auto[0]	auto[0]	53	1			T35	2		T37	1		T205	2
all_values[1]	auto[0]	auto[0]	auto[1]	111	1			T49	3		T46	8		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T35	1		T205	2		T77	1
all_values[1]	auto[0]	auto[1]	auto[1]	98	1			T49	2		T46	3		T35	4
all_values[1]	auto[1]	auto[0]	auto[1]	101	1			T49	2		T46	2		T35	2
all_values[1]	auto[1]	auto[1]	auto[1]	82	1			T49	4		T46	2		T35	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T49	1		T237	1		T245	1
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T49	3		T46	5		T35	2
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T237	1		T246	2		T244	1
all_values[2]	auto[0]	auto[1]	auto[1]	115	1			T49	3		T46	1		T35	4
all_values[2]	auto[1]	auto[0]	auto[1]	105	1			T46	6		T35	2		T174	2
all_values[2]	auto[1]	auto[1]	auto[1]	91	1			T49	4		T46	3		T35	3
all_values[3]	auto[0]	auto[0]	auto[0]	46	1			T49	1		T174	1		T237	1
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T49	2		T46	3		T174	1
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T35	2		T247	1		T189	1
all_values[3]	auto[0]	auto[1]	auto[1]	111	1			T49	4		T46	5		T35	4
all_values[3]	auto[1]	auto[0]	auto[1]	100	1			T49	1		T46	3		T35	1
all_values[3]	auto[1]	auto[1]	auto[1]	82	1			T49	3		T46	4		T35	4
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T174	3		T248	1		T247	2
all_values[4]	auto[0]	auto[0]	auto[1]	107	1			T49	7		T46	5		T35	4
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T174	1		T248	3		T189	3
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T49	1		T46	5		T35	3
all_values[4]	auto[1]	auto[0]	auto[1]	107	1			T49	1		T46	3		T35	2
all_values[4]	auto[1]	auto[1]	auto[1]	97	1			T49	2		T46	2		T35	2
all_values[5]	auto[0]	auto[0]	auto[0]	47	1			T49	1		T174	1		T237	1
all_values[5]	auto[0]	auto[0]	auto[1]	106	1			T49	2		T46	8		T35	4
all_values[5]	auto[0]	auto[1]	auto[0]	31	1			T49	1		T35	1		T237	1
all_values[5]	auto[0]	auto[1]	auto[1]	97	1			T49	2		T46	4		T35	2
all_values[5]	auto[1]	auto[0]	auto[1]	103	1			T49	2		T35	3		T174	1
all_values[5]	auto[1]	auto[1]	auto[1]	81	1			T49	3		T46	3		T35	1
all_values[6]	auto[0]	auto[0]	auto[0]	50	1			T46	1		T174	2		T77	1
all_values[6]	auto[0]	auto[0]	auto[1]	107	1			T49	7		T46	6		T35	4
all_values[6]	auto[0]	auto[1]	auto[0]	45	1			T35	1		T174	2		T77	2
all_values[6]	auto[0]	auto[1]	auto[1]	94	1			T49	2		T46	2		T35	2
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T49	2		T46	5		T35	1
all_values[6]	auto[1]	auto[1]	auto[1]	79	1			T46	1		T35	3		T237	1
all_values[7]	auto[0]	auto[0]	auto[0]	60	1			T46	4		T35	2		T174	1
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T49	3		T46	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T49	1		T46	1		T35	1
all_values[7]	auto[0]	auto[1]	auto[1]	103	1			T49	4		T46	4		T35	2
all_values[7]	auto[1]	auto[0]	auto[1]	97	1			T49	1		T46	3		T35	1
all_values[7]	auto[1]	auto[1]	auto[1]	90	1			T49	2		T46	2		T35	4
all_values[8]	auto[0]	auto[0]	auto[0]	55	1			T46	1		T174	2		T37	2
all_values[8]	auto[0]	auto[0]	auto[1]	95	1			T49	4		T46	3		T35	4
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T49	1		T174	2		T246	2
all_values[8]	auto[0]	auto[1]	auto[1]	88	1			T49	2		T46	5		T35	6
all_values[8]	auto[1]	auto[0]	auto[1]	96	1			T49	2		T46	2		T237	1
all_values[8]	auto[1]	auto[1]	auto[1]	103	1			T49	2		T46	4		T35	1
all_values[9]	auto[0]	auto[0]	auto[0]	34	1			T37	2		T205	1		T191	1
all_values[9]	auto[0]	auto[0]	auto[1]	106	1			T49	3		T46	7		T35	2
all_values[9]	auto[0]	auto[1]	auto[0]	35	1			T246	1		T244	1		T247	2
all_values[9]	auto[0]	auto[1]	auto[1]	91	1			T49	3		T46	2		T35	1
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T49	2		T46	3		T35	3
all_values[9]	auto[1]	auto[1]	auto[1]	93	1			T49	3		T46	3		T35	5
all_values[10]	auto[0]	auto[0]	auto[0]	49	1			T46	3		T35	2		T174	4
all_values[10]	auto[0]	auto[0]	auto[1]	106	1			T49	3		T46	5		T35	5
all_values[10]	auto[0]	auto[1]	auto[0]	38	1			T46	2		T35	1		T37	1
all_values[10]	auto[0]	auto[1]	auto[1]	90	1			T49	5		T237	2		T77	1
all_values[10]	auto[1]	auto[0]	auto[1]	95	1			T49	1		T46	1		T35	1
all_values[10]	auto[1]	auto[1]	auto[1]	87	1			T49	2		T46	4		T35	2
all_values[11]	auto[0]	auto[0]	auto[0]	66	1			T46	3		T174	2		T205	2
all_values[11]	auto[0]	auto[0]	auto[1]	98	1			T49	4		T46	4		T35	5
all_values[11]	auto[0]	auto[1]	auto[0]	28	1			T46	2		T237	1		T205	2
all_values[11]	auto[0]	auto[1]	auto[1]	94	1			T49	2		T46	4		T35	1
all_values[11]	auto[1]	auto[0]	auto[1]	102	1			T49	3		T46	2		T35	2
all_values[11]	auto[1]	auto[1]	auto[1]	77	1			T49	2		T35	3		T174	1
all_values[12]	auto[0]	auto[0]	auto[0]	48	1			T49	1		T237	1		T244	3
all_values[12]	auto[0]	auto[0]	auto[1]	90	1			T49	3		T46	3		T35	5
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T49	1		T249	1		T250	1
all_values[12]	auto[0]	auto[1]	auto[1]	100	1			T49	3		T46	5		T35	4
all_values[12]	auto[1]	auto[0]	auto[1]	90	1			T46	2		T174	1		T237	1
all_values[12]	auto[1]	auto[1]	auto[1]	108	1			T49	3		T46	5		T35	2
all_values[13]	auto[0]	auto[0]	auto[0]	53	1			T49	1		T46	1		T174	1
all_values[13]	auto[0]	auto[0]	auto[1]	102	1			T49	1		T46	8		T35	4
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T49	6		T205	2		T244	1
all_values[13]	auto[0]	auto[1]	auto[1]	106	1			T49	1		T35	4		T37	1
all_values[13]	auto[1]	auto[0]	auto[1]	93	1			T46	3		T35	2		T174	2
all_values[13]	auto[1]	auto[1]	auto[1]	83	1			T49	2		T46	3		T35	1
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T49	1		T46	2		T205	1
all_values[14]	auto[0]	auto[0]	auto[1]	77	1			T49	2		T46	1		T35	4
all_values[14]	auto[0]	auto[1]	auto[0]	36	1			T49	3		T46	2		T37	4
all_values[14]	auto[0]	auto[1]	auto[1]	115	1			T49	3		T46	5		T35	1
all_values[14]	auto[1]	auto[0]	auto[1]	100	1			T46	4		T35	3		T174	2
all_values[14]	auto[1]	auto[1]	auto[1]	88	1			T49	2		T46	1		T35	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal