Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.46 97.12 91.21 97.66 83.58 94.37 98.67 91.60


Total test records in report: 1472
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1309 /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3212857919 May 05 01:13:22 PM PDT 24 May 05 01:13:49 PM PDT 24 10066994861 ps
T1310 /workspace/coverage/default/42.i2c_target_stress_rd.2036113151 May 05 01:16:32 PM PDT 24 May 05 01:16:43 PM PDT 24 695613921 ps
T1311 /workspace/coverage/default/21.i2c_host_stress_all.4262841030 May 05 01:12:57 PM PDT 24 May 05 01:19:01 PM PDT 24 15493843006 ps
T1312 /workspace/coverage/default/3.i2c_host_override.2708441004 May 05 01:09:47 PM PDT 24 May 05 01:09:49 PM PDT 24 56870238 ps
T1313 /workspace/coverage/default/30.i2c_target_timeout.394576799 May 05 01:14:42 PM PDT 24 May 05 01:14:50 PM PDT 24 6562445552 ps
T1314 /workspace/coverage/default/4.i2c_target_hrst.2718023435 May 05 01:10:04 PM PDT 24 May 05 01:10:07 PM PDT 24 469142915 ps
T1315 /workspace/coverage/default/42.i2c_target_stress_wr.2983399669 May 05 01:16:31 PM PDT 24 May 05 01:18:55 PM PDT 24 34971174858 ps
T193 /workspace/coverage/default/18.i2c_host_stress_all.1504744110 May 05 01:12:31 PM PDT 24 May 05 01:17:20 PM PDT 24 37196469825 ps
T1316 /workspace/coverage/default/44.i2c_target_fifo_reset_acq.114703790 May 05 01:16:50 PM PDT 24 May 05 01:17:48 PM PDT 24 10085914745 ps
T1317 /workspace/coverage/default/11.i2c_host_fifo_full.1679687559 May 05 01:11:11 PM PDT 24 May 05 01:11:56 PM PDT 24 1827284575 ps
T1318 /workspace/coverage/default/28.i2c_target_smoke.1739280512 May 05 01:14:38 PM PDT 24 May 05 01:14:53 PM PDT 24 18975563972 ps
T1319 /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3190773503 May 05 01:10:07 PM PDT 24 May 05 01:10:10 PM PDT 24 102194294 ps
T1320 /workspace/coverage/default/41.i2c_host_fifo_full.4100440366 May 05 01:16:24 PM PDT 24 May 05 01:16:56 PM PDT 24 4460670878 ps
T1321 /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4020543102 May 05 01:11:15 PM PDT 24 May 05 01:11:37 PM PDT 24 10129503443 ps
T1322 /workspace/coverage/default/13.i2c_host_may_nack.228668579 May 05 01:11:35 PM PDT 24 May 05 01:11:43 PM PDT 24 437591136 ps
T1323 /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1623405343 May 05 01:13:08 PM PDT 24 May 05 01:13:13 PM PDT 24 702088067 ps
T1324 /workspace/coverage/default/36.i2c_host_error_intr.3847094891 May 05 01:15:27 PM PDT 24 May 05 01:15:29 PM PDT 24 516273350 ps
T1325 /workspace/coverage/default/8.i2c_alert_test.2413525324 May 05 01:10:46 PM PDT 24 May 05 01:10:48 PM PDT 24 19032662 ps
T1326 /workspace/coverage/default/36.i2c_host_may_nack.2308486792 May 05 01:15:32 PM PDT 24 May 05 01:15:48 PM PDT 24 779051641 ps
T120 /workspace/coverage/default/1.i2c_sec_cm.30236747 May 05 01:09:33 PM PDT 24 May 05 01:09:35 PM PDT 24 120557869 ps
T1327 /workspace/coverage/default/43.i2c_host_may_nack.1659787168 May 05 01:16:39 PM PDT 24 May 05 01:16:47 PM PDT 24 1028360092 ps
T1328 /workspace/coverage/default/16.i2c_host_error_intr.620738836 May 05 01:12:22 PM PDT 24 May 05 01:12:23 PM PDT 24 216173142 ps
T1329 /workspace/coverage/default/37.i2c_host_error_intr.2476636262 May 05 01:15:38 PM PDT 24 May 05 01:15:40 PM PDT 24 67061076 ps
T1330 /workspace/coverage/default/29.i2c_host_perf.2999728458 May 05 01:14:32 PM PDT 24 May 05 01:14:48 PM PDT 24 1640788060 ps
T1331 /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1155097334 May 05 01:09:55 PM PDT 24 May 05 01:10:13 PM PDT 24 355830357 ps
T1332 /workspace/coverage/default/10.i2c_target_intr_stress_wr.1032244341 May 05 01:11:01 PM PDT 24 May 05 01:11:56 PM PDT 24 11056452565 ps
T1333 /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.391437281 May 05 01:15:15 PM PDT 24 May 05 01:15:21 PM PDT 24 286941137 ps
T1334 /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.166003709 May 05 01:11:27 PM PDT 24 May 05 01:11:29 PM PDT 24 165827099 ps
T1335 /workspace/coverage/default/33.i2c_target_stress_rd.2101030895 May 05 01:15:06 PM PDT 24 May 05 01:15:11 PM PDT 24 334516058 ps
T1336 /workspace/coverage/default/42.i2c_host_may_nack.4257791503 May 05 01:16:32 PM PDT 24 May 05 01:16:39 PM PDT 24 881083255 ps
T1337 /workspace/coverage/default/7.i2c_host_perf.1215569729 May 05 01:10:32 PM PDT 24 May 05 01:11:14 PM PDT 24 5282173612 ps
T1338 /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.689361623 May 05 01:14:42 PM PDT 24 May 05 01:14:44 PM PDT 24 556802893 ps
T1339 /workspace/coverage/default/9.i2c_target_timeout.3887864562 May 05 01:10:49 PM PDT 24 May 05 01:10:57 PM PDT 24 1137600636 ps
T1340 /workspace/coverage/default/46.i2c_host_error_intr.1140534880 May 05 01:17:04 PM PDT 24 May 05 01:17:05 PM PDT 24 79588608 ps
T1341 /workspace/coverage/default/36.i2c_alert_test.1980755313 May 05 01:15:38 PM PDT 24 May 05 01:15:39 PM PDT 24 94365827 ps
T1342 /workspace/coverage/default/16.i2c_host_smoke.1884745326 May 05 01:12:16 PM PDT 24 May 05 01:12:48 PM PDT 24 1402703486 ps
T1343 /workspace/coverage/default/7.i2c_target_bad_addr.1256547722 May 05 01:10:35 PM PDT 24 May 05 01:10:39 PM PDT 24 1639917617 ps
T1344 /workspace/coverage/default/49.i2c_target_hrst.3633562800 May 05 01:17:41 PM PDT 24 May 05 01:17:44 PM PDT 24 855241425 ps
T1345 /workspace/coverage/default/21.i2c_target_intr_stress_wr.3947682997 May 05 01:13:03 PM PDT 24 May 05 01:13:07 PM PDT 24 4757123238 ps
T1346 /workspace/coverage/default/2.i2c_host_fifo_reset_rx.202803189 May 05 01:09:38 PM PDT 24 May 05 01:09:43 PM PDT 24 145566372 ps
T1347 /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3756807021 May 05 01:16:10 PM PDT 24 May 05 01:16:19 PM PDT 24 158041102 ps
T1348 /workspace/coverage/default/44.i2c_target_stress_rd.1173526364 May 05 01:16:44 PM PDT 24 May 05 01:17:03 PM PDT 24 4711520863 ps
T1349 /workspace/coverage/default/13.i2c_host_perf.2158619140 May 05 01:11:28 PM PDT 24 May 05 01:12:10 PM PDT 24 3056243381 ps
T1350 /workspace/coverage/default/9.i2c_host_fifo_overflow.24935426 May 05 01:10:47 PM PDT 24 May 05 01:11:52 PM PDT 24 2200290671 ps
T1351 /workspace/coverage/default/16.i2c_host_stretch_timeout.409874340 May 05 01:12:23 PM PDT 24 May 05 01:12:52 PM PDT 24 2514947383 ps
T1352 /workspace/coverage/default/5.i2c_host_fifo_full.101809848 May 05 01:10:14 PM PDT 24 May 05 01:11:06 PM PDT 24 1495985032 ps
T1353 /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3142680976 May 05 01:10:20 PM PDT 24 May 05 01:10:31 PM PDT 24 193100830 ps
T1354 /workspace/coverage/default/37.i2c_host_stretch_timeout.1179979947 May 05 01:15:37 PM PDT 24 May 05 01:15:46 PM PDT 24 494256610 ps
T194 /workspace/coverage/default/1.i2c_host_stress_all.2548820281 May 05 01:09:25 PM PDT 24 May 05 01:18:48 PM PDT 24 175319986611 ps
T1355 /workspace/coverage/default/7.i2c_host_override.841093178 May 05 01:10:25 PM PDT 24 May 05 01:10:27 PM PDT 24 20017736 ps
T1356 /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2330496560 May 05 01:16:04 PM PDT 24 May 05 01:16:33 PM PDT 24 10100138468 ps
T1357 /workspace/coverage/default/38.i2c_host_override.1796256996 May 05 01:15:42 PM PDT 24 May 05 01:15:43 PM PDT 24 47210076 ps
T1358 /workspace/coverage/default/45.i2c_host_fifo_watermark.2092383106 May 05 01:16:55 PM PDT 24 May 05 01:18:41 PM PDT 24 53249087138 ps
T1359 /workspace/coverage/default/0.i2c_host_override.3020661991 May 05 01:09:19 PM PDT 24 May 05 01:09:20 PM PDT 24 120170423 ps
T1360 /workspace/coverage/default/45.i2c_target_intr_stress_wr.859701224 May 05 01:16:59 PM PDT 24 May 05 01:26:03 PM PDT 24 26056332316 ps
T1361 /workspace/coverage/default/18.i2c_target_smoke.2525264531 May 05 01:12:31 PM PDT 24 May 05 01:13:03 PM PDT 24 5526912556 ps
T1362 /workspace/coverage/default/1.i2c_target_hrst.1269606693 May 05 01:09:32 PM PDT 24 May 05 01:09:36 PM PDT 24 1606861415 ps
T1363 /workspace/coverage/default/14.i2c_target_stretch.1028650624 May 05 01:11:41 PM PDT 24 May 05 01:14:07 PM PDT 24 21558265510 ps
T80 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4139838180 May 05 12:58:30 PM PDT 24 May 05 12:58:31 PM PDT 24 19379534 ps
T81 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3869638501 May 05 12:58:44 PM PDT 24 May 05 12:58:45 PM PDT 24 28503245 ps
T82 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3005426339 May 05 12:58:51 PM PDT 24 May 05 12:58:54 PM PDT 24 124316450 ps
T154 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3028959649 May 05 12:59:00 PM PDT 24 May 05 12:59:02 PM PDT 24 68369793 ps
T114 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1635686711 May 05 12:58:49 PM PDT 24 May 05 12:58:51 PM PDT 24 100087995 ps
T168 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1957536736 May 05 12:58:55 PM PDT 24 May 05 12:58:57 PM PDT 24 29097737 ps
T115 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3766541231 May 05 12:58:55 PM PDT 24 May 05 12:58:57 PM PDT 24 24675279 ps
T130 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3713409089 May 05 12:58:49 PM PDT 24 May 05 12:58:52 PM PDT 24 132646038 ps
T155 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1841026131 May 05 12:58:59 PM PDT 24 May 05 12:59:01 PM PDT 24 43468659 ps
T133 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3704516514 May 05 12:58:59 PM PDT 24 May 05 12:59:02 PM PDT 24 52092626 ps
T129 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.312296746 May 05 12:58:28 PM PDT 24 May 05 12:58:29 PM PDT 24 25290039 ps
T143 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3909013213 May 05 12:58:36 PM PDT 24 May 05 12:58:38 PM PDT 24 230957377 ps
T1364 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2385554554 May 05 12:58:49 PM PDT 24 May 05 12:58:51 PM PDT 24 70388857 ps
T1365 /workspace/coverage/cover_reg_top/31.i2c_intr_test.759030001 May 05 12:59:13 PM PDT 24 May 05 12:59:14 PM PDT 24 17595528 ps
T1366 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1595365160 May 05 12:58:52 PM PDT 24 May 05 12:58:53 PM PDT 24 76506310 ps
T1367 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2641903060 May 05 12:59:14 PM PDT 24 May 05 12:59:15 PM PDT 24 31411907 ps
T131 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3515417973 May 05 12:58:36 PM PDT 24 May 05 12:58:39 PM PDT 24 106161597 ps
T149 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2513788470 May 05 12:59:02 PM PDT 24 May 05 12:59:04 PM PDT 24 136536452 ps
T1368 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1059505897 May 05 12:59:16 PM PDT 24 May 05 12:59:17 PM PDT 24 18445302 ps
T169 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3059703458 May 05 12:59:01 PM PDT 24 May 05 12:59:03 PM PDT 24 97744581 ps
T170 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2593354804 May 05 12:58:50 PM PDT 24 May 05 12:58:51 PM PDT 24 20376490 ps
T132 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4054285230 May 05 12:58:45 PM PDT 24 May 05 12:58:47 PM PDT 24 27156766 ps
T163 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.86759406 May 05 12:58:35 PM PDT 24 May 05 12:58:40 PM PDT 24 140749575 ps
T1369 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1416778737 May 05 12:58:36 PM PDT 24 May 05 12:58:37 PM PDT 24 51733699 ps
T145 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.335131573 May 05 12:58:50 PM PDT 24 May 05 12:58:53 PM PDT 24 1594548900 ps
T138 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1508057944 May 05 12:58:50 PM PDT 24 May 05 12:58:51 PM PDT 24 111325695 ps
T1370 /workspace/coverage/cover_reg_top/19.i2c_intr_test.60481745 May 05 12:59:01 PM PDT 24 May 05 12:59:03 PM PDT 24 45411728 ps
T171 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.696278950 May 05 12:58:52 PM PDT 24 May 05 12:58:54 PM PDT 24 69095237 ps
T172 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2754785338 May 05 12:58:27 PM PDT 24 May 05 12:58:28 PM PDT 24 55870136 ps
T1371 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1471845923 May 05 12:59:12 PM PDT 24 May 05 12:59:14 PM PDT 24 133170721 ps
T156 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.377269871 May 05 12:58:48 PM PDT 24 May 05 12:58:49 PM PDT 24 18735054 ps
T1372 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3455012679 May 05 12:58:25 PM PDT 24 May 05 12:58:26 PM PDT 24 20002690 ps
T157 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2060757843 May 05 12:58:36 PM PDT 24 May 05 12:58:38 PM PDT 24 121461182 ps
T164 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1216893334 May 05 12:58:36 PM PDT 24 May 05 12:58:41 PM PDT 24 679257972 ps
T158 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1591189881 May 05 12:58:50 PM PDT 24 May 05 12:58:52 PM PDT 24 19942645 ps
T173 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.178458253 May 05 12:58:28 PM PDT 24 May 05 12:58:30 PM PDT 24 32953261 ps
T255 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2921067050 May 05 12:58:27 PM PDT 24 May 05 12:58:28 PM PDT 24 44330459 ps
T151 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2085996090 May 05 12:58:51 PM PDT 24 May 05 12:58:53 PM PDT 24 221448855 ps
T159 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1621484805 May 05 12:58:35 PM PDT 24 May 05 12:58:36 PM PDT 24 51085022 ps
T1373 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2188841899 May 05 12:58:49 PM PDT 24 May 05 12:58:51 PM PDT 24 76632641 ps
T134 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.423235693 May 05 12:58:33 PM PDT 24 May 05 12:58:35 PM PDT 24 184504650 ps
T175 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.522132549 May 05 12:58:37 PM PDT 24 May 05 12:58:39 PM PDT 24 251404065 ps
T1374 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1949597603 May 05 12:59:10 PM PDT 24 May 05 12:59:11 PM PDT 24 15880149 ps
T160 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2399652414 May 05 12:58:45 PM PDT 24 May 05 12:58:46 PM PDT 24 37586361 ps
T1375 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1899137738 May 05 12:58:40 PM PDT 24 May 05 12:58:43 PM PDT 24 73288848 ps
T1376 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2114337694 May 05 12:58:49 PM PDT 24 May 05 12:58:50 PM PDT 24 37369008 ps
T148 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1859494460 May 05 12:58:58 PM PDT 24 May 05 12:59:00 PM PDT 24 94118171 ps
T1377 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1954408280 May 05 12:58:51 PM PDT 24 May 05 12:58:53 PM PDT 24 69033141 ps
T1378 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3282400608 May 05 12:59:07 PM PDT 24 May 05 12:59:08 PM PDT 24 31744869 ps
T135 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3212003987 May 05 12:58:56 PM PDT 24 May 05 12:58:59 PM PDT 24 98582684 ps
T1379 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.253400335 May 05 12:58:52 PM PDT 24 May 05 12:58:54 PM PDT 24 23033725 ps
T1380 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2491180430 May 05 12:58:58 PM PDT 24 May 05 12:59:00 PM PDT 24 45574708 ps
T1381 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1577396999 May 05 12:58:56 PM PDT 24 May 05 12:58:59 PM PDT 24 96367275 ps
T1382 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1114103739 May 05 12:58:36 PM PDT 24 May 05 12:58:38 PM PDT 24 15076754 ps
T161 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.86604638 May 05 12:58:35 PM PDT 24 May 05 12:58:36 PM PDT 24 279129735 ps
T1383 /workspace/coverage/cover_reg_top/4.i2c_intr_test.597259751 May 05 12:58:49 PM PDT 24 May 05 12:58:51 PM PDT 24 18040270 ps
T150 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.914697183 May 05 12:59:01 PM PDT 24 May 05 12:59:03 PM PDT 24 81764692 ps
T144 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3729816623 May 05 12:58:49 PM PDT 24 May 05 12:58:50 PM PDT 24 86769771 ps
T176 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1624768260 May 05 12:58:52 PM PDT 24 May 05 12:58:54 PM PDT 24 529959472 ps
T177 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4045720088 May 05 12:58:56 PM PDT 24 May 05 12:58:58 PM PDT 24 46491004 ps
T1384 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2722659254 May 05 12:58:45 PM PDT 24 May 05 12:58:46 PM PDT 24 23477145 ps
T1385 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.324713065 May 05 12:58:45 PM PDT 24 May 05 12:58:47 PM PDT 24 202699115 ps
T136 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.750085909 May 05 12:58:52 PM PDT 24 May 05 12:58:55 PM PDT 24 113288322 ps
T1386 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4012530139 May 05 12:58:38 PM PDT 24 May 05 12:58:39 PM PDT 24 91510710 ps
T1387 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3260549086 May 05 12:59:16 PM PDT 24 May 05 12:59:18 PM PDT 24 27465334 ps
T1388 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3487041802 May 05 12:59:00 PM PDT 24 May 05 12:59:01 PM PDT 24 47426363 ps
T139 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2502157895 May 05 12:58:58 PM PDT 24 May 05 12:59:01 PM PDT 24 343037008 ps
T1389 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2155726831 May 05 12:59:00 PM PDT 24 May 05 12:59:02 PM PDT 24 18805951 ps
T162 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2376349304 May 05 12:58:27 PM PDT 24 May 05 12:58:30 PM PDT 24 77094006 ps
T1390 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3636382560 May 05 12:58:45 PM PDT 24 May 05 12:58:46 PM PDT 24 105240016 ps
T1391 /workspace/coverage/cover_reg_top/43.i2c_intr_test.193170143 May 05 12:59:13 PM PDT 24 May 05 12:59:14 PM PDT 24 21372154 ps
T137 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2078916926 May 05 12:58:39 PM PDT 24 May 05 12:58:42 PM PDT 24 103008055 ps
T1392 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1079059588 May 05 12:58:55 PM PDT 24 May 05 12:58:57 PM PDT 24 90395656 ps
T1393 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1473755805 May 05 12:59:06 PM PDT 24 May 05 12:59:07 PM PDT 24 14903422 ps
T1394 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1116153701 May 05 12:59:08 PM PDT 24 May 05 12:59:09 PM PDT 24 35953723 ps
T1395 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2533335034 May 05 12:58:58 PM PDT 24 May 05 12:59:00 PM PDT 24 29683178 ps
T204 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3662108555 May 05 12:58:39 PM PDT 24 May 05 12:58:41 PM PDT 24 264947900 ps
T1396 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3280693837 May 05 12:59:00 PM PDT 24 May 05 12:59:01 PM PDT 24 26087158 ps
T146 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3900145692 May 05 12:58:26 PM PDT 24 May 05 12:58:29 PM PDT 24 158966595 ps
T1397 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2331272806 May 05 12:58:49 PM PDT 24 May 05 12:58:50 PM PDT 24 16868358 ps
T1398 /workspace/coverage/cover_reg_top/18.i2c_intr_test.354105603 May 05 12:59:00 PM PDT 24 May 05 12:59:01 PM PDT 24 18101631 ps
T1399 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2777080649 May 05 12:58:23 PM PDT 24 May 05 12:58:25 PM PDT 24 54752339 ps
T1400 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1001100105 May 05 12:58:22 PM PDT 24 May 05 12:58:23 PM PDT 24 53907859 ps
T1401 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1020648244 May 05 12:58:36 PM PDT 24 May 05 12:58:37 PM PDT 24 21633769 ps
T1402 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1133123903 May 05 12:59:15 PM PDT 24 May 05 12:59:16 PM PDT 24 17212306 ps
T1403 /workspace/coverage/cover_reg_top/42.i2c_intr_test.4192918254 May 05 12:59:13 PM PDT 24 May 05 12:59:14 PM PDT 24 172399923 ps
T1404 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1511693352 May 05 12:58:27 PM PDT 24 May 05 12:58:28 PM PDT 24 55788928 ps
T1405 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3717538935 May 05 12:59:10 PM PDT 24 May 05 12:59:11 PM PDT 24 66898842 ps
T1406 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2084804943 May 05 12:59:13 PM PDT 24 May 05 12:59:15 PM PDT 24 124065436 ps
T1407 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3489017552 May 05 12:59:04 PM PDT 24 May 05 12:59:06 PM PDT 24 98904002 ps
T1408 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3848787786 May 05 12:58:43 PM PDT 24 May 05 12:58:45 PM PDT 24 271285210 ps
T1409 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1204791702 May 05 12:59:01 PM PDT 24 May 05 12:59:03 PM PDT 24 67540704 ps
T1410 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3808095785 May 05 12:58:46 PM PDT 24 May 05 12:58:48 PM PDT 24 30134541 ps
T1411 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2106779198 May 05 12:59:10 PM PDT 24 May 05 12:59:12 PM PDT 24 78710206 ps
T1412 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2273410630 May 05 12:58:52 PM PDT 24 May 05 12:58:53 PM PDT 24 88384804 ps
T1413 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3662205054 May 05 12:58:58 PM PDT 24 May 05 12:59:00 PM PDT 24 23019049 ps
T1414 /workspace/coverage/cover_reg_top/11.i2c_intr_test.201162677 May 05 12:58:56 PM PDT 24 May 05 12:58:58 PM PDT 24 18985459 ps
T1415 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.973478694 May 05 12:58:36 PM PDT 24 May 05 12:58:38 PM PDT 24 125321323 ps
T1416 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2431511833 May 05 12:59:03 PM PDT 24 May 05 12:59:06 PM PDT 24 119946515 ps
T1417 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3690229090 May 05 12:59:12 PM PDT 24 May 05 12:59:13 PM PDT 24 30729379 ps
T1418 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1537851850 May 05 12:58:51 PM PDT 24 May 05 12:58:53 PM PDT 24 80933435 ps
T1419 /workspace/coverage/cover_reg_top/24.i2c_intr_test.3573752282 May 05 12:59:06 PM PDT 24 May 05 12:59:07 PM PDT 24 35292047 ps
T1420 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1342682671 May 05 12:58:50 PM PDT 24 May 05 12:58:52 PM PDT 24 19010213 ps
T1421 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3053439136 May 05 12:58:56 PM PDT 24 May 05 12:58:58 PM PDT 24 70239607 ps
T1422 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3835971932 May 05 12:59:15 PM PDT 24 May 05 12:59:16 PM PDT 24 18759023 ps
T1423 /workspace/coverage/cover_reg_top/17.i2c_intr_test.787198723 May 05 12:59:01 PM PDT 24 May 05 12:59:02 PM PDT 24 15317707 ps
T140 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2874212193 May 05 12:58:25 PM PDT 24 May 05 12:58:27 PM PDT 24 88715419 ps
T1424 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3658653193 May 05 12:59:00 PM PDT 24 May 05 12:59:03 PM PDT 24 172024552 ps
T141 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1789689379 May 05 12:58:59 PM PDT 24 May 05 12:59:01 PM PDT 24 231371718 ps
T1425 /workspace/coverage/cover_reg_top/27.i2c_intr_test.61946317 May 05 12:59:09 PM PDT 24 May 05 12:59:10 PM PDT 24 58316874 ps
T152 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.253213101 May 05 12:58:49 PM PDT 24 May 05 12:58:52 PM PDT 24 295532660 ps
T1426 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2488282132 May 05 12:59:12 PM PDT 24 May 05 12:59:13 PM PDT 24 24700028 ps
T1427 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1329119265 May 05 12:59:08 PM PDT 24 May 05 12:59:09 PM PDT 24 37780358 ps
T1428 /workspace/coverage/cover_reg_top/37.i2c_intr_test.493404808 May 05 12:59:11 PM PDT 24 May 05 12:59:12 PM PDT 24 47877853 ps
T1429 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3472752380 May 05 12:58:59 PM PDT 24 May 05 12:59:00 PM PDT 24 19136971 ps
T1430 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2357658952 May 05 12:59:11 PM PDT 24 May 05 12:59:13 PM PDT 24 22086836 ps
T1431 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4080760608 May 05 12:58:52 PM PDT 24 May 05 12:58:54 PM PDT 24 460237426 ps
T142 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1763828798 May 05 12:58:33 PM PDT 24 May 05 12:58:36 PM PDT 24 551760310 ps
T1432 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1106136525 May 05 12:58:56 PM PDT 24 May 05 12:58:58 PM PDT 24 83845818 ps
T1433 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4120167657 May 05 12:58:45 PM PDT 24 May 05 12:58:47 PM PDT 24 26630380 ps
T153 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.276324588 May 05 12:58:36 PM PDT 24 May 05 12:58:38 PM PDT 24 381644033 ps
T1434 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.600957609 May 05 12:58:47 PM PDT 24 May 05 12:58:48 PM PDT 24 33541542 ps
T147 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3935475731 May 05 12:58:45 PM PDT 24 May 05 12:58:47 PM PDT 24 50772699 ps
T1435 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1872217705 May 05 12:58:35 PM PDT 24 May 05 12:58:38 PM PDT 24 95428307 ps
T1436 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.242891725 May 05 12:58:57 PM PDT 24 May 05 12:59:00 PM PDT 24 152734683 ps
T1437 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1982197303 May 05 12:58:58 PM PDT 24 May 05 12:59:01 PM PDT 24 213124745 ps
T1438 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4081715583 May 05 12:59:10 PM PDT 24 May 05 12:59:11 PM PDT 24 42593888 ps
T1439 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.990090343 May 05 12:58:47 PM PDT 24 May 05 12:58:50 PM PDT 24 51812453 ps
T1440 /workspace/coverage/cover_reg_top/49.i2c_intr_test.728817252 May 05 12:59:13 PM PDT 24 May 05 12:59:15 PM PDT 24 22604487 ps
T1441 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3852317729 May 05 12:58:47 PM PDT 24 May 05 12:58:48 PM PDT 24 21925165 ps
T1442 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.988478887 May 05 12:59:02 PM PDT 24 May 05 12:59:04 PM PDT 24 97399659 ps
T1443 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2437212372 May 05 12:58:46 PM PDT 24 May 05 12:58:47 PM PDT 24 17715646 ps
T1444 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1011880047 May 05 12:58:35 PM PDT 24 May 05 12:58:36 PM PDT 24 63033045 ps
T1445 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.4019058922 May 05 12:58:55 PM PDT 24 May 05 12:58:56 PM PDT 24 25723403 ps
T1446 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2691978472 May 05 12:58:44 PM PDT 24 May 05 12:58:47 PM PDT 24 278885391 ps
T1447 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1088646108 May 05 12:59:09 PM PDT 24 May 05 12:59:11 PM PDT 24 28142067 ps
T1448 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3301915099 May 05 12:58:35 PM PDT 24 May 05 12:58:39 PM PDT 24 1108173868 ps
T1449 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3246936735 May 05 12:59:11 PM PDT 24 May 05 12:59:12 PM PDT 24 18651747 ps
T1450 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2792203474 May 05 12:59:21 PM PDT 24 May 05 12:59:22 PM PDT 24 49654067 ps
T165 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4183691772 May 05 12:58:28 PM PDT 24 May 05 12:58:29 PM PDT 24 19165231 ps
T1451 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2970802240 May 05 12:59:04 PM PDT 24 May 05 12:59:07 PM PDT 24 648397939 ps
T1452 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1726841794 May 05 12:59:00 PM PDT 24 May 05 12:59:02 PM PDT 24 207224416 ps
T1453 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.480147280 May 05 12:59:01 PM PDT 24 May 05 12:59:02 PM PDT 24 35385020 ps
T1454 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.391192359 May 05 12:59:03 PM PDT 24 May 05 12:59:05 PM PDT 24 184160251 ps
T1455 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1082219186 May 05 12:58:59 PM PDT 24 May 05 12:59:01 PM PDT 24 74528523 ps
T1456 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1229107640 May 05 12:58:55 PM PDT 24 May 05 12:58:56 PM PDT 24 19853878 ps
T1457 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2612118621 May 05 12:58:25 PM PDT 24 May 05 12:58:27 PM PDT 24 334810242 ps
T1458 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3939420424 May 05 12:58:57 PM PDT 24 May 05 12:58:58 PM PDT 24 39125263 ps
T1459 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.272160721 May 05 12:58:56 PM PDT 24 May 05 12:58:58 PM PDT 24 344952237 ps
T166 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.4145121124 May 05 12:58:58 PM PDT 24 May 05 12:58:59 PM PDT 24 56031489 ps
T1460 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3577729347 May 05 12:59:00 PM PDT 24 May 05 12:59:01 PM PDT 24 112608558 ps
T1461 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3029905429 May 05 12:58:25 PM PDT 24 May 05 12:58:26 PM PDT 24 63257428 ps
T1462 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1353898222 May 05 12:59:14 PM PDT 24 May 05 12:59:15 PM PDT 24 19246851 ps
T167 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1423565298 May 05 12:58:36 PM PDT 24 May 05 12:58:37 PM PDT 24 29813395 ps
T1463 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.843462879 May 05 12:59:01 PM PDT 24 May 05 12:59:03 PM PDT 24 157403703 ps
T1464 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1376555362 May 05 12:58:50 PM PDT 24 May 05 12:58:52 PM PDT 24 30241661 ps
T1465 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1124140392 May 05 12:59:16 PM PDT 24 May 05 12:59:18 PM PDT 24 31958080 ps
T1466 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3614641432 May 05 12:59:13 PM PDT 24 May 05 12:59:14 PM PDT 24 31027329 ps
T1467 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3285463786 May 05 12:59:02 PM PDT 24 May 05 12:59:04 PM PDT 24 106018713 ps
T1468 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3965815832 May 05 12:59:00 PM PDT 24 May 05 12:59:01 PM PDT 24 52394142 ps
T1469 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3017306480 May 05 12:58:52 PM PDT 24 May 05 12:58:53 PM PDT 24 42874743 ps
T1470 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2534935768 May 05 12:58:22 PM PDT 24 May 05 12:58:24 PM PDT 24 45426136 ps
T1471 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1258741855 May 05 12:59:02 PM PDT 24 May 05 12:59:04 PM PDT 24 102740303 ps
T1472 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1578713006 May 05 12:58:56 PM PDT 24 May 05 12:58:57 PM PDT 24 37219682 ps

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3118883265
Short name T10
Test name
Test status
Simulation time 1702176020 ps
CPU time 83.07 seconds
Started May 05 01:11:39 PM PDT 24
Finished May 05 01:13:02 PM PDT 24
Peak memory 418288 kb
Host smart-76c4aba3-b35e-436c-ba2b-f1cd228ff41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118883265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3118883265
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1463423341
Short name T11
Test name
Test status
Simulation time 696876229 ps
CPU time 2.31 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:14:44 PM PDT 24
Peak memory 203852 kb
Host smart-735d821b-88b4-4fa6-a403-a14e811f789a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463423341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1463423341
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.3209385206
Short name T49
Test name
Test status
Simulation time 40844691054 ps
CPU time 374.31 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:18:38 PM PDT 24
Peak memory 1209224 kb
Host smart-fa9cfa45-c31f-4a89-9649-ade4839bbd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209385206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.3209385206
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2886926854
Short name T12
Test name
Test status
Simulation time 10353885755 ps
CPU time 9.31 seconds
Started May 05 01:09:25 PM PDT 24
Finished May 05 01:09:35 PM PDT 24
Peak memory 212332 kb
Host smart-234ad66d-cdb6-434a-97c2-97e2453251b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886926854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2886926854
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3515417973
Short name T131
Test name
Test status
Simulation time 106161597 ps
CPU time 1.9 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:39 PM PDT 24
Peak memory 203868 kb
Host smart-36c31380-9023-4ed2-b7b9-b0b06c633ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515417973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3515417973
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.694621868
Short name T116
Test name
Test status
Simulation time 39474365 ps
CPU time 0.86 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 221336 kb
Host smart-b69fd77c-781a-4f06-8c97-51aec0f19205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694621868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.694621868
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3100007427
Short name T27
Test name
Test status
Simulation time 10573166089 ps
CPU time 16.55 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:13:20 PM PDT 24
Peak memory 265676 kb
Host smart-fa41a5d2-090f-4bf2-a749-8c23a4e11977
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100007427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3100007427
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_host_override.910289341
Short name T9
Test name
Test status
Simulation time 30361337 ps
CPU time 0.68 seconds
Started May 05 01:11:07 PM PDT 24
Finished May 05 01:11:08 PM PDT 24
Peak memory 203632 kb
Host smart-56d098a8-64f5-4a3b-9505-68990ed56bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910289341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.910289341
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.2306608118
Short name T35
Test name
Test status
Simulation time 52899743223 ps
CPU time 365.82 seconds
Started May 05 01:12:50 PM PDT 24
Finished May 05 01:18:56 PM PDT 24
Peak memory 789872 kb
Host smart-249c5a99-31ff-40b8-b572-53ff600f49f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306608118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.2306608118
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1841026131
Short name T155
Test name
Test status
Simulation time 43468659 ps
CPU time 0.75 seconds
Started May 05 12:58:59 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203660 kb
Host smart-cfdb592b-4c0d-4628-96e2-56fc1dd61747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841026131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1841026131
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.3796138947
Short name T214
Test name
Test status
Simulation time 365522756 ps
CPU time 15.58 seconds
Started May 05 01:12:27 PM PDT 24
Finished May 05 01:12:43 PM PDT 24
Peak memory 203908 kb
Host smart-ccd71288-3ca0-4626-b9f6-f24f0b61cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796138947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3796138947
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1446941154
Short name T77
Test name
Test status
Simulation time 44217402843 ps
CPU time 58.91 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:11:49 PM PDT 24
Peak memory 501684 kb
Host smart-bf47316a-e7b3-4c1f-873f-24981793160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446941154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1446941154
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3087394983
Short name T16
Test name
Test status
Simulation time 41410554368 ps
CPU time 111.44 seconds
Started May 05 01:14:05 PM PDT 24
Finished May 05 01:15:57 PM PDT 24
Peak memory 1724760 kb
Host smart-e0fe8b15-bf14-4679-9a00-e72e9b8491d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087394983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3087394983
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2741291385
Short name T238
Test name
Test status
Simulation time 1191930075 ps
CPU time 6.49 seconds
Started May 05 01:09:46 PM PDT 24
Finished May 05 01:09:53 PM PDT 24
Peak memory 219596 kb
Host smart-e9bdce24-8e73-4517-914a-4fd40116f214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741291385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2741291385
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3005426339
Short name T82
Test name
Test status
Simulation time 124316450 ps
CPU time 2.16 seconds
Started May 05 12:58:51 PM PDT 24
Finished May 05 12:58:54 PM PDT 24
Peak memory 203864 kb
Host smart-2c61727c-4fca-45b6-9d5c-81f271ded53f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005426339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3005426339
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2628364581
Short name T25
Test name
Test status
Simulation time 2781075051 ps
CPU time 3.96 seconds
Started May 05 01:11:32 PM PDT 24
Finished May 05 01:11:37 PM PDT 24
Peak memory 212124 kb
Host smart-23c0e613-69fb-4fdc-a6df-35269f72ebeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628364581 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2628364581
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2189571588
Short name T211
Test name
Test status
Simulation time 297347246 ps
CPU time 1.01 seconds
Started May 05 01:17:01 PM PDT 24
Finished May 05 01:17:02 PM PDT 24
Peak memory 203792 kb
Host smart-c90bdc58-587c-4d36-bbf2-32529fb4798b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189571588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2189571588
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.57313115
Short name T52
Test name
Test status
Simulation time 10880958733 ps
CPU time 1109.51 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:28:18 PM PDT 24
Peak memory 1895872 kb
Host smart-8ecd147a-60ee-420c-b0a3-b4e876df1ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57313115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.57313115
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.693803138
Short name T47
Test name
Test status
Simulation time 669459940 ps
CPU time 2.78 seconds
Started May 05 01:11:11 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 203812 kb
Host smart-cbe7659f-79af-4acb-933f-7ecdcf6c4904
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693803138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
693803138
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1670344845
Short name T192
Test name
Test status
Simulation time 12929392686 ps
CPU time 337.53 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:19:18 PM PDT 24
Peak memory 1702496 kb
Host smart-30d62ba0-b089-4115-82a8-2c8c96692175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670344845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1670344845
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_alert_test.4105161277
Short name T113
Test name
Test status
Simulation time 39545843 ps
CPU time 0.61 seconds
Started May 05 01:09:22 PM PDT 24
Finished May 05 01:09:23 PM PDT 24
Peak memory 203656 kb
Host smart-ebc83c99-7f17-49ef-acab-7373d76c333f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105161277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.4105161277
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.2690412426
Short name T216
Test name
Test status
Simulation time 10773910756 ps
CPU time 6.58 seconds
Started May 05 01:14:47 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 203936 kb
Host smart-c4dccf29-ef68-49cd-b9cc-c652c9881918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690412426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.2690412426
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2175680056
Short name T184
Test name
Test status
Simulation time 2791602651 ps
CPU time 64.41 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:10:53 PM PDT 24
Peak memory 890776 kb
Host smart-ebb41cc2-df14-46bf-8ee5-cdc23a75db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175680056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2175680056
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2316161598
Short name T207
Test name
Test status
Simulation time 10459025243 ps
CPU time 14.24 seconds
Started May 05 01:09:30 PM PDT 24
Finished May 05 01:09:46 PM PDT 24
Peak memory 253892 kb
Host smart-bd36e0b4-4188-4d23-b323-e790f9b589b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316161598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2316161598
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.955933165
Short name T109
Test name
Test status
Simulation time 6751892717 ps
CPU time 59.63 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:10:47 PM PDT 24
Peak memory 626044 kb
Host smart-72b3c6b2-6d2a-42d9-a0ee-2bd6bb48d150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955933165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.955933165
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.312696750
Short name T106
Test name
Test status
Simulation time 6514702112 ps
CPU time 17.1 seconds
Started May 05 01:11:05 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 203864 kb
Host smart-2aee2811-1c55-4a54-8e19-312044266c66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312696750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.312696750
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2259086981
Short name T87
Test name
Test status
Simulation time 10095157658 ps
CPU time 77.46 seconds
Started May 05 01:12:29 PM PDT 24
Finished May 05 01:13:47 PM PDT 24
Peak memory 508684 kb
Host smart-a5d1ccdd-4134-44d2-92f1-411689fd2c06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259086981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2259086981
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3357329286
Short name T222
Test name
Test status
Simulation time 108356069 ps
CPU time 1.53 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:47 PM PDT 24
Peak memory 220252 kb
Host smart-7ecdfcc5-6570-48d5-8c6b-9a6b4a2c9457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357329286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3357329286
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.4118342130
Short name T190
Test name
Test status
Simulation time 9589065503 ps
CPU time 287.21 seconds
Started May 05 01:15:05 PM PDT 24
Finished May 05 01:19:53 PM PDT 24
Peak memory 2028112 kb
Host smart-a4034b73-d7e7-4130-a3d8-93b8183cfd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118342130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.4118342130
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3662108555
Short name T204
Test name
Test status
Simulation time 264947900 ps
CPU time 2.4 seconds
Started May 05 12:58:39 PM PDT 24
Finished May 05 12:58:41 PM PDT 24
Peak memory 203956 kb
Host smart-afbc1927-434a-4f75-93e9-43008fecfd67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662108555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3662108555
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.4285076290
Short name T38
Test name
Test status
Simulation time 1912791164 ps
CPU time 21.41 seconds
Started May 05 01:14:56 PM PDT 24
Finished May 05 01:15:18 PM PDT 24
Peak memory 260344 kb
Host smart-efc7fbaf-c00b-4f5f-9fc0-82953f890daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285076290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.4285076290
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1714801954
Short name T56
Test name
Test status
Simulation time 10032182940 ps
CPU time 65.64 seconds
Started May 05 01:10:44 PM PDT 24
Finished May 05 01:11:50 PM PDT 24
Peak memory 502536 kb
Host smart-aeeedb34-09b5-4df6-8bd2-a62cb4ddec41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714801954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1714801954
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.276324588
Short name T153
Test name
Test status
Simulation time 381644033 ps
CPU time 2.03 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203840 kb
Host smart-53febb0f-a7fe-44a7-8122-80e582abce64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276324588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.276324588
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3577074568
Short name T1011
Test name
Test status
Simulation time 3801221326 ps
CPU time 44.91 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:12:13 PM PDT 24
Peak memory 295616 kb
Host smart-b3d0223d-9de3-4cc8-ba67-dc7424404b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577074568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3577074568
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1763828798
Short name T142
Test name
Test status
Simulation time 551760310 ps
CPU time 2.51 seconds
Started May 05 12:58:33 PM PDT 24
Finished May 05 12:58:36 PM PDT 24
Peak memory 203796 kb
Host smart-9bcab64e-3982-4976-8f25-707cb44231d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763828798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1763828798
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/24.i2c_host_perf.811804125
Short name T939
Test name
Test status
Simulation time 2165681099 ps
CPU time 102.75 seconds
Started May 05 01:13:31 PM PDT 24
Finished May 05 01:15:14 PM PDT 24
Peak memory 445596 kb
Host smart-ae30a548-bd48-46e2-8507-473b9139008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811804125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.811804125
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2921067050
Short name T255
Test name
Test status
Simulation time 44330459 ps
CPU time 0.77 seconds
Started May 05 12:58:27 PM PDT 24
Finished May 05 12:58:28 PM PDT 24
Peak memory 203728 kb
Host smart-9f85ec08-b6e5-4a26-a8a4-294bca52b1dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921067050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2921067050
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3188143364
Short name T127
Test name
Test status
Simulation time 2881544942 ps
CPU time 165.66 seconds
Started May 05 01:09:40 PM PDT 24
Finished May 05 01:12:26 PM PDT 24
Peak memory 761708 kb
Host smart-934b7f57-616c-4d29-9727-66b97dc1e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188143364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3188143364
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.835678446
Short name T1290
Test name
Test status
Simulation time 10260666544 ps
CPU time 9.73 seconds
Started May 05 01:11:20 PM PDT 24
Finished May 05 01:11:31 PM PDT 24
Peak memory 250596 kb
Host smart-86ec3347-6768-4b9c-8714-87f4109e6771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835678446 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.835678446
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.4063091983
Short name T224
Test name
Test status
Simulation time 2004581732 ps
CPU time 2.95 seconds
Started May 05 01:11:41 PM PDT 24
Finished May 05 01:11:45 PM PDT 24
Peak memory 203848 kb
Host smart-73a96785-eec6-459f-bedc-3ea4dd64e885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063091983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.4063091983
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.278798988
Short name T102
Test name
Test status
Simulation time 946402440 ps
CPU time 29.93 seconds
Started May 05 01:13:30 PM PDT 24
Finished May 05 01:14:00 PM PDT 24
Peak memory 203780 kb
Host smart-8a839f1d-70f1-4440-ad14-891dd50a9575
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278798988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.278798988
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1038955025
Short name T231
Test name
Test status
Simulation time 9048258501 ps
CPU time 90.34 seconds
Started May 05 01:17:29 PM PDT 24
Finished May 05 01:19:00 PM PDT 24
Peak memory 769676 kb
Host smart-340ce7b2-6d78-4b8d-8eee-7c19bb131bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038955025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1038955025
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3984689827
Short name T59
Test name
Test status
Simulation time 14587135672 ps
CPU time 823.34 seconds
Started May 05 01:11:00 PM PDT 24
Finished May 05 01:24:44 PM PDT 24
Peak memory 2457564 kb
Host smart-b891d235-d4ec-475b-a053-5f58a6def9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984689827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3984689827
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3750887327
Short name T53
Test name
Test status
Simulation time 15389550147 ps
CPU time 714.67 seconds
Started May 05 01:16:28 PM PDT 24
Finished May 05 01:28:24 PM PDT 24
Peak memory 1216224 kb
Host smart-c184a38e-5772-43c7-a37c-e35d9cdad918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750887327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3750887327
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2874212193
Short name T140
Test name
Test status
Simulation time 88715419 ps
CPU time 1.47 seconds
Started May 05 12:58:25 PM PDT 24
Finished May 05 12:58:27 PM PDT 24
Peak memory 203896 kb
Host smart-48730a36-30e1-4a46-a410-5701c8bffddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874212193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2874212193
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2502157895
Short name T139
Test name
Test status
Simulation time 343037008 ps
CPU time 1.99 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203792 kb
Host smart-8986f958-977d-42f6-86d6-b5b39ba85338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502157895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2502157895
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1511693352
Short name T1404
Test name
Test status
Simulation time 55788928 ps
CPU time 1.23 seconds
Started May 05 12:58:27 PM PDT 24
Finished May 05 12:58:28 PM PDT 24
Peak memory 203876 kb
Host smart-dcaa70ce-0972-42fe-958f-009a8c96a7d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511693352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1511693352
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2376349304
Short name T162
Test name
Test status
Simulation time 77094006 ps
CPU time 2.89 seconds
Started May 05 12:58:27 PM PDT 24
Finished May 05 12:58:30 PM PDT 24
Peak memory 203792 kb
Host smart-032a7c7c-f35c-470d-8ac7-08ebbfa927ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376349304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2376349304
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2777080649
Short name T1399
Test name
Test status
Simulation time 54752339 ps
CPU time 1.07 seconds
Started May 05 12:58:23 PM PDT 24
Finished May 05 12:58:25 PM PDT 24
Peak memory 203880 kb
Host smart-2b6c9eda-226e-44e6-b693-192c71c5fc64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777080649 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2777080649
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2534935768
Short name T1470
Test name
Test status
Simulation time 45426136 ps
CPU time 0.78 seconds
Started May 05 12:58:22 PM PDT 24
Finished May 05 12:58:24 PM PDT 24
Peak memory 203748 kb
Host smart-ef75983d-2836-48da-b04c-a6d9933b6842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534935768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2534935768
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1001100105
Short name T1400
Test name
Test status
Simulation time 53907859 ps
CPU time 0.67 seconds
Started May 05 12:58:22 PM PDT 24
Finished May 05 12:58:23 PM PDT 24
Peak memory 203664 kb
Host smart-861c4c11-d200-4367-b16e-c70d59171fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001100105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1001100105
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2754785338
Short name T172
Test name
Test status
Simulation time 55870136 ps
CPU time 1.17 seconds
Started May 05 12:58:27 PM PDT 24
Finished May 05 12:58:28 PM PDT 24
Peak memory 203832 kb
Host smart-6c49e706-a1d3-45fb-9b9e-6735b82ab214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754785338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2754785338
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.312296746
Short name T129
Test name
Test status
Simulation time 25290039 ps
CPU time 1.14 seconds
Started May 05 12:58:28 PM PDT 24
Finished May 05 12:58:29 PM PDT 24
Peak memory 203836 kb
Host smart-7cabb2db-ed0c-46c2-befa-ba9b68ee1ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312296746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.312296746
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2060757843
Short name T157
Test name
Test status
Simulation time 121461182 ps
CPU time 2.05 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203780 kb
Host smart-32d9a9b7-cfb6-41e1-bea0-d9fbe82e2b49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060757843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2060757843
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3301915099
Short name T1448
Test name
Test status
Simulation time 1108173868 ps
CPU time 3.21 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:39 PM PDT 24
Peak memory 203868 kb
Host smart-bc2fd200-7e9d-4156-b1ac-1d0b88a0201a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301915099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3301915099
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3029905429
Short name T1461
Test name
Test status
Simulation time 63257428 ps
CPU time 0.67 seconds
Started May 05 12:58:25 PM PDT 24
Finished May 05 12:58:26 PM PDT 24
Peak memory 203628 kb
Host smart-e82f276c-7897-4f51-9979-52dc090faf64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029905429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3029905429
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.423235693
Short name T134
Test name
Test status
Simulation time 184504650 ps
CPU time 1.05 seconds
Started May 05 12:58:33 PM PDT 24
Finished May 05 12:58:35 PM PDT 24
Peak memory 203788 kb
Host smart-ae2285b0-80bd-4e03-a0a5-12622b3bb4c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423235693 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.423235693
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4183691772
Short name T165
Test name
Test status
Simulation time 19165231 ps
CPU time 0.71 seconds
Started May 05 12:58:28 PM PDT 24
Finished May 05 12:58:29 PM PDT 24
Peak memory 203664 kb
Host smart-430dce62-d288-4ced-86b2-e4fa107c4738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183691772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4183691772
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3455012679
Short name T1372
Test name
Test status
Simulation time 20002690 ps
CPU time 0.67 seconds
Started May 05 12:58:25 PM PDT 24
Finished May 05 12:58:26 PM PDT 24
Peak memory 203624 kb
Host smart-197895d1-180d-47d7-8bf1-1a2b9e5fc1de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455012679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3455012679
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.178458253
Short name T173
Test name
Test status
Simulation time 32953261 ps
CPU time 1.12 seconds
Started May 05 12:58:28 PM PDT 24
Finished May 05 12:58:30 PM PDT 24
Peak memory 203848 kb
Host smart-de5e66f5-1a58-4627-9b68-2a005d7a2ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178458253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.178458253
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2612118621
Short name T1457
Test name
Test status
Simulation time 334810242 ps
CPU time 2.02 seconds
Started May 05 12:58:25 PM PDT 24
Finished May 05 12:58:27 PM PDT 24
Peak memory 203876 kb
Host smart-b190a02a-df3b-4da6-a815-73772676edf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612118621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2612118621
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3900145692
Short name T146
Test name
Test status
Simulation time 158966595 ps
CPU time 2.43 seconds
Started May 05 12:58:26 PM PDT 24
Finished May 05 12:58:29 PM PDT 24
Peak memory 203768 kb
Host smart-85e92678-9357-46b3-8ec3-c6beed74c1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900145692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3900145692
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1537851850
Short name T1418
Test name
Test status
Simulation time 80933435 ps
CPU time 0.78 seconds
Started May 05 12:58:51 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203796 kb
Host smart-77291c66-e53c-40ce-951c-080d46d4c951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537851850 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1537851850
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1342682671
Short name T1420
Test name
Test status
Simulation time 19010213 ps
CPU time 0.82 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:52 PM PDT 24
Peak memory 203716 kb
Host smart-68f3755a-73d1-4281-9ce6-578ef8d95f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342682671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1342682671
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2331272806
Short name T1397
Test name
Test status
Simulation time 16868358 ps
CPU time 0.67 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:50 PM PDT 24
Peak memory 203648 kb
Host smart-3f0412eb-ab48-412f-b1c8-d715c14788a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331272806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2331272806
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1376555362
Short name T1464
Test name
Test status
Simulation time 30241661 ps
CPU time 1.05 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:52 PM PDT 24
Peak memory 203840 kb
Host smart-71e47c34-c0b6-4ff3-a827-196a6f8abaa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376555362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1376555362
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1635686711
Short name T114
Test name
Test status
Simulation time 100087995 ps
CPU time 1.25 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203904 kb
Host smart-e358c189-71bb-453c-b62a-38832f3719c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635686711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1635686711
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3766541231
Short name T115
Test name
Test status
Simulation time 24675279 ps
CPU time 1.02 seconds
Started May 05 12:58:55 PM PDT 24
Finished May 05 12:58:57 PM PDT 24
Peak memory 203720 kb
Host smart-64e72bca-b320-4dfc-ad5e-87e7e8978f9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766541231 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3766541231
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3059703458
Short name T169
Test name
Test status
Simulation time 97744581 ps
CPU time 0.82 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203748 kb
Host smart-ff711b99-cf96-4a35-8c47-d201c8b7159b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059703458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3059703458
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.201162677
Short name T1414
Test name
Test status
Simulation time 18985459 ps
CPU time 0.67 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203636 kb
Host smart-c50947a2-4d1d-4c38-a695-94f915eb8aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201162677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.201162677
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1079059588
Short name T1392
Test name
Test status
Simulation time 90395656 ps
CPU time 1.06 seconds
Started May 05 12:58:55 PM PDT 24
Finished May 05 12:58:57 PM PDT 24
Peak memory 203832 kb
Host smart-12d8192f-7c71-4ea1-88ae-98eac62f5b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079059588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1079059588
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3729816623
Short name T144
Test name
Test status
Simulation time 86769771 ps
CPU time 1.31 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:50 PM PDT 24
Peak memory 203888 kb
Host smart-cb97c6ce-ccb1-4b1a-ad2f-aad298d5a3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729816623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3729816623
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1859494460
Short name T148
Test name
Test status
Simulation time 94118171 ps
CPU time 2.2 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 203768 kb
Host smart-49905ed3-ae7c-48bb-91e4-3921361e1c54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859494460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1859494460
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3939420424
Short name T1458
Test name
Test status
Simulation time 39125263 ps
CPU time 0.93 seconds
Started May 05 12:58:57 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203812 kb
Host smart-13ae654f-59dc-42a8-8638-ba212e9b5999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939420424 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3939420424
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3053439136
Short name T1421
Test name
Test status
Simulation time 70239607 ps
CPU time 0.69 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203740 kb
Host smart-e7273577-eec6-49b2-a500-42f9f015fb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053439136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3053439136
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2155726831
Short name T1389
Test name
Test status
Simulation time 18805951 ps
CPU time 0.62 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203640 kb
Host smart-d63e3e1e-d32c-420b-92f5-f363112390a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155726831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2155726831
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3658653193
Short name T1424
Test name
Test status
Simulation time 172024552 ps
CPU time 1.22 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203816 kb
Host smart-6817287f-852a-4079-94ae-5f0d7f1452fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658653193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3658653193
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1726841794
Short name T1452
Test name
Test status
Simulation time 207224416 ps
CPU time 1.32 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203880 kb
Host smart-b076d329-26d4-417b-9e72-64e3a44b629f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726841794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1726841794
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1789689379
Short name T141
Test name
Test status
Simulation time 231371718 ps
CPU time 1.51 seconds
Started May 05 12:58:59 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203888 kb
Host smart-f8b0211b-cc25-4b11-8976-b69d0d81b562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789689379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1789689379
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4045720088
Short name T177
Test name
Test status
Simulation time 46491004 ps
CPU time 0.78 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203716 kb
Host smart-317fa2a2-840d-4b52-ad3f-be654aabef0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045720088 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.4045720088
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1229107640
Short name T1456
Test name
Test status
Simulation time 19853878 ps
CPU time 0.67 seconds
Started May 05 12:58:55 PM PDT 24
Finished May 05 12:58:56 PM PDT 24
Peak memory 203696 kb
Host smart-7caa73bc-b522-4be0-8ebb-96acc568a4e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229107640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1229107640
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3487041802
Short name T1388
Test name
Test status
Simulation time 47426363 ps
CPU time 0.63 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203652 kb
Host smart-053ae13b-11df-4587-bc49-0fa2dded248e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487041802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3487041802
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2491180430
Short name T1380
Test name
Test status
Simulation time 45574708 ps
CPU time 1.11 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 203840 kb
Host smart-6ca928eb-1931-4fe1-a579-157e08579a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491180430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2491180430
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3212003987
Short name T135
Test name
Test status
Simulation time 98582684 ps
CPU time 2 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:59 PM PDT 24
Peak memory 203920 kb
Host smart-c7c2a988-73c2-412d-8af4-04a25594ae4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212003987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3212003987
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1082219186
Short name T1455
Test name
Test status
Simulation time 74528523 ps
CPU time 0.95 seconds
Started May 05 12:58:59 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203768 kb
Host smart-8b2155b0-50e6-4d7d-be1b-eed118d0c82a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082219186 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1082219186
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1578713006
Short name T1472
Test name
Test status
Simulation time 37219682 ps
CPU time 0.67 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:57 PM PDT 24
Peak memory 203704 kb
Host smart-392f8250-43b9-4b18-9ae6-e8568276ca83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578713006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1578713006
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3280693837
Short name T1396
Test name
Test status
Simulation time 26087158 ps
CPU time 0.67 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203652 kb
Host smart-33d0fc1d-de1d-4c25-8d8b-0d652e85e4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280693837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3280693837
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1957536736
Short name T168
Test name
Test status
Simulation time 29097737 ps
CPU time 1.04 seconds
Started May 05 12:58:55 PM PDT 24
Finished May 05 12:58:57 PM PDT 24
Peak memory 203840 kb
Host smart-3bf56abd-0a4c-439c-8304-aae4cc1b99a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957536736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1957536736
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1982197303
Short name T1437
Test name
Test status
Simulation time 213124745 ps
CPU time 2.54 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203896 kb
Host smart-b212b45e-964e-4063-beb7-bf43caed411c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982197303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1982197303
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3704516514
Short name T133
Test name
Test status
Simulation time 52092626 ps
CPU time 1.4 seconds
Started May 05 12:58:59 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203836 kb
Host smart-bba57878-e2e7-40d2-817a-a57097486ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704516514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3704516514
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2533335034
Short name T1395
Test name
Test status
Simulation time 29683178 ps
CPU time 1.44 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 212344 kb
Host smart-2cdb5745-0f2d-4c2d-a3ef-8c3dde2759f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533335034 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2533335034
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3472752380
Short name T1429
Test name
Test status
Simulation time 19136971 ps
CPU time 0.67 seconds
Started May 05 12:58:59 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 203636 kb
Host smart-8acb6414-1e59-45af-abbf-fa779722a5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472752380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3472752380
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3577729347
Short name T1460
Test name
Test status
Simulation time 112608558 ps
CPU time 0.84 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203696 kb
Host smart-378ec479-f105-49ae-b9cf-5cc3809240c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577729347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3577729347
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.4019058922
Short name T1445
Test name
Test status
Simulation time 25723403 ps
CPU time 1.28 seconds
Started May 05 12:58:55 PM PDT 24
Finished May 05 12:58:56 PM PDT 24
Peak memory 203864 kb
Host smart-5596014f-79ba-4239-ac10-efc0a13aebcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019058922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4019058922
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1577396999
Short name T1381
Test name
Test status
Simulation time 96367275 ps
CPU time 2.22 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:59 PM PDT 24
Peak memory 203952 kb
Host smart-f42c34aa-187c-4304-8dd0-53ae00db2b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577396999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1577396999
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3489017552
Short name T1407
Test name
Test status
Simulation time 98904002 ps
CPU time 1.33 seconds
Started May 05 12:59:04 PM PDT 24
Finished May 05 12:59:06 PM PDT 24
Peak memory 212080 kb
Host smart-30d9e7c4-26b8-473b-a93d-dbc79ac2d038
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489017552 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3489017552
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.4145121124
Short name T166
Test name
Test status
Simulation time 56031489 ps
CPU time 0.75 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:58:59 PM PDT 24
Peak memory 203728 kb
Host smart-9a819de4-2be2-4919-9d3f-09593d92f3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145121124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.4145121124
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1106136525
Short name T1432
Test name
Test status
Simulation time 83845818 ps
CPU time 0.63 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203620 kb
Host smart-4afa3ca8-3404-4594-b487-13b638f3d57a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106136525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1106136525
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3662205054
Short name T1413
Test name
Test status
Simulation time 23019049 ps
CPU time 0.83 seconds
Started May 05 12:58:58 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 203700 kb
Host smart-2069fd0d-a0f8-4c0a-bab7-9518d89e7712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662205054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3662205054
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.272160721
Short name T1459
Test name
Test status
Simulation time 344952237 ps
CPU time 1.2 seconds
Started May 05 12:58:56 PM PDT 24
Finished May 05 12:58:58 PM PDT 24
Peak memory 203792 kb
Host smart-d02fcbd4-4ec5-4bda-bfac-6afa726ec6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272160721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.272160721
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.242891725
Short name T1436
Test name
Test status
Simulation time 152734683 ps
CPU time 2.45 seconds
Started May 05 12:58:57 PM PDT 24
Finished May 05 12:59:00 PM PDT 24
Peak memory 203776 kb
Host smart-7de9a10f-47c7-4adc-9891-9373f9bc0540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242891725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.242891725
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2513788470
Short name T149
Test name
Test status
Simulation time 136536452 ps
CPU time 0.86 seconds
Started May 05 12:59:02 PM PDT 24
Finished May 05 12:59:04 PM PDT 24
Peak memory 203744 kb
Host smart-b5885985-3ec5-4c09-9965-9782531773f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513788470 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2513788470
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3028959649
Short name T154
Test name
Test status
Simulation time 68369793 ps
CPU time 0.79 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203696 kb
Host smart-a6ecda5a-18d2-4722-a88c-c77698cccc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028959649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3028959649
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.787198723
Short name T1423
Test name
Test status
Simulation time 15317707 ps
CPU time 0.65 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203704 kb
Host smart-248c9494-19ca-4f2b-abd0-7bc21fab8d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787198723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.787198723
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1204791702
Short name T1409
Test name
Test status
Simulation time 67540704 ps
CPU time 1.31 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203836 kb
Host smart-63a4ad69-6ca5-4c36-ae3b-4e6ffde02b3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204791702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1204791702
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2431511833
Short name T1416
Test name
Test status
Simulation time 119946515 ps
CPU time 2.14 seconds
Started May 05 12:59:03 PM PDT 24
Finished May 05 12:59:06 PM PDT 24
Peak memory 203872 kb
Host smart-0b14bb31-ccf4-4ba6-bfd7-1e8cb20eba69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431511833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2431511833
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.988478887
Short name T1442
Test name
Test status
Simulation time 97399659 ps
CPU time 1.51 seconds
Started May 05 12:59:02 PM PDT 24
Finished May 05 12:59:04 PM PDT 24
Peak memory 203856 kb
Host smart-0665c4e3-1461-4539-9996-074ce78c2e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988478887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.988478887
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3285463786
Short name T1467
Test name
Test status
Simulation time 106018713 ps
CPU time 1.26 seconds
Started May 05 12:59:02 PM PDT 24
Finished May 05 12:59:04 PM PDT 24
Peak memory 203932 kb
Host smart-d92026e9-7869-427a-8add-0df7381daaaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285463786 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3285463786
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.480147280
Short name T1453
Test name
Test status
Simulation time 35385020 ps
CPU time 0.75 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:02 PM PDT 24
Peak memory 203704 kb
Host smart-b7f9919c-3d43-4cfd-805e-6fd2cfe2877d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480147280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.480147280
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.354105603
Short name T1398
Test name
Test status
Simulation time 18101631 ps
CPU time 0.64 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203640 kb
Host smart-395ed6ab-d576-40d9-ac27-066504f048c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354105603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.354105603
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.843462879
Short name T1463
Test name
Test status
Simulation time 157403703 ps
CPU time 1.21 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203752 kb
Host smart-f6c10efe-97a0-4865-a2d5-1e429f86d1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843462879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.843462879
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.391192359
Short name T1454
Test name
Test status
Simulation time 184160251 ps
CPU time 1.39 seconds
Started May 05 12:59:03 PM PDT 24
Finished May 05 12:59:05 PM PDT 24
Peak memory 203892 kb
Host smart-9fe7155a-d05e-4446-b925-3d3ff5bc2765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391192359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.391192359
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1088646108
Short name T1447
Test name
Test status
Simulation time 28142067 ps
CPU time 0.8 seconds
Started May 05 12:59:09 PM PDT 24
Finished May 05 12:59:11 PM PDT 24
Peak memory 203772 kb
Host smart-4ee0bd6c-e860-4929-aaf9-617e56627d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088646108 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1088646108
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3965815832
Short name T1468
Test name
Test status
Simulation time 52394142 ps
CPU time 0.69 seconds
Started May 05 12:59:00 PM PDT 24
Finished May 05 12:59:01 PM PDT 24
Peak memory 203720 kb
Host smart-4abeb270-2211-44e9-838c-f8686af8e010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965815832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3965815832
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.60481745
Short name T1370
Test name
Test status
Simulation time 45411728 ps
CPU time 0.65 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203580 kb
Host smart-277e1907-0a92-474a-91d4-2db9348276dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60481745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.60481745
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1258741855
Short name T1471
Test name
Test status
Simulation time 102740303 ps
CPU time 1.07 seconds
Started May 05 12:59:02 PM PDT 24
Finished May 05 12:59:04 PM PDT 24
Peak memory 203844 kb
Host smart-8887c300-e93e-425a-a791-8dd705134d91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258741855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1258741855
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2970802240
Short name T1451
Test name
Test status
Simulation time 648397939 ps
CPU time 2.63 seconds
Started May 05 12:59:04 PM PDT 24
Finished May 05 12:59:07 PM PDT 24
Peak memory 203852 kb
Host smart-6772119e-fcb7-4dfa-acd8-c4e2bf07d432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970802240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2970802240
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.914697183
Short name T150
Test name
Test status
Simulation time 81764692 ps
CPU time 1.69 seconds
Started May 05 12:59:01 PM PDT 24
Finished May 05 12:59:03 PM PDT 24
Peak memory 203872 kb
Host smart-6cb5bb59-c94e-4a41-bbc3-3c6f20c23f47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914697183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.914697183
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.522132549
Short name T175
Test name
Test status
Simulation time 251404065 ps
CPU time 1.39 seconds
Started May 05 12:58:37 PM PDT 24
Finished May 05 12:58:39 PM PDT 24
Peak memory 203860 kb
Host smart-e473281e-48d2-4261-b00d-37bc70d0e7c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522132549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.522132549
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.86759406
Short name T163
Test name
Test status
Simulation time 140749575 ps
CPU time 5.16 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:40 PM PDT 24
Peak memory 203848 kb
Host smart-183bd116-92db-4332-8113-08ce82110996
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86759406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.86759406
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4139838180
Short name T80
Test name
Test status
Simulation time 19379534 ps
CPU time 0.69 seconds
Started May 05 12:58:30 PM PDT 24
Finished May 05 12:58:31 PM PDT 24
Peak memory 203688 kb
Host smart-2d5f6162-3b9d-4640-9286-51e149c7de71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139838180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4139838180
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3909013213
Short name T143
Test name
Test status
Simulation time 230957377 ps
CPU time 0.82 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203712 kb
Host smart-a48ca310-3c5b-4b8a-8f6a-030d9d508a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909013213 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3909013213
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1423565298
Short name T167
Test name
Test status
Simulation time 29813395 ps
CPU time 0.81 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:37 PM PDT 24
Peak memory 203712 kb
Host smart-4faae088-a474-4ac9-96c3-bc3d70de5b86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423565298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1423565298
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1114103739
Short name T1382
Test name
Test status
Simulation time 15076754 ps
CPU time 0.65 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203564 kb
Host smart-b3787b9c-f050-4acb-a540-403a7bf6de1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114103739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1114103739
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1011880047
Short name T1444
Test name
Test status
Simulation time 63033045 ps
CPU time 0.89 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:36 PM PDT 24
Peak memory 203692 kb
Host smart-03ccb076-56bb-4a41-a32c-3a5dd448ad68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011880047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1011880047
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1872217705
Short name T1435
Test name
Test status
Simulation time 95428307 ps
CPU time 2.34 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203860 kb
Host smart-98618eda-e1ac-40f2-9ef1-bf9dda6253b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872217705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1872217705
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1473755805
Short name T1393
Test name
Test status
Simulation time 14903422 ps
CPU time 0.66 seconds
Started May 05 12:59:06 PM PDT 24
Finished May 05 12:59:07 PM PDT 24
Peak memory 203636 kb
Host smart-ccc15bc6-4fb8-48f6-bbdc-2a7184e98a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473755805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1473755805
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4081715583
Short name T1438
Test name
Test status
Simulation time 42593888 ps
CPU time 0.59 seconds
Started May 05 12:59:10 PM PDT 24
Finished May 05 12:59:11 PM PDT 24
Peak memory 202772 kb
Host smart-320a2f09-9156-4a30-a746-6ef2dc6ba2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081715583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4081715583
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3246936735
Short name T1449
Test name
Test status
Simulation time 18651747 ps
CPU time 0.67 seconds
Started May 05 12:59:11 PM PDT 24
Finished May 05 12:59:12 PM PDT 24
Peak memory 203564 kb
Host smart-0dd3e786-434c-44c3-9d22-41ef03d4bc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246936735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3246936735
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3282400608
Short name T1378
Test name
Test status
Simulation time 31744869 ps
CPU time 0.63 seconds
Started May 05 12:59:07 PM PDT 24
Finished May 05 12:59:08 PM PDT 24
Peak memory 203624 kb
Host smart-de6dd51d-400f-4944-88b8-4c18e65b7f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282400608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3282400608
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.3573752282
Short name T1419
Test name
Test status
Simulation time 35292047 ps
CPU time 0.64 seconds
Started May 05 12:59:06 PM PDT 24
Finished May 05 12:59:07 PM PDT 24
Peak memory 203628 kb
Host smart-1b631e37-768e-4fc3-a43d-4f88b57aaac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573752282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3573752282
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1329119265
Short name T1427
Test name
Test status
Simulation time 37780358 ps
CPU time 0.63 seconds
Started May 05 12:59:08 PM PDT 24
Finished May 05 12:59:09 PM PDT 24
Peak memory 203560 kb
Host smart-346f3c55-c316-4eb3-a699-fffc0430d887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329119265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1329119265
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1116153701
Short name T1394
Test name
Test status
Simulation time 35953723 ps
CPU time 0.66 seconds
Started May 05 12:59:08 PM PDT 24
Finished May 05 12:59:09 PM PDT 24
Peak memory 203652 kb
Host smart-539eac0a-4b54-4093-8f5d-66265ff560b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116153701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1116153701
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.61946317
Short name T1425
Test name
Test status
Simulation time 58316874 ps
CPU time 0.63 seconds
Started May 05 12:59:09 PM PDT 24
Finished May 05 12:59:10 PM PDT 24
Peak memory 203620 kb
Host smart-18e69134-9e0b-48d3-a514-8eff27088715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61946317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.61946317
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1949597603
Short name T1374
Test name
Test status
Simulation time 15880149 ps
CPU time 0.67 seconds
Started May 05 12:59:10 PM PDT 24
Finished May 05 12:59:11 PM PDT 24
Peak memory 203656 kb
Host smart-4771e065-c859-43a4-886c-130346829572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949597603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1949597603
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2792203474
Short name T1450
Test name
Test status
Simulation time 49654067 ps
CPU time 0.62 seconds
Started May 05 12:59:21 PM PDT 24
Finished May 05 12:59:22 PM PDT 24
Peak memory 203660 kb
Host smart-5251aa53-0056-4fb1-8c89-4dc8533c04f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792203474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2792203474
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.86604638
Short name T161
Test name
Test status
Simulation time 279129735 ps
CPU time 1.32 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:36 PM PDT 24
Peak memory 203840 kb
Host smart-ccdf137a-8036-4416-ad92-3ac008448deb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86604638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.86604638
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1216893334
Short name T164
Test name
Test status
Simulation time 679257972 ps
CPU time 4.99 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:41 PM PDT 24
Peak memory 203860 kb
Host smart-9d8badbd-d522-4e2f-b68d-ad2cbc5cbbd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216893334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1216893334
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1621484805
Short name T159
Test name
Test status
Simulation time 51085022 ps
CPU time 0.82 seconds
Started May 05 12:58:35 PM PDT 24
Finished May 05 12:58:36 PM PDT 24
Peak memory 203668 kb
Host smart-051c927b-5df0-4014-b7a3-d5aae3894c60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621484805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1621484805
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.973478694
Short name T1415
Test name
Test status
Simulation time 125321323 ps
CPU time 0.82 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:38 PM PDT 24
Peak memory 203772 kb
Host smart-9d2e9455-3721-450d-869e-563bf7e11fab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973478694 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.973478694
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1020648244
Short name T1401
Test name
Test status
Simulation time 21633769 ps
CPU time 0.67 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:37 PM PDT 24
Peak memory 203728 kb
Host smart-840b6d4c-bb15-4d21-ab65-20cab5a1e5ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020648244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1020648244
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1416778737
Short name T1369
Test name
Test status
Simulation time 51733699 ps
CPU time 0.64 seconds
Started May 05 12:58:36 PM PDT 24
Finished May 05 12:58:37 PM PDT 24
Peak memory 203632 kb
Host smart-8e40abef-ffa1-4470-a8d7-83ba0d587be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416778737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1416778737
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4012530139
Short name T1386
Test name
Test status
Simulation time 91510710 ps
CPU time 0.82 seconds
Started May 05 12:58:38 PM PDT 24
Finished May 05 12:58:39 PM PDT 24
Peak memory 203732 kb
Host smart-3e6a3039-b6d3-47dc-a8ff-354b23775610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012530139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.4012530139
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3614641432
Short name T1466
Test name
Test status
Simulation time 31027329 ps
CPU time 0.67 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:14 PM PDT 24
Peak memory 203564 kb
Host smart-40a4d6e5-9a5b-44aa-a0c3-8feea35ef80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614641432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3614641432
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.759030001
Short name T1365
Test name
Test status
Simulation time 17595528 ps
CPU time 0.68 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:14 PM PDT 24
Peak memory 203576 kb
Host smart-189fd3d5-cd79-4738-b58c-c981f3ae5ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759030001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.759030001
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2488282132
Short name T1426
Test name
Test status
Simulation time 24700028 ps
CPU time 0.65 seconds
Started May 05 12:59:12 PM PDT 24
Finished May 05 12:59:13 PM PDT 24
Peak memory 203636 kb
Host smart-890e7424-46d4-434d-95bf-4e194fce17b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488282132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2488282132
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3717538935
Short name T1405
Test name
Test status
Simulation time 66898842 ps
CPU time 0.64 seconds
Started May 05 12:59:10 PM PDT 24
Finished May 05 12:59:11 PM PDT 24
Peak memory 203604 kb
Host smart-9e91af1d-b165-4614-bfe5-f41c6ff11e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717538935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3717538935
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3835971932
Short name T1422
Test name
Test status
Simulation time 18759023 ps
CPU time 0.64 seconds
Started May 05 12:59:15 PM PDT 24
Finished May 05 12:59:16 PM PDT 24
Peak memory 203564 kb
Host smart-552a1473-1c68-43ac-969d-f102b84add50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835971932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3835971932
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3690229090
Short name T1417
Test name
Test status
Simulation time 30729379 ps
CPU time 0.64 seconds
Started May 05 12:59:12 PM PDT 24
Finished May 05 12:59:13 PM PDT 24
Peak memory 203640 kb
Host smart-3ecbfc0a-c04d-4963-a033-e4f5f69a4249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690229090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3690229090
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1059505897
Short name T1368
Test name
Test status
Simulation time 18445302 ps
CPU time 0.66 seconds
Started May 05 12:59:16 PM PDT 24
Finished May 05 12:59:17 PM PDT 24
Peak memory 203660 kb
Host smart-ccaf4065-c3f1-40d2-a430-348da7a0b564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059505897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1059505897
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.493404808
Short name T1428
Test name
Test status
Simulation time 47877853 ps
CPU time 0.61 seconds
Started May 05 12:59:11 PM PDT 24
Finished May 05 12:59:12 PM PDT 24
Peak memory 203564 kb
Host smart-96fa46de-814a-4b7f-b414-f5305ed57b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493404808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.493404808
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1471845923
Short name T1371
Test name
Test status
Simulation time 133170721 ps
CPU time 0.65 seconds
Started May 05 12:59:12 PM PDT 24
Finished May 05 12:59:14 PM PDT 24
Peak memory 203620 kb
Host smart-1f850d42-20e3-4731-adb9-7bd65dfcfef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471845923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1471845923
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1124140392
Short name T1465
Test name
Test status
Simulation time 31958080 ps
CPU time 0.72 seconds
Started May 05 12:59:16 PM PDT 24
Finished May 05 12:59:18 PM PDT 24
Peak memory 203660 kb
Host smart-3a30427e-83b0-401c-878b-a602669b5a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124140392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1124140392
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3848787786
Short name T1408
Test name
Test status
Simulation time 271285210 ps
CPU time 1.39 seconds
Started May 05 12:58:43 PM PDT 24
Finished May 05 12:58:45 PM PDT 24
Peak memory 203796 kb
Host smart-8af3143a-32f5-43bf-bafa-22eca0afb87c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848787786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3848787786
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1899137738
Short name T1375
Test name
Test status
Simulation time 73288848 ps
CPU time 2.97 seconds
Started May 05 12:58:40 PM PDT 24
Finished May 05 12:58:43 PM PDT 24
Peak memory 203892 kb
Host smart-aa8a405f-5335-4643-8420-27ab1250ba98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899137738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1899137738
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3869638501
Short name T81
Test name
Test status
Simulation time 28503245 ps
CPU time 0.75 seconds
Started May 05 12:58:44 PM PDT 24
Finished May 05 12:58:45 PM PDT 24
Peak memory 203724 kb
Host smart-760bcf97-9f4d-43d1-9e49-90b1cdd9afc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869638501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3869638501
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.324713065
Short name T1385
Test name
Test status
Simulation time 202699115 ps
CPU time 0.96 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 203760 kb
Host smart-f9e5ad38-cf29-453e-ab5f-fb2f10160c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324713065 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.324713065
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3852317729
Short name T1441
Test name
Test status
Simulation time 21925165 ps
CPU time 0.68 seconds
Started May 05 12:58:47 PM PDT 24
Finished May 05 12:58:48 PM PDT 24
Peak memory 203748 kb
Host smart-7b74f636-bfd4-4cad-8837-6126d5267976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852317729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3852317729
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.597259751
Short name T1383
Test name
Test status
Simulation time 18040270 ps
CPU time 0.65 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203632 kb
Host smart-e27efbdd-dca5-4062-a6e4-70aa6498b845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597259751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.597259751
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3636382560
Short name T1390
Test name
Test status
Simulation time 105240016 ps
CPU time 0.85 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:46 PM PDT 24
Peak memory 203648 kb
Host smart-97d5351c-ccb5-443a-9f24-19e99cd3137a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636382560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3636382560
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2078916926
Short name T137
Test name
Test status
Simulation time 103008055 ps
CPU time 2.38 seconds
Started May 05 12:58:39 PM PDT 24
Finished May 05 12:58:42 PM PDT 24
Peak memory 203808 kb
Host smart-1469cb71-5d53-4f47-925b-8787f8fccb97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078916926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2078916926
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3935475731
Short name T147
Test name
Test status
Simulation time 50772699 ps
CPU time 1.35 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 203900 kb
Host smart-f49f8e6c-d7de-4610-ab7f-2f0718705f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935475731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3935475731
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2106779198
Short name T1411
Test name
Test status
Simulation time 78710206 ps
CPU time 0.66 seconds
Started May 05 12:59:10 PM PDT 24
Finished May 05 12:59:12 PM PDT 24
Peak memory 203616 kb
Host smart-f2007af4-27d9-4939-bb23-fd010493ff44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106779198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2106779198
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3260549086
Short name T1387
Test name
Test status
Simulation time 27465334 ps
CPU time 0.7 seconds
Started May 05 12:59:16 PM PDT 24
Finished May 05 12:59:18 PM PDT 24
Peak memory 203652 kb
Host smart-d2f52d2f-2d08-4b37-99f0-af5f8a7a578f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260549086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3260549086
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.4192918254
Short name T1403
Test name
Test status
Simulation time 172399923 ps
CPU time 0.64 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:14 PM PDT 24
Peak memory 203588 kb
Host smart-6f4c0f9d-3031-4f67-a9cb-17758acf7394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192918254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4192918254
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.193170143
Short name T1391
Test name
Test status
Simulation time 21372154 ps
CPU time 0.66 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:14 PM PDT 24
Peak memory 203616 kb
Host smart-2b063f0b-1afa-4b40-a291-77c9cf411a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193170143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.193170143
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1133123903
Short name T1402
Test name
Test status
Simulation time 17212306 ps
CPU time 0.66 seconds
Started May 05 12:59:15 PM PDT 24
Finished May 05 12:59:16 PM PDT 24
Peak memory 203668 kb
Host smart-9109dc84-f2fc-4bb2-b567-13c6d59194fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133123903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1133123903
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2641903060
Short name T1367
Test name
Test status
Simulation time 31411907 ps
CPU time 0.62 seconds
Started May 05 12:59:14 PM PDT 24
Finished May 05 12:59:15 PM PDT 24
Peak memory 203584 kb
Host smart-cec1bea4-e336-490c-8130-10728b1cdf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641903060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2641903060
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1353898222
Short name T1462
Test name
Test status
Simulation time 19246851 ps
CPU time 0.68 seconds
Started May 05 12:59:14 PM PDT 24
Finished May 05 12:59:15 PM PDT 24
Peak memory 203600 kb
Host smart-5c4a90bc-d9d3-49bb-91a8-e7f73eeb1067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353898222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1353898222
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2357658952
Short name T1430
Test name
Test status
Simulation time 22086836 ps
CPU time 0.65 seconds
Started May 05 12:59:11 PM PDT 24
Finished May 05 12:59:13 PM PDT 24
Peak memory 203644 kb
Host smart-db0ee833-791c-47d7-be9b-28a59d1e9f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357658952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2357658952
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2084804943
Short name T1406
Test name
Test status
Simulation time 124065436 ps
CPU time 0.66 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:15 PM PDT 24
Peak memory 203620 kb
Host smart-4f82e13a-99b0-44e5-9980-d6a82d103f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084804943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2084804943
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.728817252
Short name T1440
Test name
Test status
Simulation time 22604487 ps
CPU time 0.71 seconds
Started May 05 12:59:13 PM PDT 24
Finished May 05 12:59:15 PM PDT 24
Peak memory 203592 kb
Host smart-765a1f95-1b0c-4f1e-9648-d91e6d0e9044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728817252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.728817252
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4054285230
Short name T132
Test name
Test status
Simulation time 27156766 ps
CPU time 1.22 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 212052 kb
Host smart-e5e97218-0aeb-4646-8a4a-7d5c8799f468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054285230 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4054285230
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.377269871
Short name T156
Test name
Test status
Simulation time 18735054 ps
CPU time 0.79 seconds
Started May 05 12:58:48 PM PDT 24
Finished May 05 12:58:49 PM PDT 24
Peak memory 203724 kb
Host smart-62dee028-5833-4d6c-a40e-72489847190b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377269871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.377269871
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2437212372
Short name T1443
Test name
Test status
Simulation time 17715646 ps
CPU time 0.64 seconds
Started May 05 12:58:46 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 203596 kb
Host smart-ec5c823a-b8bc-4f38-9dd1-6598a0f3481f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437212372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2437212372
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3808095785
Short name T1410
Test name
Test status
Simulation time 30134541 ps
CPU time 1.1 seconds
Started May 05 12:58:46 PM PDT 24
Finished May 05 12:58:48 PM PDT 24
Peak memory 203808 kb
Host smart-f738041c-b099-4940-ae9f-e31cc14fd744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808095785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3808095785
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2691978472
Short name T1446
Test name
Test status
Simulation time 278885391 ps
CPU time 2.32 seconds
Started May 05 12:58:44 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 203832 kb
Host smart-ffa7b0e0-3b8f-472e-86ed-7674a9ed98e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691978472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2691978472
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.600957609
Short name T1434
Test name
Test status
Simulation time 33541542 ps
CPU time 0.96 seconds
Started May 05 12:58:47 PM PDT 24
Finished May 05 12:58:48 PM PDT 24
Peak memory 203784 kb
Host smart-b0de5993-50fb-4575-a948-169beee2a7f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600957609 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.600957609
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2399652414
Short name T160
Test name
Test status
Simulation time 37586361 ps
CPU time 0.67 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:46 PM PDT 24
Peak memory 203620 kb
Host smart-d0af52e9-d22e-462c-a73d-a8d8c31561ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399652414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2399652414
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2722659254
Short name T1384
Test name
Test status
Simulation time 23477145 ps
CPU time 0.65 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:46 PM PDT 24
Peak memory 203696 kb
Host smart-27c31bd4-130a-4993-a69a-61ba1a9d206f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722659254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2722659254
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2593354804
Short name T170
Test name
Test status
Simulation time 20376490 ps
CPU time 0.83 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203676 kb
Host smart-124b09e4-d040-430b-86fb-a3b3a3d47d02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593354804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2593354804
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.990090343
Short name T1439
Test name
Test status
Simulation time 51812453 ps
CPU time 2.59 seconds
Started May 05 12:58:47 PM PDT 24
Finished May 05 12:58:50 PM PDT 24
Peak memory 203884 kb
Host smart-0ca48080-ecdb-4c59-8686-965748e0896a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990090343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.990090343
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3713409089
Short name T130
Test name
Test status
Simulation time 132646038 ps
CPU time 1.55 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:52 PM PDT 24
Peak memory 203808 kb
Host smart-3e7a8ffb-ced9-4d76-a058-14b4b6538e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713409089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3713409089
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1508057944
Short name T138
Test name
Test status
Simulation time 111325695 ps
CPU time 0.92 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203780 kb
Host smart-f83a68bc-23c4-4fa8-a5bf-5453160b1ada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508057944 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1508057944
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1595365160
Short name T1366
Test name
Test status
Simulation time 76506310 ps
CPU time 0.64 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203720 kb
Host smart-8be3531d-5319-4655-ac46-7addba72df21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595365160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1595365160
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2385554554
Short name T1364
Test name
Test status
Simulation time 70388857 ps
CPU time 0.65 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203636 kb
Host smart-3acd6e7d-eb13-446a-8dc6-c0b9e9668e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385554554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2385554554
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2114337694
Short name T1376
Test name
Test status
Simulation time 37369008 ps
CPU time 1.2 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:50 PM PDT 24
Peak memory 203812 kb
Host smart-0594ff40-cad5-4223-b84c-fd55a6cd3c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114337694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2114337694
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4120167657
Short name T1433
Test name
Test status
Simulation time 26630380 ps
CPU time 1.2 seconds
Started May 05 12:58:45 PM PDT 24
Finished May 05 12:58:47 PM PDT 24
Peak memory 203920 kb
Host smart-8e0b294d-a40f-479b-97fc-ccf62bfa9f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120167657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4120167657
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.253213101
Short name T152
Test name
Test status
Simulation time 295532660 ps
CPU time 2.44 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:52 PM PDT 24
Peak memory 203808 kb
Host smart-80d14ca2-786d-4924-aaf2-2444d67f832c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253213101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.253213101
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1954408280
Short name T1377
Test name
Test status
Simulation time 69033141 ps
CPU time 0.79 seconds
Started May 05 12:58:51 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203828 kb
Host smart-80c7be7e-a2b3-4259-8f81-d8d1319cca37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954408280 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1954408280
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1591189881
Short name T158
Test name
Test status
Simulation time 19942645 ps
CPU time 0.77 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:52 PM PDT 24
Peak memory 203732 kb
Host smart-12b70eb5-c430-4adc-8c8d-57fae309c22d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591189881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1591189881
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3017306480
Short name T1469
Test name
Test status
Simulation time 42874743 ps
CPU time 0.64 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203524 kb
Host smart-f41cbaf1-46dd-4986-84b7-1b0e31c0a5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017306480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3017306480
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4080760608
Short name T1431
Test name
Test status
Simulation time 460237426 ps
CPU time 1.17 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:54 PM PDT 24
Peak memory 204068 kb
Host smart-01065ad9-58e3-4183-ae53-44fcb86ace02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080760608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4080760608
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.750085909
Short name T136
Test name
Test status
Simulation time 113288322 ps
CPU time 2.73 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:55 PM PDT 24
Peak memory 203952 kb
Host smart-c61aca23-98cb-4afb-a737-9a0cb4f5784e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750085909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.750085909
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1624768260
Short name T176
Test name
Test status
Simulation time 529959472 ps
CPU time 1.49 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:54 PM PDT 24
Peak memory 203892 kb
Host smart-f0eb3398-c557-41bd-8087-3ce05a8110fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624768260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1624768260
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.253400335
Short name T1379
Test name
Test status
Simulation time 23033725 ps
CPU time 0.78 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:54 PM PDT 24
Peak memory 204024 kb
Host smart-ce2688f3-9d78-4770-ac98-100f35bce8eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253400335 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.253400335
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.696278950
Short name T171
Test name
Test status
Simulation time 69095237 ps
CPU time 0.76 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:54 PM PDT 24
Peak memory 203748 kb
Host smart-32055974-ada7-4bb9-9674-78e1b2a08ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696278950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.696278950
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2273410630
Short name T1412
Test name
Test status
Simulation time 88384804 ps
CPU time 0.66 seconds
Started May 05 12:58:52 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203608 kb
Host smart-cf769dcf-aa9b-4858-a1e5-cd94ff043621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273410630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2273410630
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2188841899
Short name T1373
Test name
Test status
Simulation time 76632641 ps
CPU time 0.8 seconds
Started May 05 12:58:49 PM PDT 24
Finished May 05 12:58:51 PM PDT 24
Peak memory 203716 kb
Host smart-62e07b5e-7eb1-4f71-a243-ce8a04f4e782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188841899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2188841899
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2085996090
Short name T151
Test name
Test status
Simulation time 221448855 ps
CPU time 1.52 seconds
Started May 05 12:58:51 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203872 kb
Host smart-704f7c27-ccb3-4c76-8dd6-33f4d34d0d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085996090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2085996090
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.335131573
Short name T145
Test name
Test status
Simulation time 1594548900 ps
CPU time 2.28 seconds
Started May 05 12:58:50 PM PDT 24
Finished May 05 12:58:53 PM PDT 24
Peak memory 203784 kb
Host smart-e7aaf4ea-e4d8-49d2-8372-3b5ba21e2676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335131573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.335131573
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.25872053
Short name T581
Test name
Test status
Simulation time 295509608 ps
CPU time 1.18 seconds
Started May 05 01:09:18 PM PDT 24
Finished May 05 01:09:20 PM PDT 24
Peak memory 212048 kb
Host smart-c77ad846-ada7-48a8-9c91-649b3cbf9ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25872053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.25872053
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.936474044
Short name T424
Test name
Test status
Simulation time 259536251 ps
CPU time 5.64 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:09:23 PM PDT 24
Peak memory 253748 kb
Host smart-ad30fa77-8d2b-4d78-8680-03407286f025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936474044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.936474044
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.413317176
Short name T938
Test name
Test status
Simulation time 5380075352 ps
CPU time 39.81 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:09:57 PM PDT 24
Peak memory 527088 kb
Host smart-6c0b7811-1852-46a4-b55d-28bbf41f6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413317176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.413317176
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2933434832
Short name T980
Test name
Test status
Simulation time 1654977860 ps
CPU time 53.92 seconds
Started May 05 01:09:18 PM PDT 24
Finished May 05 01:10:12 PM PDT 24
Peak memory 602452 kb
Host smart-fd40b6b8-6a5a-4948-ac91-434d29fa8488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933434832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2933434832
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.25139854
Short name T1015
Test name
Test status
Simulation time 292943145 ps
CPU time 0.91 seconds
Started May 05 01:09:24 PM PDT 24
Finished May 05 01:09:25 PM PDT 24
Peak memory 203840 kb
Host smart-2486f2d5-d3d0-45bb-a4e2-cec96ac07797
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25139854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.25139854
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1046917970
Short name T639
Test name
Test status
Simulation time 195240706 ps
CPU time 2.64 seconds
Started May 05 01:09:15 PM PDT 24
Finished May 05 01:09:19 PM PDT 24
Peak memory 217648 kb
Host smart-d982f18d-d757-44f1-8dcd-d223d0e9581c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046917970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1046917970
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2790166382
Short name T622
Test name
Test status
Simulation time 17530157403 ps
CPU time 93.63 seconds
Started May 05 01:09:20 PM PDT 24
Finished May 05 01:10:54 PM PDT 24
Peak memory 943028 kb
Host smart-e0756302-6374-4e78-992f-8c453610d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790166382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2790166382
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1072309777
Short name T69
Test name
Test status
Simulation time 505423896 ps
CPU time 21.06 seconds
Started May 05 01:09:29 PM PDT 24
Finished May 05 01:09:51 PM PDT 24
Peak memory 204072 kb
Host smart-9d11c496-9d71-4544-bb6c-f4ac0eb09899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072309777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1072309777
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.555684085
Short name T632
Test name
Test status
Simulation time 3106969549 ps
CPU time 24.38 seconds
Started May 05 01:09:32 PM PDT 24
Finished May 05 01:09:57 PM PDT 24
Peak memory 302360 kb
Host smart-3f6bc9d8-cae6-42f3-ac30-1ff167b16ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555684085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.555684085
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3020661991
Short name T1359
Test name
Test status
Simulation time 120170423 ps
CPU time 0.66 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:09:20 PM PDT 24
Peak memory 203616 kb
Host smart-113efdbe-3152-4a0e-868f-54eac88703e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020661991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3020661991
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.791993410
Short name T382
Test name
Test status
Simulation time 17724356657 ps
CPU time 210.81 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:12:48 PM PDT 24
Peak memory 932740 kb
Host smart-0c7b733e-4ff3-4ea6-89ef-fa6906894859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791993410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.791993410
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2750632284
Short name T725
Test name
Test status
Simulation time 3378633170 ps
CPU time 54.76 seconds
Started May 05 01:09:18 PM PDT 24
Finished May 05 01:10:14 PM PDT 24
Peak memory 309756 kb
Host smart-2c8f46a2-cd87-4d02-a0c5-1f3791fab9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750632284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2750632284
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3888437328
Short name T1172
Test name
Test status
Simulation time 47331429713 ps
CPU time 468.54 seconds
Started May 05 01:09:21 PM PDT 24
Finished May 05 01:17:10 PM PDT 24
Peak memory 1627304 kb
Host smart-ed21764a-9f87-4c04-88b3-8237b86a0c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888437328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3888437328
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.3952088316
Short name T1264
Test name
Test status
Simulation time 3661107265 ps
CPU time 32.79 seconds
Started May 05 01:09:16 PM PDT 24
Finished May 05 01:09:49 PM PDT 24
Peak memory 212092 kb
Host smart-17c0ea7f-8eec-41e5-a819-6fb755d50c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952088316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3952088316
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2127954008
Short name T351
Test name
Test status
Simulation time 1135072960 ps
CPU time 3.17 seconds
Started May 05 01:09:30 PM PDT 24
Finished May 05 01:09:33 PM PDT 24
Peak memory 203812 kb
Host smart-713bbf09-ccc6-49fb-9724-9eb637b9c886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127954008 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2127954008
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2210739755
Short name T393
Test name
Test status
Simulation time 10066428393 ps
CPU time 68.82 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:10:42 PM PDT 24
Peak memory 501224 kb
Host smart-aff419c4-5319-4b37-ae05-bc53a8955925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210739755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2210739755
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2683393010
Short name T457
Test name
Test status
Simulation time 10294250907 ps
CPU time 14.07 seconds
Started May 05 01:09:23 PM PDT 24
Finished May 05 01:09:37 PM PDT 24
Peak memory 269348 kb
Host smart-d39b00df-7820-430b-a57c-70f9aa9bb471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683393010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2683393010
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.300387503
Short name T912
Test name
Test status
Simulation time 797941507 ps
CPU time 2.65 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:09:22 PM PDT 24
Peak memory 203848 kb
Host smart-5e49cf90-612c-40ce-b7b6-94563595030a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300387503 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.300387503
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1048221224
Short name T373
Test name
Test status
Simulation time 2765753147 ps
CPU time 7.01 seconds
Started May 05 01:09:22 PM PDT 24
Finished May 05 01:09:30 PM PDT 24
Peak memory 212060 kb
Host smart-624c98da-c0fd-4916-9d90-4eca71b7d5a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048221224 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1048221224
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.897897127
Short name T891
Test name
Test status
Simulation time 5749590438 ps
CPU time 5.96 seconds
Started May 05 01:09:22 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 203892 kb
Host smart-d83df504-11a5-4be5-be5c-4e3891913d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897897127 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.897897127
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1966249132
Short name T671
Test name
Test status
Simulation time 2315578392 ps
CPU time 9.72 seconds
Started May 05 01:09:24 PM PDT 24
Finished May 05 01:09:34 PM PDT 24
Peak memory 203884 kb
Host smart-00b2c6fd-f88b-47dd-8772-95527f1bf1f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966249132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1966249132
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.532462659
Short name T586
Test name
Test status
Simulation time 4306212001 ps
CPU time 46.51 seconds
Started May 05 01:09:19 PM PDT 24
Finished May 05 01:10:06 PM PDT 24
Peak memory 205596 kb
Host smart-bdcf1a7f-f0cb-4e59-81c9-d7875d238b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532462659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.532462659
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.4143073322
Short name T499
Test name
Test status
Simulation time 34934979681 ps
CPU time 41.53 seconds
Started May 05 01:09:29 PM PDT 24
Finished May 05 01:10:11 PM PDT 24
Peak memory 881512 kb
Host smart-63b6d98b-4cba-4e4b-993e-e0a115465256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143073322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.4143073322
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2951258415
Short name T1246
Test name
Test status
Simulation time 3341150021 ps
CPU time 16.2 seconds
Started May 05 01:09:30 PM PDT 24
Finished May 05 01:09:47 PM PDT 24
Peak memory 400408 kb
Host smart-79fca86f-3be3-4d1d-9da7-5e834be4772d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951258415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2951258415
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3156330251
Short name T404
Test name
Test status
Simulation time 5074599989 ps
CPU time 7 seconds
Started May 05 01:09:29 PM PDT 24
Finished May 05 01:09:37 PM PDT 24
Peak memory 220192 kb
Host smart-c69db25a-9a10-4012-b655-383dd13f5797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156330251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3156330251
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.3034323181
Short name T15
Test name
Test status
Simulation time 3938001420 ps
CPU time 5.08 seconds
Started May 05 01:09:20 PM PDT 24
Finished May 05 01:09:25 PM PDT 24
Peak memory 203892 kb
Host smart-123581ea-dfe8-4005-90c2-434013e8c6c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034323181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.3034323181
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2953305716
Short name T677
Test name
Test status
Simulation time 21003088 ps
CPU time 0.59 seconds
Started May 05 01:09:32 PM PDT 24
Finished May 05 01:09:34 PM PDT 24
Peak memory 203724 kb
Host smart-4eb7dea6-f004-46fc-989d-1dc671ec18f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953305716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2953305716
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1587272034
Short name T494
Test name
Test status
Simulation time 83895676 ps
CPU time 1.45 seconds
Started May 05 01:09:30 PM PDT 24
Finished May 05 01:09:32 PM PDT 24
Peak memory 203804 kb
Host smart-acc61f21-b8e4-4449-8713-2685091de3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587272034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1587272034
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2145448383
Short name T1080
Test name
Test status
Simulation time 173069399 ps
CPU time 3.22 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:09:32 PM PDT 24
Peak memory 232736 kb
Host smart-5b3f65d9-0e9d-449e-a75f-f136aed9fb12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145448383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2145448383
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2319717656
Short name T988
Test name
Test status
Simulation time 1386416111 ps
CPU time 52.54 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:10:27 PM PDT 24
Peak memory 545052 kb
Host smart-54499e21-23c1-4f4a-8505-1725d82c177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319717656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2319717656
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2446658352
Short name T676
Test name
Test status
Simulation time 1988845028 ps
CPU time 54.07 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:10:23 PM PDT 24
Peak memory 676172 kb
Host smart-d7d6d45f-682e-4af1-8bb5-c457a0afc22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446658352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2446658352
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.28682552
Short name T630
Test name
Test status
Simulation time 268708736 ps
CPU time 1.15 seconds
Started May 05 01:09:30 PM PDT 24
Finished May 05 01:09:32 PM PDT 24
Peak memory 204068 kb
Host smart-e72d94eb-298e-4cd9-9153-7f5c26f5e2e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28682552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.28682552
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.4223089507
Short name T782
Test name
Test status
Simulation time 562318912 ps
CPU time 3.64 seconds
Started May 05 01:09:25 PM PDT 24
Finished May 05 01:09:29 PM PDT 24
Peak memory 229320 kb
Host smart-ec6a8bd0-7553-4759-ad4e-91356cd73a39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223089507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
4223089507
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3736502357
Short name T1137
Test name
Test status
Simulation time 333126837 ps
CPU time 5.39 seconds
Started May 05 01:09:35 PM PDT 24
Finished May 05 01:09:41 PM PDT 24
Peak memory 203872 kb
Host smart-0ec9cbfc-bf25-43e8-843c-4a96507e1430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736502357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3736502357
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2127823330
Short name T823
Test name
Test status
Simulation time 5307800842 ps
CPU time 13.79 seconds
Started May 05 01:09:31 PM PDT 24
Finished May 05 01:09:45 PM PDT 24
Peak memory 261012 kb
Host smart-ff08c462-ef84-46ea-b2aa-96a6358c08b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127823330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2127823330
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3734135227
Short name T398
Test name
Test status
Simulation time 79760639 ps
CPU time 0.66 seconds
Started May 05 01:09:34 PM PDT 24
Finished May 05 01:09:35 PM PDT 24
Peak memory 203548 kb
Host smart-86cbff73-346c-4191-b0a7-eb7fdd2739be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734135227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3734135227
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1275149931
Short name T975
Test name
Test status
Simulation time 97029693081 ps
CPU time 888.44 seconds
Started May 05 01:09:24 PM PDT 24
Finished May 05 01:24:13 PM PDT 24
Peak memory 203868 kb
Host smart-8a79127b-22eb-49c5-8ccb-dcc7949a71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275149931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1275149931
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2769096077
Short name T978
Test name
Test status
Simulation time 1074725136 ps
CPU time 21.48 seconds
Started May 05 01:09:31 PM PDT 24
Finished May 05 01:09:53 PM PDT 24
Peak memory 329128 kb
Host smart-a2c13be8-66c1-4de2-ae24-628edfe673b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769096077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2769096077
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2548820281
Short name T194
Test name
Test status
Simulation time 175319986611 ps
CPU time 563.12 seconds
Started May 05 01:09:25 PM PDT 24
Finished May 05 01:18:48 PM PDT 24
Peak memory 2190404 kb
Host smart-1e414bbc-bb03-4809-a208-7e6dbf1b1367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548820281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2548820281
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.412132296
Short name T233
Test name
Test status
Simulation time 357761053 ps
CPU time 7.42 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:09:36 PM PDT 24
Peak memory 212028 kb
Host smart-0fd6f886-b77d-4415-b0c8-e33e85f3ac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412132296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.412132296
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.30236747
Short name T120
Test name
Test status
Simulation time 120557869 ps
CPU time 0.92 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:09:35 PM PDT 24
Peak memory 222316 kb
Host smart-a124bcf2-e521-4553-8124-502a27fb9bc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30236747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.30236747
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.726449058
Short name T377
Test name
Test status
Simulation time 1110728847 ps
CPU time 5.59 seconds
Started May 05 01:09:37 PM PDT 24
Finished May 05 01:09:43 PM PDT 24
Peak memory 203928 kb
Host smart-65ddb98f-d789-4717-964a-7b22bfd90824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726449058 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.726449058
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1481438959
Short name T1182
Test name
Test status
Simulation time 10125877353 ps
CPU time 16.03 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:09:50 PM PDT 24
Peak memory 301548 kb
Host smart-1171203d-0866-4edf-8938-bf22d4f68dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481438959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1481438959
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.609165325
Short name T14
Test name
Test status
Simulation time 29568043475 ps
CPU time 10.57 seconds
Started May 05 01:09:27 PM PDT 24
Finished May 05 01:09:38 PM PDT 24
Peak memory 212376 kb
Host smart-5d761685-f3dc-4298-9653-9766d06aed56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609165325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.609165325
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1269606693
Short name T1362
Test name
Test status
Simulation time 1606861415 ps
CPU time 2.77 seconds
Started May 05 01:09:32 PM PDT 24
Finished May 05 01:09:36 PM PDT 24
Peak memory 203832 kb
Host smart-e7f0710d-a714-4d47-b983-f54a67ba3b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269606693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1269606693
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1307535334
Short name T1138
Test name
Test status
Simulation time 1047642454 ps
CPU time 5.48 seconds
Started May 05 01:09:35 PM PDT 24
Finished May 05 01:09:41 PM PDT 24
Peak memory 207008 kb
Host smart-fa310310-9a7d-40f2-9bcb-b96910504b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307535334 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1307535334
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.683353716
Short name T767
Test name
Test status
Simulation time 2791768622 ps
CPU time 5.69 seconds
Started May 05 01:09:32 PM PDT 24
Finished May 05 01:09:38 PM PDT 24
Peak memory 203856 kb
Host smart-6cd89558-0444-435d-868c-a479e19cd882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683353716 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.683353716
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2938610960
Short name T1213
Test name
Test status
Simulation time 3459223343 ps
CPU time 36.51 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:10:10 PM PDT 24
Peak memory 203864 kb
Host smart-d1f11ff2-25a5-4168-bb8b-cf997f1674b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938610960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2938610960
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3999970276
Short name T1307
Test name
Test status
Simulation time 1965353766 ps
CPU time 19.33 seconds
Started May 05 01:09:34 PM PDT 24
Finished May 05 01:09:54 PM PDT 24
Peak memory 212804 kb
Host smart-497ba11c-7bca-4772-a088-2732a9dd605d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999970276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3999970276
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1900842954
Short name T1072
Test name
Test status
Simulation time 58347685877 ps
CPU time 553.75 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:18:42 PM PDT 24
Peak memory 4482664 kb
Host smart-f0c360d0-430e-4b3e-89be-7b37eea5fc62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900842954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1900842954
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.980330621
Short name T355
Test name
Test status
Simulation time 34368365134 ps
CPU time 779.46 seconds
Started May 05 01:09:28 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 2060832 kb
Host smart-80c48292-f102-4fc8-a375-5cb38d69169f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980330621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.980330621
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3611722618
Short name T1177
Test name
Test status
Simulation time 1229981977 ps
CPU time 6.65 seconds
Started May 05 01:09:33 PM PDT 24
Finished May 05 01:09:40 PM PDT 24
Peak memory 212080 kb
Host smart-1758b382-c669-4e21-a0b7-5ccceb882e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611722618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3611722618
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.497160158
Short name T1102
Test name
Test status
Simulation time 17471570 ps
CPU time 0.64 seconds
Started May 05 01:11:06 PM PDT 24
Finished May 05 01:11:07 PM PDT 24
Peak memory 203704 kb
Host smart-25e8c18c-fc43-4286-b0c4-aa2980871fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497160158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.497160158
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.330232186
Short name T1247
Test name
Test status
Simulation time 782922437 ps
CPU time 1.32 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:03 PM PDT 24
Peak memory 214940 kb
Host smart-d2898905-9834-44f0-accf-2ef205d7ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330232186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.330232186
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2630995377
Short name T322
Test name
Test status
Simulation time 661969618 ps
CPU time 5.76 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:08 PM PDT 24
Peak memory 255364 kb
Host smart-2eebca07-ee86-479d-b461-708208f5e4aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630995377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2630995377
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1265622108
Short name T1032
Test name
Test status
Simulation time 1870364567 ps
CPU time 127.76 seconds
Started May 05 01:11:03 PM PDT 24
Finished May 05 01:13:11 PM PDT 24
Peak memory 647608 kb
Host smart-a83fb9da-7a0a-4f11-9d8a-5eac3907497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265622108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1265622108
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2297661894
Short name T513
Test name
Test status
Simulation time 5249158434 ps
CPU time 32.54 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:34 PM PDT 24
Peak memory 518252 kb
Host smart-760980e4-47df-492d-950a-20351e56c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297661894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2297661894
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3768487961
Short name T761
Test name
Test status
Simulation time 401070165 ps
CPU time 1.01 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:02 PM PDT 24
Peak memory 203680 kb
Host smart-0d5493fc-410d-428e-abc3-aab66ae72252
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768487961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3768487961
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3917938395
Short name T1283
Test name
Test status
Simulation time 148869823 ps
CPU time 3.23 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:05 PM PDT 24
Peak memory 203820 kb
Host smart-d6da1b3d-e871-4c57-b35f-565c4f29c905
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917938395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3917938395
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1551017028
Short name T924
Test name
Test status
Simulation time 3347927446 ps
CPU time 78.85 seconds
Started May 05 01:11:00 PM PDT 24
Finished May 05 01:12:19 PM PDT 24
Peak memory 1034308 kb
Host smart-920cdd15-b2f5-41f0-99c6-3a93b5985995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551017028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1551017028
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1485069371
Short name T570
Test name
Test status
Simulation time 1405247019 ps
CPU time 15.07 seconds
Started May 05 01:11:09 PM PDT 24
Finished May 05 01:11:24 PM PDT 24
Peak memory 203824 kb
Host smart-864777e6-5b16-441f-9a8a-2ec60fffb6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485069371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1485069371
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1180837464
Short name T740
Test name
Test status
Simulation time 5143049028 ps
CPU time 59.69 seconds
Started May 05 01:11:13 PM PDT 24
Finished May 05 01:12:13 PM PDT 24
Peak memory 418308 kb
Host smart-9c9242d0-e03b-4955-b1e4-d47905d4fab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180837464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1180837464
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1530793753
Short name T202
Test name
Test status
Simulation time 31584286 ps
CPU time 0.78 seconds
Started May 05 01:11:02 PM PDT 24
Finished May 05 01:11:03 PM PDT 24
Peak memory 203876 kb
Host smart-faac0bdb-ecd9-4714-9d9f-def6a5a8375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530793753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1530793753
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4026286809
Short name T1108
Test name
Test status
Simulation time 72277825387 ps
CPU time 2766.04 seconds
Started May 05 01:11:05 PM PDT 24
Finished May 05 01:57:12 PM PDT 24
Peak memory 203828 kb
Host smart-bd1b40b5-ff42-4b7d-be50-d0d989e65fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026286809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4026286809
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.4293110772
Short name T531
Test name
Test status
Simulation time 4355617677 ps
CPU time 50.02 seconds
Started May 05 01:10:57 PM PDT 24
Finished May 05 01:11:47 PM PDT 24
Peak memory 274064 kb
Host smart-2b75019b-6e3d-4a74-ba03-7f62c88297a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293110772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.4293110772
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2123083887
Short name T104
Test name
Test status
Simulation time 1019264983 ps
CPU time 30.93 seconds
Started May 05 01:11:04 PM PDT 24
Finished May 05 01:11:35 PM PDT 24
Peak memory 212016 kb
Host smart-7e4097c5-6f1f-458a-a587-977d122ef43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123083887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2123083887
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2416194997
Short name T285
Test name
Test status
Simulation time 868001644 ps
CPU time 4.27 seconds
Started May 05 01:11:09 PM PDT 24
Finished May 05 01:11:13 PM PDT 24
Peak memory 211980 kb
Host smart-05f0ea4e-853c-48bf-b021-a0d934443f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416194997 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2416194997
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.9001701
Short name T337
Test name
Test status
Simulation time 10368102978 ps
CPU time 14.59 seconds
Started May 05 01:11:07 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 255504 kb
Host smart-197ec030-94ba-4f8b-a3fe-89e2b7b8d4a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9001701 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_fifo_reset_acq.9001701
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2411398211
Short name T1216
Test name
Test status
Simulation time 10024662744 ps
CPU time 81.73 seconds
Started May 05 01:11:07 PM PDT 24
Finished May 05 01:12:29 PM PDT 24
Peak memory 491040 kb
Host smart-4c3b136e-95b3-477f-ba42-6c3d11ce00c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411398211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2411398211
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3631346397
Short name T655
Test name
Test status
Simulation time 5220225741 ps
CPU time 2.79 seconds
Started May 05 01:11:08 PM PDT 24
Finished May 05 01:11:11 PM PDT 24
Peak memory 203876 kb
Host smart-e34ddaeb-91b5-400c-955c-1cedb80aa40c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631346397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3631346397
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2380239021
Short name T514
Test name
Test status
Simulation time 1542138217 ps
CPU time 4.64 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:06 PM PDT 24
Peak memory 203860 kb
Host smart-108cc228-a464-4d7b-a2d2-85c9302d811a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380239021 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2380239021
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1032244341
Short name T1332
Test name
Test status
Simulation time 11056452565 ps
CPU time 54.98 seconds
Started May 05 01:11:01 PM PDT 24
Finished May 05 01:11:56 PM PDT 24
Peak memory 1044152 kb
Host smart-ed1a97cd-4c1c-41e6-b3c9-14c27cb257a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032244341 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1032244341
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3075056987
Short name T694
Test name
Test status
Simulation time 5777483553 ps
CPU time 20.14 seconds
Started May 05 01:11:05 PM PDT 24
Finished May 05 01:11:25 PM PDT 24
Peak memory 225876 kb
Host smart-6a19d61a-7d7a-49ae-bf6d-df9367425bd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075056987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3075056987
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1540925340
Short name T1280
Test name
Test status
Simulation time 57666403355 ps
CPU time 199.22 seconds
Started May 05 01:11:04 PM PDT 24
Finished May 05 01:14:23 PM PDT 24
Peak memory 2417704 kb
Host smart-61c54f92-5b20-4d46-9de1-24f2d6e5248f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540925340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1540925340
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.37478228
Short name T1084
Test name
Test status
Simulation time 11372932945 ps
CPU time 43.32 seconds
Started May 05 01:11:02 PM PDT 24
Finished May 05 01:11:46 PM PDT 24
Peak memory 598588 kb
Host smart-18c2687b-253a-478f-873f-37732d3069fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37478228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_stretch.37478228
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1536441682
Short name T670
Test name
Test status
Simulation time 1808434215 ps
CPU time 7.63 seconds
Started May 05 01:11:04 PM PDT 24
Finished May 05 01:11:12 PM PDT 24
Peak memory 212072 kb
Host smart-255b8f7b-dcf9-4c35-9dde-e6f92b33bab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536441682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1536441682
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2911588242
Short name T982
Test name
Test status
Simulation time 37671883 ps
CPU time 0.61 seconds
Started May 05 01:11:16 PM PDT 24
Finished May 05 01:11:17 PM PDT 24
Peak memory 203744 kb
Host smart-e067ff83-f4c1-4d86-9b10-545fd64d1450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911588242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2911588242
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1022845565
Short name T877
Test name
Test status
Simulation time 97944985 ps
CPU time 1.62 seconds
Started May 05 01:11:12 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 212212 kb
Host smart-31f81d69-c1cc-4e2d-9f63-e3b95c96fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022845565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1022845565
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.131554762
Short name T292
Test name
Test status
Simulation time 581485909 ps
CPU time 14.61 seconds
Started May 05 01:11:11 PM PDT 24
Finished May 05 01:11:27 PM PDT 24
Peak memory 258800 kb
Host smart-d4c39386-f65d-450d-9c11-21b8309c9c85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131554762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.131554762
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1679687559
Short name T1317
Test name
Test status
Simulation time 1827284575 ps
CPU time 44.62 seconds
Started May 05 01:11:11 PM PDT 24
Finished May 05 01:11:56 PM PDT 24
Peak memory 491972 kb
Host smart-fe60f0a1-e15c-487e-b6be-f6ddc1595030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679687559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1679687559
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3681766684
Short name T475
Test name
Test status
Simulation time 2952258428 ps
CPU time 108.1 seconds
Started May 05 01:11:13 PM PDT 24
Finished May 05 01:13:02 PM PDT 24
Peak memory 561952 kb
Host smart-f4f0da78-9321-46f7-917c-6a6c4cf78067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681766684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3681766684
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2848564231
Short name T73
Test name
Test status
Simulation time 578300828 ps
CPU time 0.82 seconds
Started May 05 01:11:13 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 203692 kb
Host smart-49f4b462-8ccf-44a1-a054-c841038462f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848564231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2848564231
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.4153147241
Short name T323
Test name
Test status
Simulation time 15570485176 ps
CPU time 326.24 seconds
Started May 05 01:11:04 PM PDT 24
Finished May 05 01:16:31 PM PDT 24
Peak memory 1220380 kb
Host smart-c1381410-da79-40af-bdc1-e7c70d8ebd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153147241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.4153147241
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2671977654
Short name T747
Test name
Test status
Simulation time 981626327 ps
CPU time 10.56 seconds
Started May 05 01:11:15 PM PDT 24
Finished May 05 01:11:27 PM PDT 24
Peak memory 203864 kb
Host smart-6448e986-1305-4255-b982-d38881859288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671977654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2671977654
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4277152546
Short name T1180
Test name
Test status
Simulation time 1354396595 ps
CPU time 63.52 seconds
Started May 05 01:11:19 PM PDT 24
Finished May 05 01:12:23 PM PDT 24
Peak memory 328364 kb
Host smart-548443ca-26ac-4dfe-8e0d-420eece32449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277152546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4277152546
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_perf.329726400
Short name T1121
Test name
Test status
Simulation time 25649677259 ps
CPU time 1888.84 seconds
Started May 05 01:11:12 PM PDT 24
Finished May 05 01:42:42 PM PDT 24
Peak memory 4054732 kb
Host smart-bcdeea4f-a1af-4d52-8b16-92d0b2ac8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329726400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.329726400
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.829917419
Short name T950
Test name
Test status
Simulation time 3714106259 ps
CPU time 102.78 seconds
Started May 05 01:11:07 PM PDT 24
Finished May 05 01:12:50 PM PDT 24
Peak memory 447468 kb
Host smart-fea25e07-7f5b-4a07-97ae-4b5d10568ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829917419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.829917419
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2748805850
Short name T191
Test name
Test status
Simulation time 40464372435 ps
CPU time 154.2 seconds
Started May 05 01:11:09 PM PDT 24
Finished May 05 01:13:44 PM PDT 24
Peak memory 543972 kb
Host smart-88273618-e142-4553-8587-a401833b9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748805850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2748805850
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3955060880
Short name T649
Test name
Test status
Simulation time 2866764034 ps
CPU time 13.73 seconds
Started May 05 01:11:12 PM PDT 24
Finished May 05 01:11:26 PM PDT 24
Peak memory 220072 kb
Host smart-20900afa-c44f-49b3-99b6-6ab9f9fc0646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955060880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3955060880
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.45758176
Short name T308
Test name
Test status
Simulation time 1766287411 ps
CPU time 4.8 seconds
Started May 05 01:11:19 PM PDT 24
Finished May 05 01:11:24 PM PDT 24
Peak memory 212164 kb
Host smart-7b386b7f-2226-411b-9ad3-686e51521dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45758176 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_bad_addr.45758176
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.855894648
Short name T240
Test name
Test status
Simulation time 10027277258 ps
CPU time 63.66 seconds
Started May 05 01:11:19 PM PDT 24
Finished May 05 01:12:23 PM PDT 24
Peak memory 388664 kb
Host smart-b062a8c4-48cd-43b0-8645-1a9ecb3cae80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855894648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.855894648
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4020543102
Short name T1321
Test name
Test status
Simulation time 10129503443 ps
CPU time 20.75 seconds
Started May 05 01:11:15 PM PDT 24
Finished May 05 01:11:37 PM PDT 24
Peak memory 316628 kb
Host smart-07ecfc40-0013-4ac0-b6cb-da8c2a0f6d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020543102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4020543102
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2184611555
Short name T685
Test name
Test status
Simulation time 825022325 ps
CPU time 2.53 seconds
Started May 05 01:11:17 PM PDT 24
Finished May 05 01:11:20 PM PDT 24
Peak memory 203804 kb
Host smart-94ec7921-03b8-407c-9c88-76bbf332e4d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184611555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2184611555
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3634532428
Short name T512
Test name
Test status
Simulation time 861803070 ps
CPU time 4.36 seconds
Started May 05 01:11:24 PM PDT 24
Finished May 05 01:11:29 PM PDT 24
Peak memory 203868 kb
Host smart-261989f5-9c27-41d5-9f62-5dc50109c0c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634532428 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3634532428
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3903493412
Short name T883
Test name
Test status
Simulation time 23532225835 ps
CPU time 179.11 seconds
Started May 05 01:11:11 PM PDT 24
Finished May 05 01:14:11 PM PDT 24
Peak memory 2883808 kb
Host smart-b7bf351e-38c0-4e00-8bdd-f01bbf9c420f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903493412 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3903493412
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4251959755
Short name T611
Test name
Test status
Simulation time 1209974933 ps
CPU time 48.72 seconds
Started May 05 01:11:10 PM PDT 24
Finished May 05 01:12:00 PM PDT 24
Peak memory 203808 kb
Host smart-1bebe406-1170-4276-8653-ccde712db0d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251959755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4251959755
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.219538111
Short name T755
Test name
Test status
Simulation time 2112195720 ps
CPU time 9.81 seconds
Started May 05 01:11:12 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 203868 kb
Host smart-516dee67-d803-4f29-90ca-89c6d7cc5637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219538111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.219538111
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3842192446
Short name T1054
Test name
Test status
Simulation time 26840196816 ps
CPU time 50.87 seconds
Started May 05 01:11:13 PM PDT 24
Finished May 05 01:12:05 PM PDT 24
Peak memory 933544 kb
Host smart-48cf87cf-28c4-4395-9db1-ddcb58e33462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842192446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3842192446
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2115849531
Short name T544
Test name
Test status
Simulation time 32559253646 ps
CPU time 2090.52 seconds
Started May 05 01:11:12 PM PDT 24
Finished May 05 01:46:03 PM PDT 24
Peak memory 3822192 kb
Host smart-49fcab36-1b10-4efa-a619-31f10b3afd55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115849531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2115849531
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1782481258
Short name T476
Test name
Test status
Simulation time 6043899672 ps
CPU time 7.35 seconds
Started May 05 01:11:13 PM PDT 24
Finished May 05 01:11:20 PM PDT 24
Peak memory 214580 kb
Host smart-f99d9172-ed41-4653-8fa0-80760ec37ef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782481258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1782481258
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.4035132264
Short name T813
Test name
Test status
Simulation time 17996481 ps
CPU time 0.61 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:11:28 PM PDT 24
Peak memory 203728 kb
Host smart-131ff04f-4dd0-47b9-883d-d40f35b2035c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035132264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.4035132264
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2976487856
Short name T819
Test name
Test status
Simulation time 90489987 ps
CPU time 1.28 seconds
Started May 05 01:11:23 PM PDT 24
Finished May 05 01:11:25 PM PDT 24
Peak memory 212092 kb
Host smart-e5380b9f-b28d-4e9d-8637-ffd14af1adde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976487856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2976487856
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3152374816
Short name T638
Test name
Test status
Simulation time 394512482 ps
CPU time 8.54 seconds
Started May 05 01:11:21 PM PDT 24
Finished May 05 01:11:30 PM PDT 24
Peak memory 285408 kb
Host smart-40ca4ce1-2355-4f48-928e-f5ff981192fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152374816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3152374816
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.944625429
Short name T492
Test name
Test status
Simulation time 1041775548 ps
CPU time 27.12 seconds
Started May 05 01:11:21 PM PDT 24
Finished May 05 01:11:49 PM PDT 24
Peak memory 297020 kb
Host smart-535c9d98-d4de-481f-a463-3a239a29b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944625429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.944625429
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1753677208
Short name T267
Test name
Test status
Simulation time 1183686006 ps
CPU time 71.29 seconds
Started May 05 01:11:15 PM PDT 24
Finished May 05 01:12:27 PM PDT 24
Peak memory 401444 kb
Host smart-910aa3bf-e2e1-442d-974e-0ae6a74e9231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753677208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1753677208
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.259629691
Short name T615
Test name
Test status
Simulation time 429738303 ps
CPU time 0.99 seconds
Started May 05 01:11:20 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 203876 kb
Host smart-66b5f900-df9f-45dc-86e3-543dc338af3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259629691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.259629691
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.4054462616
Short name T1078
Test name
Test status
Simulation time 123327475 ps
CPU time 3.37 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:26 PM PDT 24
Peak memory 223676 kb
Host smart-a0e19f61-46fa-4153-864c-9b08afa32170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054462616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.4054462616
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.802014299
Short name T283
Test name
Test status
Simulation time 3438064849 ps
CPU time 256.52 seconds
Started May 05 01:11:17 PM PDT 24
Finished May 05 01:15:34 PM PDT 24
Peak memory 1059088 kb
Host smart-3caf7dc1-a0a1-4a05-a6ef-c1b743b9d5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802014299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.802014299
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1580104097
Short name T215
Test name
Test status
Simulation time 402590023 ps
CPU time 6.12 seconds
Started May 05 01:11:26 PM PDT 24
Finished May 05 01:11:33 PM PDT 24
Peak memory 203828 kb
Host smart-5bcb6f20-9108-43f8-913c-04d665a9aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580104097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1580104097
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.1048176537
Short name T128
Test name
Test status
Simulation time 34893848 ps
CPU time 0.64 seconds
Started May 05 01:11:15 PM PDT 24
Finished May 05 01:11:16 PM PDT 24
Peak memory 203572 kb
Host smart-035d2589-cf75-4e4d-8a1f-b5ae07175326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048176537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1048176537
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.287074795
Short name T1278
Test name
Test status
Simulation time 7543135962 ps
CPU time 82.37 seconds
Started May 05 01:11:21 PM PDT 24
Finished May 05 01:12:44 PM PDT 24
Peak memory 220336 kb
Host smart-abc6c910-79cf-47b1-a17b-89a370d85b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287074795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.287074795
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1901140206
Short name T885
Test name
Test status
Simulation time 3953855319 ps
CPU time 47.95 seconds
Started May 05 01:11:18 PM PDT 24
Finished May 05 01:12:06 PM PDT 24
Peak memory 314372 kb
Host smart-ebefb3e5-ad00-43de-bba5-89d245d040fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901140206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1901140206
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.866430202
Short name T246
Test name
Test status
Simulation time 135787911791 ps
CPU time 2665.57 seconds
Started May 05 01:11:18 PM PDT 24
Finished May 05 01:55:45 PM PDT 24
Peak memory 3015020 kb
Host smart-c0930a3d-6ad7-4d65-809b-e03135de7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866430202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.866430202
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2212235638
Short name T820
Test name
Test status
Simulation time 3025671502 ps
CPU time 12.46 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:34 PM PDT 24
Peak memory 214644 kb
Host smart-cd517cbf-9a92-4a41-bbc9-a188108f3568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212235638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2212235638
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.675621391
Short name T417
Test name
Test status
Simulation time 2509792253 ps
CPU time 3.77 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:11:32 PM PDT 24
Peak memory 203932 kb
Host smart-95704b53-fde9-4dad-b4a4-e8b652e0a132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675621391 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.675621391
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3201972275
Short name T673
Test name
Test status
Simulation time 11889215504 ps
CPU time 3.35 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:26 PM PDT 24
Peak memory 220072 kb
Host smart-48a7fc93-64a0-40ee-9faa-2d9be57f72bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201972275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3201972275
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2325977655
Short name T1119
Test name
Test status
Simulation time 1958498042 ps
CPU time 2.71 seconds
Started May 05 01:11:28 PM PDT 24
Finished May 05 01:11:31 PM PDT 24
Peak memory 203820 kb
Host smart-d69f56fd-b048-4c41-8fae-fa8d086dbc39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325977655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2325977655
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3519797730
Short name T1065
Test name
Test status
Simulation time 1402848135 ps
CPU time 7.57 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:30 PM PDT 24
Peak memory 219276 kb
Host smart-497ca51e-b853-4eb7-b9a4-8cd91540e700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519797730 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3519797730
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.679535956
Short name T959
Test name
Test status
Simulation time 14169403537 ps
CPU time 276.69 seconds
Started May 05 01:11:20 PM PDT 24
Finished May 05 01:15:58 PM PDT 24
Peak memory 3541232 kb
Host smart-4e98ba0f-2f9b-4942-939e-f25670f4c02e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679535956 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.679535956
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.71219179
Short name T964
Test name
Test status
Simulation time 1398617987 ps
CPU time 19.26 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:42 PM PDT 24
Peak memory 204076 kb
Host smart-a3459fee-c9f8-40d2-b93c-575352309cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71219179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_targ
et_smoke.71219179
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2083352356
Short name T1044
Test name
Test status
Simulation time 276119982 ps
CPU time 11.68 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:34 PM PDT 24
Peak memory 203840 kb
Host smart-8908e849-412b-4956-a4fd-3539a07793e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083352356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2083352356
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1072550871
Short name T1009
Test name
Test status
Simulation time 10257261049 ps
CPU time 17.42 seconds
Started May 05 01:11:23 PM PDT 24
Finished May 05 01:11:41 PM PDT 24
Peak memory 203888 kb
Host smart-09c5cd63-8949-4c40-9acd-c1264b8c6be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072550871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1072550871
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3267211725
Short name T1122
Test name
Test status
Simulation time 14826060380 ps
CPU time 35.09 seconds
Started May 05 01:11:22 PM PDT 24
Finished May 05 01:11:58 PM PDT 24
Peak memory 528456 kb
Host smart-79c6ed10-d170-4431-a204-5ca336408b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267211725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3267211725
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1179692257
Short name T1110
Test name
Test status
Simulation time 5198723417 ps
CPU time 6.79 seconds
Started May 05 01:11:24 PM PDT 24
Finished May 05 01:11:31 PM PDT 24
Peak memory 212044 kb
Host smart-46d1f679-42d2-4bfa-b661-0506c0d6ef7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179692257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1179692257
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3721271686
Short name T713
Test name
Test status
Simulation time 20411693 ps
CPU time 0.63 seconds
Started May 05 01:11:38 PM PDT 24
Finished May 05 01:11:39 PM PDT 24
Peak memory 203736 kb
Host smart-e68d2708-5d80-4888-9695-046117b36009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721271686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3721271686
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1474311701
Short name T1060
Test name
Test status
Simulation time 76854777 ps
CPU time 1.81 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:11:30 PM PDT 24
Peak memory 220332 kb
Host smart-5e50adcc-2444-48a8-9beb-305b59c95fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474311701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1474311701
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3261823133
Short name T796
Test name
Test status
Simulation time 1489114383 ps
CPU time 8.29 seconds
Started May 05 01:11:26 PM PDT 24
Finished May 05 01:11:35 PM PDT 24
Peak memory 281988 kb
Host smart-07c2dd28-0aa4-44e8-a3b0-0c7ecbf0f4b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261823133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3261823133
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.499134252
Short name T609
Test name
Test status
Simulation time 3122541203 ps
CPU time 81.86 seconds
Started May 05 01:11:26 PM PDT 24
Finished May 05 01:12:48 PM PDT 24
Peak memory 504992 kb
Host smart-1bdd4798-3db0-4452-b536-d47e564328b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499134252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.499134252
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1673514211
Short name T1256
Test name
Test status
Simulation time 1989277497 ps
CPU time 152.43 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:14:00 PM PDT 24
Peak memory 693496 kb
Host smart-070db138-93ab-4b89-a768-330f0b0e15e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673514211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1673514211
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.166003709
Short name T1334
Test name
Test status
Simulation time 165827099 ps
CPU time 1.22 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:11:29 PM PDT 24
Peak memory 203784 kb
Host smart-bd5353ed-b041-4687-b99e-1749fcf8f891
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166003709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fm
t.166003709
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3914623611
Short name T6
Test name
Test status
Simulation time 120497397 ps
CPU time 2.67 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:11:30 PM PDT 24
Peak memory 203848 kb
Host smart-0a92f33c-ab79-43f4-be27-8b2f47b1a52f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914623611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3914623611
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3353539918
Short name T760
Test name
Test status
Simulation time 5115692821 ps
CPU time 154.87 seconds
Started May 05 01:11:25 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 745828 kb
Host smart-50b1ae9f-4ad9-4667-adcf-4df69a072200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353539918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3353539918
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.228668579
Short name T1322
Test name
Test status
Simulation time 437591136 ps
CPU time 6.96 seconds
Started May 05 01:11:35 PM PDT 24
Finished May 05 01:11:43 PM PDT 24
Peak memory 203948 kb
Host smart-36e5b53c-ab8f-4246-85a3-568c0209fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228668579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.228668579
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.1421649110
Short name T1207
Test name
Test status
Simulation time 26067158 ps
CPU time 0.66 seconds
Started May 05 01:11:26 PM PDT 24
Finished May 05 01:11:27 PM PDT 24
Peak memory 203640 kb
Host smart-3507fd71-56e2-4aa3-817a-ce1941f8c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421649110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1421649110
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2158619140
Short name T1349
Test name
Test status
Simulation time 3056243381 ps
CPU time 41.22 seconds
Started May 05 01:11:28 PM PDT 24
Finished May 05 01:12:10 PM PDT 24
Peak memory 373196 kb
Host smart-62324d2d-950b-4665-b25f-78429c44dd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158619140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2158619140
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3964448231
Short name T529
Test name
Test status
Simulation time 6025178678 ps
CPU time 87.36 seconds
Started May 05 01:11:27 PM PDT 24
Finished May 05 01:12:55 PM PDT 24
Peak memory 362580 kb
Host smart-a1214622-dbf1-4a91-a082-366033116893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964448231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3964448231
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.631196306
Short name T229
Test name
Test status
Simulation time 844971077 ps
CPU time 8.37 seconds
Started May 05 01:11:26 PM PDT 24
Finished May 05 01:11:36 PM PDT 24
Peak memory 212076 kb
Host smart-37188dac-0357-46bb-b527-25d5303d7546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631196306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.631196306
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3902038135
Short name T516
Test name
Test status
Simulation time 10125469353 ps
CPU time 72.18 seconds
Started May 05 01:11:33 PM PDT 24
Finished May 05 01:12:45 PM PDT 24
Peak memory 531396 kb
Host smart-18fdd853-9220-4936-a5f1-89c2b6ea3e66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902038135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3902038135
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.206127704
Short name T981
Test name
Test status
Simulation time 10103728179 ps
CPU time 83.42 seconds
Started May 05 01:11:33 PM PDT 24
Finished May 05 01:12:57 PM PDT 24
Peak memory 551304 kb
Host smart-bd4ae6f2-8052-4e42-9fe4-1a5cf0753424
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206127704 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.206127704
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2637620061
Short name T1004
Test name
Test status
Simulation time 625268116 ps
CPU time 2.06 seconds
Started May 05 01:11:44 PM PDT 24
Finished May 05 01:11:47 PM PDT 24
Peak memory 204084 kb
Host smart-4880d136-9391-4526-9107-a235a35eb3c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637620061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2637620061
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2641471807
Short name T801
Test name
Test status
Simulation time 1697465537 ps
CPU time 4.48 seconds
Started May 05 01:11:30 PM PDT 24
Finished May 05 01:11:35 PM PDT 24
Peak memory 203788 kb
Host smart-ac10bd6f-2b67-4070-a485-04dd10590460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641471807 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2641471807
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2546164984
Short name T735
Test name
Test status
Simulation time 11064527875 ps
CPU time 175.88 seconds
Started May 05 01:11:32 PM PDT 24
Finished May 05 01:14:29 PM PDT 24
Peak memory 2692960 kb
Host smart-32c39c11-99d5-4410-926e-b17129e8122b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546164984 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2546164984
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3776283408
Short name T1111
Test name
Test status
Simulation time 1986220359 ps
CPU time 12.28 seconds
Started May 05 01:11:31 PM PDT 24
Finished May 05 01:11:44 PM PDT 24
Peak memory 203824 kb
Host smart-b4d28bf5-cf26-45b2-b6f7-37b293646f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776283408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3776283408
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.1080153016
Short name T1243
Test name
Test status
Simulation time 85203569381 ps
CPU time 129.7 seconds
Started May 05 01:11:31 PM PDT 24
Finished May 05 01:13:41 PM PDT 24
Peak memory 837284 kb
Host smart-dfe6fc2e-4954-4cc3-9032-1a784cdae4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080153016 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.1080153016
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.4202685660
Short name T601
Test name
Test status
Simulation time 3057621130 ps
CPU time 11.57 seconds
Started May 05 01:11:31 PM PDT 24
Finished May 05 01:11:43 PM PDT 24
Peak memory 215216 kb
Host smart-342703cb-d6e0-4be2-a0b3-c17a1eeaa880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202685660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.4202685660
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2657117534
Short name T816
Test name
Test status
Simulation time 13284290338 ps
CPU time 26.04 seconds
Started May 05 01:11:32 PM PDT 24
Finished May 05 01:11:59 PM PDT 24
Peak memory 203940 kb
Host smart-8ecab7d2-60a0-459d-955d-cd5aa7791784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657117534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2657117534
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1808967287
Short name T488
Test name
Test status
Simulation time 25004259698 ps
CPU time 140.12 seconds
Started May 05 01:11:31 PM PDT 24
Finished May 05 01:13:52 PM PDT 24
Peak memory 1377276 kb
Host smart-9700596c-6c41-4a64-9673-f5fda3aa7c7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808967287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1808967287
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.417728527
Short name T26
Test name
Test status
Simulation time 1308691753 ps
CPU time 6.68 seconds
Started May 05 01:11:30 PM PDT 24
Finished May 05 01:11:38 PM PDT 24
Peak memory 208972 kb
Host smart-d523ed9c-5e91-429f-bedd-7393afb71be4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417728527 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.417728527
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.766425127
Short name T1173
Test name
Test status
Simulation time 1343079117 ps
CPU time 6.21 seconds
Started May 05 01:11:31 PM PDT 24
Finished May 05 01:11:38 PM PDT 24
Peak memory 206844 kb
Host smart-d6c79b28-e2bf-4674-b9fe-fd1c1124f0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766425127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_unexp_stop.766425127
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.34447104
Short name T545
Test name
Test status
Simulation time 19374587 ps
CPU time 0.61 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:11:49 PM PDT 24
Peak memory 203688 kb
Host smart-37ee4e6c-d814-4eec-bdd3-984d9f64f529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34447104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.34447104
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2053984090
Short name T1109
Test name
Test status
Simulation time 148186076 ps
CPU time 1.8 seconds
Started May 05 01:11:36 PM PDT 24
Finished May 05 01:11:39 PM PDT 24
Peak memory 212148 kb
Host smart-0323944c-1edd-453b-bbaa-b6929c682de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053984090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2053984090
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2501148522
Short name T371
Test name
Test status
Simulation time 1069896722 ps
CPU time 15.67 seconds
Started May 05 01:11:39 PM PDT 24
Finished May 05 01:11:55 PM PDT 24
Peak memory 266996 kb
Host smart-457b74e3-4e89-4aa8-abd6-5c2ff6eec43c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501148522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2501148522
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1467441817
Short name T430
Test name
Test status
Simulation time 2385412038 ps
CPU time 79.74 seconds
Started May 05 01:11:37 PM PDT 24
Finished May 05 01:12:58 PM PDT 24
Peak memory 713296 kb
Host smart-0327c989-bf70-47fa-9651-703bd4dfe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467441817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1467441817
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3667621982
Short name T1266
Test name
Test status
Simulation time 16632001536 ps
CPU time 55.73 seconds
Started May 05 01:11:39 PM PDT 24
Finished May 05 01:12:35 PM PDT 24
Peak memory 672660 kb
Host smart-b336a77c-3202-4ebd-aae2-22196f31db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667621982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3667621982
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2576254820
Short name T418
Test name
Test status
Simulation time 147455659 ps
CPU time 0.83 seconds
Started May 05 01:11:36 PM PDT 24
Finished May 05 01:11:38 PM PDT 24
Peak memory 203724 kb
Host smart-67abc0da-e7dc-4c0e-8267-4290c98004a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576254820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2576254820
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3578700216
Short name T303
Test name
Test status
Simulation time 2421475427 ps
CPU time 2.66 seconds
Started May 05 01:11:37 PM PDT 24
Finished May 05 01:11:40 PM PDT 24
Peak memory 203820 kb
Host smart-c7844128-f390-4256-8efe-fcf02c98684e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578700216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3578700216
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.4191015256
Short name T425
Test name
Test status
Simulation time 11214043449 ps
CPU time 184.23 seconds
Started May 05 01:11:39 PM PDT 24
Finished May 05 01:14:44 PM PDT 24
Peak memory 841876 kb
Host smart-3abaff38-a980-43dc-908c-789ddb017839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191015256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.4191015256
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2107146169
Short name T564
Test name
Test status
Simulation time 3562414207 ps
CPU time 21.45 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:12:08 PM PDT 24
Peak memory 203920 kb
Host smart-1c07b660-2ae3-4dba-8317-a785edbe0553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107146169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2107146169
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3936157593
Short name T703
Test name
Test status
Simulation time 2143333274 ps
CPU time 43.44 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 245552 kb
Host smart-3ee6cefb-1bf8-4501-8486-2916a399a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936157593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3936157593
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.2736537253
Short name T198
Test name
Test status
Simulation time 21998421 ps
CPU time 0.63 seconds
Started May 05 01:11:35 PM PDT 24
Finished May 05 01:11:36 PM PDT 24
Peak memory 203684 kb
Host smart-37ec5e77-66de-4f06-b2cd-73004bff1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736537253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2736537253
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1679665608
Short name T1105
Test name
Test status
Simulation time 29854368309 ps
CPU time 1245.69 seconds
Started May 05 01:11:36 PM PDT 24
Finished May 05 01:32:22 PM PDT 24
Peak memory 203864 kb
Host smart-52af7b44-8bac-4155-b73a-af5016957216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679665608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1679665608
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3707608123
Short name T1223
Test name
Test status
Simulation time 2197450401 ps
CPU time 17.46 seconds
Started May 05 01:11:37 PM PDT 24
Finished May 05 01:11:55 PM PDT 24
Peak memory 307916 kb
Host smart-9c487e3c-b61e-4616-a41e-89a84732f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707608123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3707608123
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3753712978
Short name T189
Test name
Test status
Simulation time 38460505374 ps
CPU time 322.01 seconds
Started May 05 01:11:38 PM PDT 24
Finished May 05 01:17:00 PM PDT 24
Peak memory 1251276 kb
Host smart-f75d1d8e-c739-4bb0-a489-5273e25b5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753712978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3753712978
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3417362854
Short name T1164
Test name
Test status
Simulation time 461344738 ps
CPU time 7.5 seconds
Started May 05 01:11:36 PM PDT 24
Finished May 05 01:11:44 PM PDT 24
Peak memory 213520 kb
Host smart-ab974f2e-3368-453a-8b97-26601f4dcd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417362854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3417362854
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2679300876
Short name T525
Test name
Test status
Simulation time 969166627 ps
CPU time 4.9 seconds
Started May 05 01:11:43 PM PDT 24
Finished May 05 01:11:48 PM PDT 24
Peak memory 212088 kb
Host smart-4d0f08a8-39a0-449c-a8dc-251583f5119e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679300876 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2679300876
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.929686156
Short name T714
Test name
Test status
Simulation time 10257593457 ps
CPU time 16.21 seconds
Started May 05 01:11:43 PM PDT 24
Finished May 05 01:12:00 PM PDT 24
Peak memory 261216 kb
Host smart-ca93cb77-56d7-4792-915e-fdfe146e3cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929686156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.929686156
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.568316947
Short name T252
Test name
Test status
Simulation time 10034031511 ps
CPU time 86.98 seconds
Started May 05 01:11:43 PM PDT 24
Finished May 05 01:13:10 PM PDT 24
Peak memory 496056 kb
Host smart-dfea194c-f381-47d2-9b62-a1587d609e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568316947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.568316947
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1947854999
Short name T1166
Test name
Test status
Simulation time 1236885148 ps
CPU time 6.42 seconds
Started May 05 01:11:43 PM PDT 24
Finished May 05 01:11:50 PM PDT 24
Peak memory 218228 kb
Host smart-e29caa7f-4639-42c2-acf6-628861d2251d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947854999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1947854999
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1876270706
Short name T888
Test name
Test status
Simulation time 14026824959 ps
CPU time 251.04 seconds
Started May 05 01:11:43 PM PDT 24
Finished May 05 01:15:55 PM PDT 24
Peak memory 3424160 kb
Host smart-c1eb2517-dea3-4c17-b049-c4026624c42b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876270706 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1876270706
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.424152427
Short name T866
Test name
Test status
Simulation time 1023825541 ps
CPU time 15.64 seconds
Started May 05 01:11:36 PM PDT 24
Finished May 05 01:11:53 PM PDT 24
Peak memory 203764 kb
Host smart-749b9206-2693-4226-9108-3e5b1a79942e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424152427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.424152427
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1328342708
Short name T1273
Test name
Test status
Simulation time 1523955705 ps
CPU time 6.09 seconds
Started May 05 01:11:44 PM PDT 24
Finished May 05 01:11:50 PM PDT 24
Peak memory 203848 kb
Host smart-012aaf63-d419-4f56-b04e-660ccab89109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328342708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1328342708
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1124267124
Short name T1231
Test name
Test status
Simulation time 9008071033 ps
CPU time 10.27 seconds
Started May 05 01:11:38 PM PDT 24
Finished May 05 01:11:49 PM PDT 24
Peak memory 203840 kb
Host smart-2b601ee6-2d69-4453-9327-19f0d3662c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124267124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1124267124
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1028650624
Short name T1363
Test name
Test status
Simulation time 21558265510 ps
CPU time 144.63 seconds
Started May 05 01:11:41 PM PDT 24
Finished May 05 01:14:07 PM PDT 24
Peak memory 1213232 kb
Host smart-e3352556-905f-41c1-8898-1d6d23227a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028650624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1028650624
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1272031669
Short name T1124
Test name
Test status
Simulation time 7414897407 ps
CPU time 6.37 seconds
Started May 05 01:11:41 PM PDT 24
Finished May 05 01:11:48 PM PDT 24
Peak memory 215992 kb
Host smart-4bda44bc-788d-4810-9f4a-eabdb8d5f192
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272031669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1272031669
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2006398677
Short name T524
Test name
Test status
Simulation time 34123487 ps
CPU time 0.62 seconds
Started May 05 01:12:14 PM PDT 24
Finished May 05 01:12:15 PM PDT 24
Peak memory 203652 kb
Host smart-a4045f85-cbe6-47e6-b734-8f41d1987a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006398677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2006398677
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3570584032
Short name T998
Test name
Test status
Simulation time 158367181 ps
CPU time 1.3 seconds
Started May 05 01:11:54 PM PDT 24
Finished May 05 01:11:56 PM PDT 24
Peak memory 212052 kb
Host smart-50cbb70d-2cbf-4430-b43c-da6c373b50a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570584032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3570584032
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3929130403
Short name T613
Test name
Test status
Simulation time 881336176 ps
CPU time 6.13 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:11:54 PM PDT 24
Peak memory 249616 kb
Host smart-4e5268c6-82e5-4db0-8047-e8afae81b8ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929130403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3929130403
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3526812281
Short name T778
Test name
Test status
Simulation time 4737594744 ps
CPU time 63.92 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:12:51 PM PDT 24
Peak memory 639192 kb
Host smart-c68b6ce2-4408-4ab2-b3fb-330717903321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526812281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3526812281
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1825280231
Short name T503
Test name
Test status
Simulation time 8252823065 ps
CPU time 73.93 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:13:00 PM PDT 24
Peak memory 716848 kb
Host smart-281994a7-f601-49ea-826a-ec34bc81905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825280231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1825280231
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2646616949
Short name T209
Test name
Test status
Simulation time 102480769 ps
CPU time 0.95 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:11:48 PM PDT 24
Peak memory 203776 kb
Host smart-d0c23c91-5680-416a-9711-9c798d0792b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646616949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2646616949
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3209173688
Short name T683
Test name
Test status
Simulation time 120302616 ps
CPU time 3.48 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:11:51 PM PDT 24
Peak memory 221712 kb
Host smart-c242f7ef-d710-452f-9973-8e36d4c4a5e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209173688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3209173688
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1143641970
Short name T1277
Test name
Test status
Simulation time 6465423420 ps
CPU time 97.55 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:13:24 PM PDT 24
Peak memory 993072 kb
Host smart-3f7a67bd-044c-4c5b-9b10-ab95e8a04705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143641970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1143641970
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2941748797
Short name T364
Test name
Test status
Simulation time 2330627033 ps
CPU time 16.56 seconds
Started May 05 01:12:14 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 203916 kb
Host smart-3d2cf549-e5ef-41ce-9517-12971cb56552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941748797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2941748797
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1240558628
Short name T567
Test name
Test status
Simulation time 4875945863 ps
CPU time 49.34 seconds
Started May 05 01:12:14 PM PDT 24
Finished May 05 01:13:03 PM PDT 24
Peak memory 244628 kb
Host smart-69aee255-3811-476b-a23b-95b096eb25ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240558628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1240558628
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1544408290
Short name T201
Test name
Test status
Simulation time 21352886 ps
CPU time 0.64 seconds
Started May 05 01:11:46 PM PDT 24
Finished May 05 01:11:48 PM PDT 24
Peak memory 203656 kb
Host smart-d265491c-5a81-4251-a7e2-b9daf4b93625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544408290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1544408290
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.140595984
Short name T1274
Test name
Test status
Simulation time 24151568988 ps
CPU time 738.29 seconds
Started May 05 01:11:44 PM PDT 24
Finished May 05 01:24:03 PM PDT 24
Peak memory 2220412 kb
Host smart-e5a54c33-538c-4d14-abf8-1115c21d29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140595984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.140595984
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.538464331
Short name T460
Test name
Test status
Simulation time 1830134053 ps
CPU time 29.31 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:12:17 PM PDT 24
Peak memory 364396 kb
Host smart-0c727e9d-0df4-4552-a431-67b41781c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538464331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.538464331
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1114706103
Short name T37
Test name
Test status
Simulation time 23029344533 ps
CPU time 1405.25 seconds
Started May 05 01:11:53 PM PDT 24
Finished May 05 01:35:19 PM PDT 24
Peak memory 2017748 kb
Host smart-509a9231-3fb0-44a6-a294-52be688593f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114706103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1114706103
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3539759259
Short name T489
Test name
Test status
Simulation time 618631379 ps
CPU time 28.95 seconds
Started May 05 01:11:47 PM PDT 24
Finished May 05 01:12:17 PM PDT 24
Peak memory 212080 kb
Host smart-846fcf31-30b7-4af4-b15b-652c9dea9b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539759259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3539759259
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.955801125
Short name T1034
Test name
Test status
Simulation time 2530005291 ps
CPU time 2.87 seconds
Started May 05 01:12:15 PM PDT 24
Finished May 05 01:12:18 PM PDT 24
Peak memory 203904 kb
Host smart-5198fd88-0cae-4dfd-8b06-42f6d5ae2ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955801125 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.955801125
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4150408817
Short name T830
Test name
Test status
Simulation time 10153171206 ps
CPU time 30.75 seconds
Started May 05 01:12:13 PM PDT 24
Finished May 05 01:12:44 PM PDT 24
Peak memory 290860 kb
Host smart-eb893690-aba4-4290-b219-e82ce4fab28d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150408817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4150408817
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2980184830
Short name T2
Test name
Test status
Simulation time 10077585371 ps
CPU time 18.19 seconds
Started May 05 01:12:16 PM PDT 24
Finished May 05 01:12:35 PM PDT 24
Peak memory 323328 kb
Host smart-832a3df2-89ed-4df7-84c0-89a735cfc9c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980184830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2980184830
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2730445966
Short name T656
Test name
Test status
Simulation time 1741592081 ps
CPU time 2.3 seconds
Started May 05 01:12:15 PM PDT 24
Finished May 05 01:12:18 PM PDT 24
Peak memory 203760 kb
Host smart-c7e78e0a-71a4-48a7-9e9a-643fc4305d7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730445966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2730445966
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2970503154
Short name T999
Test name
Test status
Simulation time 641964794 ps
CPU time 3.74 seconds
Started May 05 01:11:54 PM PDT 24
Finished May 05 01:11:58 PM PDT 24
Peak memory 203884 kb
Host smart-7e128d8a-f64d-4794-89cf-386bbc550b42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970503154 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2970503154
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2918977800
Short name T402
Test name
Test status
Simulation time 5679939204 ps
CPU time 31.41 seconds
Started May 05 01:11:54 PM PDT 24
Finished May 05 01:12:26 PM PDT 24
Peak memory 995216 kb
Host smart-0e7257e2-045d-4ebd-af14-457681dd0f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918977800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2918977800
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2784387643
Short name T265
Test name
Test status
Simulation time 1587531816 ps
CPU time 60.82 seconds
Started May 05 01:11:52 PM PDT 24
Finished May 05 01:12:53 PM PDT 24
Peak memory 203856 kb
Host smart-c5d2139e-38cf-45a4-8953-ae3c28b911d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784387643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2784387643
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1270665965
Short name T1017
Test name
Test status
Simulation time 1412413249 ps
CPU time 15.21 seconds
Started May 05 01:11:54 PM PDT 24
Finished May 05 01:12:09 PM PDT 24
Peak memory 203816 kb
Host smart-268b75b0-8152-4430-8ea8-95bf636d7188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270665965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1270665965
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2182698533
Short name T242
Test name
Test status
Simulation time 28889372174 ps
CPU time 181.62 seconds
Started May 05 01:11:54 PM PDT 24
Finished May 05 01:14:56 PM PDT 24
Peak memory 2238244 kb
Host smart-a152d56a-6a95-42dd-97ae-cd8b3b096c99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182698533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2182698533
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3069785348
Short name T710
Test name
Test status
Simulation time 7046775913 ps
CPU time 125.63 seconds
Started May 05 01:11:53 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 693468 kb
Host smart-9ea3a912-abd5-4319-8280-f5efb1a71a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069785348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3069785348
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2203578422
Short name T647
Test name
Test status
Simulation time 5526659052 ps
CPU time 7.58 seconds
Started May 05 01:11:55 PM PDT 24
Finished May 05 01:12:03 PM PDT 24
Peak memory 210064 kb
Host smart-6b65d669-13a0-44c3-85bc-d8d0b2af2d8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203578422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2203578422
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1640549843
Short name T439
Test name
Test status
Simulation time 43545135 ps
CPU time 0.58 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:25 PM PDT 24
Peak memory 203640 kb
Host smart-fb10474c-493f-4b6d-853f-690e8f89b24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640549843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1640549843
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.620738836
Short name T1328
Test name
Test status
Simulation time 216173142 ps
CPU time 1.05 seconds
Started May 05 01:12:22 PM PDT 24
Finished May 05 01:12:23 PM PDT 24
Peak memory 212124 kb
Host smart-f436996c-e6a5-41e1-8d1d-bace520cc00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620738836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.620738836
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3705245420
Short name T97
Test name
Test status
Simulation time 3005142703 ps
CPU time 13.98 seconds
Started May 05 01:12:16 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 240068 kb
Host smart-0b9b6769-e79b-4f9a-b7c3-08283aa8e1c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705245420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3705245420
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2167786686
Short name T350
Test name
Test status
Simulation time 16508816306 ps
CPU time 201.43 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:15:45 PM PDT 24
Peak memory 819928 kb
Host smart-c032fb08-6b59-4e09-a3a0-77fa2f244231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167786686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2167786686
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2103228861
Short name T403
Test name
Test status
Simulation time 1632889084 ps
CPU time 114.7 seconds
Started May 05 01:12:15 PM PDT 24
Finished May 05 01:14:10 PM PDT 24
Peak memory 568764 kb
Host smart-bee2dd16-8f4a-4cd3-8587-fc2859dff260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103228861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2103228861
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.392277886
Short name T709
Test name
Test status
Simulation time 320184192 ps
CPU time 0.85 seconds
Started May 05 01:12:14 PM PDT 24
Finished May 05 01:12:15 PM PDT 24
Peak memory 203716 kb
Host smart-93756e6e-3eb8-4e0b-b060-9b3df15c5095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392277886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.392277886
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1448227422
Short name T1267
Test name
Test status
Simulation time 258637696 ps
CPU time 7.56 seconds
Started May 05 01:12:15 PM PDT 24
Finished May 05 01:12:23 PM PDT 24
Peak memory 226692 kb
Host smart-481096b7-ce61-4e14-a7a7-1892a138dfb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448227422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1448227422
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1010698632
Short name T648
Test name
Test status
Simulation time 27723812354 ps
CPU time 225.81 seconds
Started May 05 01:12:15 PM PDT 24
Finished May 05 01:16:01 PM PDT 24
Peak memory 964588 kb
Host smart-c626fe46-b040-4bef-9012-de1b463083e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010698632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1010698632
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1851374097
Short name T987
Test name
Test status
Simulation time 3110808737 ps
CPU time 5.84 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 203828 kb
Host smart-2d0aecc0-c39a-4479-b7eb-85f03be9bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851374097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1851374097
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3087600364
Short name T426
Test name
Test status
Simulation time 5850620089 ps
CPU time 71.81 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 316688 kb
Host smart-f44820ad-2ed6-4d17-a745-1fd7d1e7414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087600364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3087600364
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1426833295
Short name T1190
Test name
Test status
Simulation time 43251034 ps
CPU time 0.64 seconds
Started May 05 01:12:13 PM PDT 24
Finished May 05 01:12:14 PM PDT 24
Peak memory 203552 kb
Host smart-07567210-d3b7-4357-bcae-db4148f16a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426833295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1426833295
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2704941854
Short name T646
Test name
Test status
Simulation time 1908509144 ps
CPU time 30.45 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:56 PM PDT 24
Peak memory 203888 kb
Host smart-33e8a571-854c-40a1-af9a-fc0e457bb02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704941854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2704941854
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1884745326
Short name T1342
Test name
Test status
Simulation time 1402703486 ps
CPU time 31.51 seconds
Started May 05 01:12:16 PM PDT 24
Finished May 05 01:12:48 PM PDT 24
Peak memory 251476 kb
Host smart-c8d4aaf5-0396-4fa0-bf61-33bfa26dd026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884745326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1884745326
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.409874340
Short name T1351
Test name
Test status
Simulation time 2514947383 ps
CPU time 28.6 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:52 PM PDT 24
Peak memory 212108 kb
Host smart-291e1ce4-ee78-41bd-9b97-23cab5ac7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409874340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.409874340
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2901908090
Short name T263
Test name
Test status
Simulation time 1398884898 ps
CPU time 4.15 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:29 PM PDT 24
Peak memory 211960 kb
Host smart-4a8bf947-d45e-43fe-8ce4-1f4ec37ae545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901908090 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2901908090
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1478963332
Short name T682
Test name
Test status
Simulation time 10436175713 ps
CPU time 12.46 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:36 PM PDT 24
Peak memory 269888 kb
Host smart-659ba74c-3a78-49bd-8825-a12b81bacfd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478963332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1478963332
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.209636012
Short name T481
Test name
Test status
Simulation time 10069130320 ps
CPU time 73.53 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:13:39 PM PDT 24
Peak memory 468032 kb
Host smart-5d0e470a-4f1c-497d-a06b-c3e754e47989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209636012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.209636012
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3999906558
Short name T20
Test name
Test status
Simulation time 2076196054 ps
CPU time 2.96 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:27 PM PDT 24
Peak memory 203852 kb
Host smart-b9ff69e2-2412-47d7-9ff6-76385564b48b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999906558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3999906558
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2449978035
Short name T343
Test name
Test status
Simulation time 915512517 ps
CPU time 4.94 seconds
Started May 05 01:12:09 PM PDT 24
Finished May 05 01:12:15 PM PDT 24
Peak memory 216980 kb
Host smart-62392f99-2deb-446a-a7fd-ed64afd488f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449978035 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2449978035
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2508856416
Short name T1058
Test name
Test status
Simulation time 3928635201 ps
CPU time 4.57 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:28 PM PDT 24
Peak memory 203864 kb
Host smart-42baafc6-e536-4376-9798-243179c3b6ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508856416 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2508856416
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.522282077
Short name T521
Test name
Test status
Simulation time 3019520653 ps
CPU time 13.13 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:36 PM PDT 24
Peak memory 203932 kb
Host smart-4fe8c7ea-5824-449e-96bb-8f506555b5ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522282077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.522282077
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2890786539
Short name T272
Test name
Test status
Simulation time 20870842986 ps
CPU time 43.79 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:13:08 PM PDT 24
Peak memory 205320 kb
Host smart-4cd274f8-0b34-4d10-94d7-8deede4d0c76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890786539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2890786539
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1623929335
Short name T291
Test name
Test status
Simulation time 8477197163 ps
CPU time 9.19 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 203828 kb
Host smart-9b2a633f-ce7b-42ad-a4e2-4787575a505a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623929335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1623929335
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.4219440863
Short name T1282
Test name
Test status
Simulation time 43837430209 ps
CPU time 146.51 seconds
Started May 05 01:12:22 PM PDT 24
Finished May 05 01:14:49 PM PDT 24
Peak memory 1301280 kb
Host smart-3d464339-0b83-421b-ad2e-ee387d8ec007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219440863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.4219440863
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3885844203
Short name T41
Test name
Test status
Simulation time 1198501722 ps
CPU time 7.18 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 218984 kb
Host smart-690bdf80-d521-4755-9be4-243852555965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885844203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3885844203
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2141017416
Short name T826
Test name
Test status
Simulation time 24951799 ps
CPU time 0.61 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:25 PM PDT 24
Peak memory 203732 kb
Host smart-bf361127-72a1-4d88-bdbd-9d9c95fff2a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141017416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2141017416
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.22725795
Short name T643
Test name
Test status
Simulation time 386187829 ps
CPU time 1.5 seconds
Started May 05 01:12:27 PM PDT 24
Finished May 05 01:12:29 PM PDT 24
Peak memory 212076 kb
Host smart-f378295b-a160-497b-aef4-c17cdfcf52a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22725795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.22725795
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1411638280
Short name T1248
Test name
Test status
Simulation time 225187813 ps
CPU time 11.29 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:36 PM PDT 24
Peak memory 244916 kb
Host smart-753aa2ed-f7fe-48a8-85bf-f0dd24fea4f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411638280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1411638280
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1143460206
Short name T1262
Test name
Test status
Simulation time 2509743193 ps
CPU time 82.66 seconds
Started May 05 01:12:26 PM PDT 24
Finished May 05 01:13:49 PM PDT 24
Peak memory 506684 kb
Host smart-d837cd06-a0d9-47c2-a3c9-ff22a0b9bc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143460206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1143460206
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1388761316
Short name T1219
Test name
Test status
Simulation time 8103472456 ps
CPU time 128.56 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:14:34 PM PDT 24
Peak memory 649400 kb
Host smart-d3244b48-6785-4744-80ee-22a89472e483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388761316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1388761316
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.2432380477
Short name T1027
Test name
Test status
Simulation time 336581114 ps
CPU time 0.89 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:26 PM PDT 24
Peak memory 203648 kb
Host smart-e3a175e2-3ec2-4d6d-983c-f6d21e6d85b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432380477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.2432380477
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.998299303
Short name T447
Test name
Test status
Simulation time 3202136856 ps
CPU time 3.64 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:29 PM PDT 24
Peak memory 203912 kb
Host smart-f45710ef-a272-4b9d-a119-f940addd43c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998299303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
998299303
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1167917949
Short name T795
Test name
Test status
Simulation time 17133990892 ps
CPU time 340.67 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:18:05 PM PDT 24
Peak memory 1271212 kb
Host smart-108c7e2f-1e38-4d8e-93e9-7d3805476af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167917949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1167917949
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1877437178
Short name T480
Test name
Test status
Simulation time 1276007485 ps
CPU time 19.33 seconds
Started May 05 01:12:28 PM PDT 24
Finished May 05 01:12:47 PM PDT 24
Peak memory 295496 kb
Host smart-09109b0d-10ba-418d-848b-06fbcdcc3fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877437178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1877437178
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.762709065
Short name T1272
Test name
Test status
Simulation time 51824487 ps
CPU time 0.63 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:12:25 PM PDT 24
Peak memory 203640 kb
Host smart-c1df7d9a-fca8-4729-b4e1-269b16c4b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762709065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.762709065
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1643898802
Short name T1112
Test name
Test status
Simulation time 12463583413 ps
CPU time 31.66 seconds
Started May 05 01:12:23 PM PDT 24
Finished May 05 01:12:55 PM PDT 24
Peak memory 203944 kb
Host smart-4d4923b5-c339-4284-845a-1c97082e0bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643898802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1643898802
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2282566924
Short name T1193
Test name
Test status
Simulation time 5766519159 ps
CPU time 25.3 seconds
Started May 05 01:12:26 PM PDT 24
Finished May 05 01:12:51 PM PDT 24
Peak memory 329976 kb
Host smart-084d1991-b5f3-4138-aa76-49c83a05c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282566924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2282566924
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3010204578
Short name T1261
Test name
Test status
Simulation time 31229623470 ps
CPU time 628.2 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:22:53 PM PDT 24
Peak memory 1175076 kb
Host smart-f836c770-7b26-49a7-83d0-7e967a4cd552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010204578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3010204578
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.565677136
Short name T909
Test name
Test status
Simulation time 378606313 ps
CPU time 16.58 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:42 PM PDT 24
Peak memory 211972 kb
Host smart-4463578d-f438-408e-bb2f-60d8c473a001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565677136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.565677136
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1079192561
Short name T691
Test name
Test status
Simulation time 6001811527 ps
CPU time 3.57 seconds
Started May 05 01:12:27 PM PDT 24
Finished May 05 01:12:31 PM PDT 24
Peak memory 212096 kb
Host smart-d3466159-4bcb-485d-966a-acba6676e760
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079192561 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1079192561
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.488796328
Short name T1012
Test name
Test status
Simulation time 10072393235 ps
CPU time 80.64 seconds
Started May 05 01:12:28 PM PDT 24
Finished May 05 01:13:49 PM PDT 24
Peak memory 441396 kb
Host smart-fa4cc422-adaa-4b6a-8f7a-d367364e9e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488796328 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.488796328
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3806068450
Short name T803
Test name
Test status
Simulation time 10048286012 ps
CPU time 70.84 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:13:41 PM PDT 24
Peak memory 457752 kb
Host smart-4495ed7a-2e3f-4ed7-995d-376ef9b45847
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806068450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3806068450
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.338073201
Short name T626
Test name
Test status
Simulation time 939720006 ps
CPU time 2.92 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 203848 kb
Host smart-0aaeeca5-a410-49d4-8c97-53c1cb37fe46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338073201 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.338073201
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1946870494
Short name T421
Test name
Test status
Simulation time 678509941 ps
CPU time 3.62 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:29 PM PDT 24
Peak memory 203840 kb
Host smart-30073179-60c3-4d69-8fd9-c000f784bc08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946870494 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1946870494
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2864114514
Short name T1212
Test name
Test status
Simulation time 3318538050 ps
CPU time 4.63 seconds
Started May 05 01:12:29 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 203892 kb
Host smart-5cec123c-f75b-462c-97de-c4bd55a39e72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864114514 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2864114514
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3762647952
Short name T432
Test name
Test status
Simulation time 11655467403 ps
CPU time 28.92 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:55 PM PDT 24
Peak memory 203920 kb
Host smart-c7510698-9eb0-47a7-b60b-569790d4c203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762647952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3762647952
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3048781299
Short name T1295
Test name
Test status
Simulation time 5101330059 ps
CPU time 23.3 seconds
Started May 05 01:12:26 PM PDT 24
Finished May 05 01:12:50 PM PDT 24
Peak memory 220304 kb
Host smart-d49bd999-ea1d-40ec-9ef6-e2e06048ea08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048781299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3048781299
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3933694360
Short name T825
Test name
Test status
Simulation time 37418684476 ps
CPU time 450.48 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:19:55 PM PDT 24
Peak memory 4156928 kb
Host smart-8b223474-5eea-46da-af35-29afb5db01bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933694360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3933694360
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.525366708
Short name T967
Test name
Test status
Simulation time 34767678766 ps
CPU time 899.87 seconds
Started May 05 01:12:24 PM PDT 24
Finished May 05 01:27:25 PM PDT 24
Peak memory 4183976 kb
Host smart-cb4c0b22-4ae4-46a7-9333-5e3931809ced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525366708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.525366708
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3939375517
Short name T1202
Test name
Test status
Simulation time 2748251126 ps
CPU time 7.76 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:38 PM PDT 24
Peak memory 212132 kb
Host smart-009c99a1-7448-4bdc-829d-8b2877815a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939375517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3939375517
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3678746763
Short name T898
Test name
Test status
Simulation time 28122907 ps
CPU time 0.63 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:12:33 PM PDT 24
Peak memory 203684 kb
Host smart-07ae5b71-3f10-4b7a-9ae3-32480f7e962f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678746763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3678746763
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1822112257
Short name T1037
Test name
Test status
Simulation time 316788382 ps
CPU time 1.56 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:32 PM PDT 24
Peak memory 212112 kb
Host smart-7d1643b3-282a-41ac-a0b7-80ea229b878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822112257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1822112257
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2186793573
Short name T842
Test name
Test status
Simulation time 1133216941 ps
CPU time 6.41 seconds
Started May 05 01:12:29 PM PDT 24
Finished May 05 01:12:36 PM PDT 24
Peak memory 262316 kb
Host smart-e1ebabd0-0fb4-4473-bda5-fba4c3f9bae0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186793573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2186793573
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1157629885
Short name T1033
Test name
Test status
Simulation time 9501434415 ps
CPU time 91.69 seconds
Started May 05 01:12:31 PM PDT 24
Finished May 05 01:14:03 PM PDT 24
Peak memory 771660 kb
Host smart-23f98c68-1154-43b9-8d06-0ce532be1326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157629885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1157629885
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3719232888
Short name T561
Test name
Test status
Simulation time 3879718808 ps
CPU time 140.27 seconds
Started May 05 01:12:28 PM PDT 24
Finished May 05 01:14:48 PM PDT 24
Peak memory 666180 kb
Host smart-a2b88d44-2f39-4a24-89bb-a2cd8299852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719232888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3719232888
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3017998171
Short name T736
Test name
Test status
Simulation time 239923457 ps
CPU time 0.96 seconds
Started May 05 01:12:31 PM PDT 24
Finished May 05 01:12:33 PM PDT 24
Peak memory 203720 kb
Host smart-a0182fcf-1871-43fe-a753-1edf2c8a5ca4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017998171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3017998171
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2529446279
Short name T428
Test name
Test status
Simulation time 746269134 ps
CPU time 4.93 seconds
Started May 05 01:12:26 PM PDT 24
Finished May 05 01:12:32 PM PDT 24
Peak memory 239368 kb
Host smart-5da95931-56d4-408e-81a9-96f9824c0431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529446279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2529446279
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.855594
Short name T48
Test name
Test status
Simulation time 17723543235 ps
CPU time 146.23 seconds
Started May 05 01:12:27 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 1308104 kb
Host smart-cbae238e-9a6b-41b0-a5b2-2bac2c198fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.855594
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.530627735
Short name T624
Test name
Test status
Simulation time 2841840151 ps
CPU time 26.91 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:13:01 PM PDT 24
Peak memory 203824 kb
Host smart-f30fc4dc-180c-4e39-a2a6-cddd57a28c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530627735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.530627735
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.2388860812
Short name T1063
Test name
Test status
Simulation time 1255001668 ps
CPU time 20.67 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:12:53 PM PDT 24
Peak memory 301116 kb
Host smart-cd06b27d-739f-41ab-8e9e-acba62232974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388860812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2388860812
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.471433529
Short name T929
Test name
Test status
Simulation time 26584964 ps
CPU time 0.69 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:32 PM PDT 24
Peak memory 203656 kb
Host smart-a1502fcc-4b47-48c1-bddd-eabd2a1032af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471433529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.471433529
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1456834055
Short name T1141
Test name
Test status
Simulation time 6840529915 ps
CPU time 44.29 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:13:14 PM PDT 24
Peak memory 212112 kb
Host smart-4c556dff-85f3-4a0b-bf9d-56c835f2b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456834055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1456834055
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.4068834329
Short name T502
Test name
Test status
Simulation time 8485176487 ps
CPU time 47.57 seconds
Started May 05 01:12:27 PM PDT 24
Finished May 05 01:13:15 PM PDT 24
Peak memory 312972 kb
Host smart-a2da011b-abdf-46a2-9ad8-d2f2105d5572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068834329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.4068834329
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1504744110
Short name T193
Test name
Test status
Simulation time 37196469825 ps
CPU time 289.08 seconds
Started May 05 01:12:31 PM PDT 24
Finished May 05 01:17:20 PM PDT 24
Peak memory 1895100 kb
Host smart-17109b98-633d-406c-a63b-2e73d8a3d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504744110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1504744110
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.2359709407
Short name T698
Test name
Test status
Simulation time 7185609378 ps
CPU time 10.97 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:42 PM PDT 24
Peak memory 220020 kb
Host smart-76d8cc03-c556-4f46-886f-603d940baede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359709407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.2359709407
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1617245
Short name T1201
Test name
Test status
Simulation time 478064621 ps
CPU time 2.46 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:32 PM PDT 24
Peak memory 203904 kb
Host smart-ebfdf68d-d92f-4f22-924b-7f29ad8a7895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617245 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1617245
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.48615650
Short name T85
Test name
Test status
Simulation time 10107465749 ps
CPU time 73.46 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:13:44 PM PDT 24
Peak memory 532044 kb
Host smart-926dd5f2-4028-4829-b10d-073f8b38f35c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48615650 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_acq.48615650
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3246390579
Short name T1006
Test name
Test status
Simulation time 407511217 ps
CPU time 2.45 seconds
Started May 05 01:12:25 PM PDT 24
Finished May 05 01:12:28 PM PDT 24
Peak memory 203820 kb
Host smart-16b9dba0-f0c4-459d-9dd8-c0b30f054e92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246390579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3246390579
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.210868051
Short name T101
Test name
Test status
Simulation time 6287499800 ps
CPU time 8.24 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:39 PM PDT 24
Peak memory 220172 kb
Host smart-bdd4c611-11c9-4784-8342-5d3cca12cff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210868051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.210868051
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.4188523212
Short name T989
Test name
Test status
Simulation time 14632054686 ps
CPU time 150.09 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:15:00 PM PDT 24
Peak memory 2025740 kb
Host smart-9567d9bc-60d6-4ff3-843d-bba6eca4b5c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188523212 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.4188523212
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2525264531
Short name T1361
Test name
Test status
Simulation time 5526912556 ps
CPU time 31.23 seconds
Started May 05 01:12:31 PM PDT 24
Finished May 05 01:13:03 PM PDT 24
Peak memory 203928 kb
Host smart-b7401f6d-af0c-439d-b2c7-6dedfa8c9b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525264531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2525264531
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.4039468579
Short name T28
Test name
Test status
Simulation time 451857769 ps
CPU time 8.62 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:12:40 PM PDT 24
Peak memory 203852 kb
Host smart-cafec815-e940-4e21-996d-e612515fd3b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039468579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.4039468579
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1461326080
Short name T83
Test name
Test status
Simulation time 14955580313 ps
CPU time 31.28 seconds
Started May 05 01:12:30 PM PDT 24
Finished May 05 01:13:02 PM PDT 24
Peak memory 203824 kb
Host smart-98fb1159-1418-46f1-bab4-da3512ee85e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461326080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1461326080
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3258066514
Short name T241
Test name
Test status
Simulation time 26125455762 ps
CPU time 2369.76 seconds
Started May 05 01:12:29 PM PDT 24
Finished May 05 01:52:00 PM PDT 24
Peak memory 6383888 kb
Host smart-61b0671a-c6e9-4c66-9712-33cbd45e5d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258066514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3258066514
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2030957608
Short name T517
Test name
Test status
Simulation time 14088494378 ps
CPU time 7.16 seconds
Started May 05 01:12:31 PM PDT 24
Finished May 05 01:12:39 PM PDT 24
Peak memory 218084 kb
Host smart-d76e3e6c-7b0e-47d7-933b-1482114afd2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030957608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2030957608
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.297148295
Short name T1156
Test name
Test status
Simulation time 28330636 ps
CPU time 0.66 seconds
Started May 05 01:12:46 PM PDT 24
Finished May 05 01:12:47 PM PDT 24
Peak memory 203716 kb
Host smart-9827a32c-f1c0-4254-9ba6-f21a46b1e13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297148295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.297148295
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1045231582
Short name T855
Test name
Test status
Simulation time 135602614 ps
CPU time 1.64 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 212128 kb
Host smart-7de40a5d-be2e-4b1c-a735-5e3c3a62f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045231582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1045231582
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.82203462
Short name T706
Test name
Test status
Simulation time 233859055 ps
CPU time 11.31 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:12:45 PM PDT 24
Peak memory 234856 kb
Host smart-c29d69e2-9d3d-4fc6-b27b-991a154a1423
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82203462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty
.82203462
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4053380111
Short name T1143
Test name
Test status
Simulation time 10666435373 ps
CPU time 174.81 seconds
Started May 05 01:12:39 PM PDT 24
Finished May 05 01:15:34 PM PDT 24
Peak memory 734744 kb
Host smart-bdb454e5-c29a-44f4-a2c3-c526260a1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053380111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4053380111
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2434824239
Short name T779
Test name
Test status
Simulation time 4338463362 ps
CPU time 136.31 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:14:51 PM PDT 24
Peak memory 658936 kb
Host smart-c18e2018-71dd-4c3a-94ce-b00e19f9a80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434824239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2434824239
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1354756082
Short name T711
Test name
Test status
Simulation time 299848443 ps
CPU time 0.79 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 203612 kb
Host smart-be2d4f04-ad65-4777-9ca2-4e84795dab45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354756082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1354756082
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1424758740
Short name T1019
Test name
Test status
Simulation time 124710121 ps
CPU time 3.31 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:12:37 PM PDT 24
Peak memory 220688 kb
Host smart-b5ea3f32-767a-4bc9-9f68-5e49ffb306cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424758740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1424758740
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.4155736834
Short name T1131
Test name
Test status
Simulation time 4581911807 ps
CPU time 121.36 seconds
Started May 05 01:12:28 PM PDT 24
Finished May 05 01:14:30 PM PDT 24
Peak memory 1303988 kb
Host smart-7f10b2aa-65a7-4ec2-8562-df2306d34cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155736834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.4155736834
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2899903249
Short name T223
Test name
Test status
Simulation time 299894035 ps
CPU time 4.91 seconds
Started May 05 01:12:48 PM PDT 24
Finished May 05 01:12:53 PM PDT 24
Peak memory 203852 kb
Host smart-ccfe4ac3-74af-46a4-9edb-6e22aed884aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899903249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2899903249
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2463033083
Short name T768
Test name
Test status
Simulation time 10868473071 ps
CPU time 22.13 seconds
Started May 05 01:12:46 PM PDT 24
Finished May 05 01:13:09 PM PDT 24
Peak memory 312140 kb
Host smart-f669ef4b-7899-41bd-b31e-821d3a5d8cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463033083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2463033083
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1579827579
Short name T969
Test name
Test status
Simulation time 30368112 ps
CPU time 0.67 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:12:34 PM PDT 24
Peak memory 203564 kb
Host smart-348f6932-3525-4358-ae33-384c6b23e87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579827579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1579827579
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3626549761
Short name T636
Test name
Test status
Simulation time 25136332355 ps
CPU time 160.82 seconds
Started May 05 01:12:34 PM PDT 24
Finished May 05 01:15:15 PM PDT 24
Peak memory 260360 kb
Host smart-af25b56c-136d-4ea5-b4e2-5482a1cf05e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626549761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3626549761
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1436083679
Short name T923
Test name
Test status
Simulation time 4048021962 ps
CPU time 44.14 seconds
Started May 05 01:12:34 PM PDT 24
Finished May 05 01:13:19 PM PDT 24
Peak memory 249576 kb
Host smart-71fd1a6d-0c69-4c48-b34d-d136b2d41127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436083679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1436083679
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.655545792
Short name T1176
Test name
Test status
Simulation time 13866469158 ps
CPU time 460.44 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:20:13 PM PDT 24
Peak memory 1891768 kb
Host smart-d338e593-d926-4b87-b9fd-b04897201ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655545792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.655545792
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.125953531
Short name T1047
Test name
Test status
Simulation time 2534748100 ps
CPU time 30.1 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:13:02 PM PDT 24
Peak memory 212148 kb
Host smart-11513b46-1686-4d86-821c-6740ab41f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125953531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.125953531
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2337307816
Short name T262
Test name
Test status
Simulation time 1013360885 ps
CPU time 4.78 seconds
Started May 05 01:12:46 PM PDT 24
Finished May 05 01:12:51 PM PDT 24
Peak memory 212044 kb
Host smart-9910c67f-eb3c-43f0-9f3e-e386668e81e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337307816 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2337307816
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.714546609
Short name T1263
Test name
Test status
Simulation time 10520930611 ps
CPU time 14.32 seconds
Started May 05 01:12:39 PM PDT 24
Finished May 05 01:12:54 PM PDT 24
Peak memory 249752 kb
Host smart-b89c65a0-fae4-4d21-8cfb-d02685309b2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714546609 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.714546609
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3840864854
Short name T765
Test name
Test status
Simulation time 10179176994 ps
CPU time 19.65 seconds
Started May 05 01:12:39 PM PDT 24
Finished May 05 01:12:59 PM PDT 24
Peak memory 302268 kb
Host smart-b02645cc-5ff0-4993-a31b-8b0e0c03b70b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840864854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3840864854
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1288559973
Short name T704
Test name
Test status
Simulation time 1388882351 ps
CPU time 2.2 seconds
Started May 05 01:12:48 PM PDT 24
Finished May 05 01:12:50 PM PDT 24
Peak memory 203856 kb
Host smart-43a60aec-3768-4a0d-924c-8241373c8cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288559973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1288559973
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4165883215
Short name T786
Test name
Test status
Simulation time 3206918679 ps
CPU time 7.51 seconds
Started May 05 01:12:34 PM PDT 24
Finished May 05 01:12:42 PM PDT 24
Peak memory 217628 kb
Host smart-8796e736-6aaa-4332-8fa9-6d89de4030c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165883215 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4165883215
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.349028603
Short name T1204
Test name
Test status
Simulation time 8006700338 ps
CPU time 91.8 seconds
Started May 05 01:12:35 PM PDT 24
Finished May 05 01:14:07 PM PDT 24
Peak memory 1980712 kb
Host smart-01350662-ef5b-4d94-8520-2414c57d1799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349028603 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.349028603
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3460559743
Short name T1170
Test name
Test status
Simulation time 642061664 ps
CPU time 10.14 seconds
Started May 05 01:12:34 PM PDT 24
Finished May 05 01:12:45 PM PDT 24
Peak memory 204004 kb
Host smart-cbc639b5-dd31-4962-8baa-a572c51a9699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460559743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3460559743
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1073894692
Short name T603
Test name
Test status
Simulation time 1349194261 ps
CPU time 25.51 seconds
Started May 05 01:12:39 PM PDT 24
Finished May 05 01:13:05 PM PDT 24
Peak memory 223572 kb
Host smart-f616f633-747e-4850-b847-a2f32a65ae61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073894692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1073894692
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2720190444
Short name T908
Test name
Test status
Simulation time 54571554347 ps
CPU time 59.74 seconds
Started May 05 01:12:32 PM PDT 24
Finished May 05 01:13:32 PM PDT 24
Peak memory 1016460 kb
Host smart-cff0e576-a5d2-4ff8-a445-1aecc79164d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720190444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2720190444
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1018000030
Short name T1230
Test name
Test status
Simulation time 11826521701 ps
CPU time 1372.57 seconds
Started May 05 01:12:33 PM PDT 24
Finished May 05 01:35:27 PM PDT 24
Peak memory 2859044 kb
Host smart-0414781c-4005-4bfe-93c1-0ffbfc347d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018000030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1018000030
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2028152409
Short name T1252
Test name
Test status
Simulation time 8371311765 ps
CPU time 7.31 seconds
Started May 05 01:12:39 PM PDT 24
Finished May 05 01:12:47 PM PDT 24
Peak memory 216548 kb
Host smart-69d44ddc-5edb-43fd-a053-3c4d40641bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028152409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2028152409
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2880668213
Short name T112
Test name
Test status
Simulation time 47670415 ps
CPU time 0.58 seconds
Started May 05 01:09:42 PM PDT 24
Finished May 05 01:09:44 PM PDT 24
Peak memory 203732 kb
Host smart-698ec265-dae2-4c47-ada3-11ed31b1486f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880668213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2880668213
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1266048283
Short name T381
Test name
Test status
Simulation time 204482730 ps
CPU time 1.12 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:09:40 PM PDT 24
Peak memory 203904 kb
Host smart-d94fd138-c806-4635-b1dd-763c055899af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266048283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1266048283
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2738587640
Short name T1249
Test name
Test status
Simulation time 479282881 ps
CPU time 12.78 seconds
Started May 05 01:09:35 PM PDT 24
Finished May 05 01:09:49 PM PDT 24
Peak memory 254044 kb
Host smart-6072c48c-8f16-42d1-93e9-a9356df95524
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738587640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2738587640
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.510845703
Short name T1198
Test name
Test status
Simulation time 6984873075 ps
CPU time 96.64 seconds
Started May 05 01:09:41 PM PDT 24
Finished May 05 01:11:18 PM PDT 24
Peak memory 567608 kb
Host smart-0c5ef6fa-d137-481d-913e-70462d49e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510845703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.510845703
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3439107012
Short name T592
Test name
Test status
Simulation time 2217562494 ps
CPU time 160.18 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:12:19 PM PDT 24
Peak memory 729984 kb
Host smart-52f2dcaf-5e9b-4eb0-9235-eea66efb14ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439107012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3439107012
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2900723630
Short name T674
Test name
Test status
Simulation time 497374040 ps
CPU time 0.94 seconds
Started May 05 01:09:41 PM PDT 24
Finished May 05 01:09:43 PM PDT 24
Peak memory 203860 kb
Host smart-0a43d257-5dff-4218-9081-a13aef7bc375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900723630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2900723630
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.202803189
Short name T1346
Test name
Test status
Simulation time 145566372 ps
CPU time 4.62 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:09:43 PM PDT 24
Peak memory 229552 kb
Host smart-7d8ad073-07db-4b3f-9e04-09d0fbe3e66a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202803189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.202803189
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1818520538
Short name T1185
Test name
Test status
Simulation time 36843579266 ps
CPU time 59.73 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:10:38 PM PDT 24
Peak memory 755112 kb
Host smart-d4143529-5332-44e2-9be5-8c1f1923811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818520538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1818520538
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1623935374
Short name T770
Test name
Test status
Simulation time 484162921 ps
CPU time 18.86 seconds
Started May 05 01:09:43 PM PDT 24
Finished May 05 01:10:02 PM PDT 24
Peak memory 203812 kb
Host smart-bc539060-59c8-48b6-8ba5-393397714f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623935374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1623935374
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2259294441
Short name T416
Test name
Test status
Simulation time 1698910668 ps
CPU time 27.19 seconds
Started May 05 01:09:43 PM PDT 24
Finished May 05 01:10:11 PM PDT 24
Peak memory 358484 kb
Host smart-ada9de7c-65c8-4762-bc62-ff9b31db8b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259294441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2259294441
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3149566943
Short name T1070
Test name
Test status
Simulation time 47853237 ps
CPU time 0.64 seconds
Started May 05 01:09:37 PM PDT 24
Finished May 05 01:09:38 PM PDT 24
Peak memory 203660 kb
Host smart-34e3e18a-7ee3-4fc2-935f-af2508fcd49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149566943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3149566943
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2407556603
Short name T789
Test name
Test status
Simulation time 6327304887 ps
CPU time 32.74 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:10:11 PM PDT 24
Peak memory 212160 kb
Host smart-021b5cb4-b884-47cd-bd37-4dbd900aeb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407556603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2407556603
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2574298858
Short name T126
Test name
Test status
Simulation time 15813665117 ps
CPU time 43.34 seconds
Started May 05 01:09:36 PM PDT 24
Finished May 05 01:10:20 PM PDT 24
Peak memory 379744 kb
Host smart-0668ae4c-72fe-45cf-8084-9ae1064660d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574298858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2574298858
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.2163922311
Short name T467
Test name
Test status
Simulation time 54120743098 ps
CPU time 1743.22 seconds
Started May 05 01:09:44 PM PDT 24
Finished May 05 01:38:48 PM PDT 24
Peak memory 2685292 kb
Host smart-4355e085-f028-4375-992d-0a6bed5edd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163922311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.2163922311
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2100476671
Short name T741
Test name
Test status
Simulation time 922757585 ps
CPU time 8.14 seconds
Started May 05 01:09:37 PM PDT 24
Finished May 05 01:09:45 PM PDT 24
Peak memory 212016 kb
Host smart-edc3a8a2-8907-4165-8bae-7bea2053e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100476671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2100476671
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1374989606
Short name T118
Test name
Test status
Simulation time 36558844 ps
CPU time 0.85 seconds
Started May 05 01:09:42 PM PDT 24
Finished May 05 01:09:44 PM PDT 24
Peak memory 221352 kb
Host smart-b4964720-b492-4864-aaca-805bebeb73b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374989606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1374989606
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.938356718
Short name T904
Test name
Test status
Simulation time 835578305 ps
CPU time 3.89 seconds
Started May 05 01:09:42 PM PDT 24
Finished May 05 01:09:47 PM PDT 24
Peak memory 203840 kb
Host smart-7420b6e7-ad0f-4f7c-92f1-00f6c1d0052a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938356718 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.938356718
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1680203657
Short name T1189
Test name
Test status
Simulation time 10118055652 ps
CPU time 76.08 seconds
Started May 05 01:09:46 PM PDT 24
Finished May 05 01:11:03 PM PDT 24
Peak memory 499828 kb
Host smart-2efe6305-a8e8-46da-a6d1-b0d71295a01b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680203657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1680203657
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2339188039
Short name T920
Test name
Test status
Simulation time 10088996803 ps
CPU time 43.95 seconds
Started May 05 01:09:42 PM PDT 24
Finished May 05 01:10:26 PM PDT 24
Peak memory 374344 kb
Host smart-d58367be-fc79-4a48-9781-066cdb0fcf23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339188039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2339188039
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.899197558
Short name T962
Test name
Test status
Simulation time 530403859 ps
CPU time 3.24 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:09:50 PM PDT 24
Peak memory 203868 kb
Host smart-3d94b623-d77d-483a-a353-5e6efb6fde13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899197558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.899197558
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3158931653
Short name T1046
Test name
Test status
Simulation time 1222068565 ps
CPU time 6.51 seconds
Started May 05 01:09:37 PM PDT 24
Finished May 05 01:09:44 PM PDT 24
Peak memory 217192 kb
Host smart-e9c84f3e-4ea0-4efa-88f5-5d7c54e79efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158931653 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3158931653
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2228764485
Short name T347
Test name
Test status
Simulation time 14459631229 ps
CPU time 33.93 seconds
Started May 05 01:09:41 PM PDT 24
Finished May 05 01:10:16 PM PDT 24
Peak memory 943336 kb
Host smart-b4fad299-1791-4fab-8259-12394462998a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228764485 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2228764485
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1293850214
Short name T996
Test name
Test status
Simulation time 3654761400 ps
CPU time 12.42 seconds
Started May 05 01:09:43 PM PDT 24
Finished May 05 01:09:56 PM PDT 24
Peak memory 203848 kb
Host smart-86dab939-32da-46e4-bcf3-78504ed76a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293850214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1293850214
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3405290922
Short name T485
Test name
Test status
Simulation time 2006148493 ps
CPU time 15.62 seconds
Started May 05 01:09:38 PM PDT 24
Finished May 05 01:09:54 PM PDT 24
Peak memory 221360 kb
Host smart-cb338db3-64c5-4116-b97c-ce521793204d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405290922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3405290922
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.4222723302
Short name T730
Test name
Test status
Simulation time 43266025078 ps
CPU time 509.1 seconds
Started May 05 01:09:39 PM PDT 24
Finished May 05 01:18:08 PM PDT 24
Peak memory 4033272 kb
Host smart-4ed3291b-0f30-43ad-a6a5-5d690751da5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222723302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.4222723302
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1590547461
Short name T555
Test name
Test status
Simulation time 11877208507 ps
CPU time 52.77 seconds
Started May 05 01:09:40 PM PDT 24
Finished May 05 01:10:33 PM PDT 24
Peak memory 667324 kb
Host smart-e7b4cc12-00c5-4cdc-8f79-91cfe010a5bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590547461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1590547461
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1306121959
Short name T1107
Test name
Test status
Simulation time 35784900 ps
CPU time 0.61 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:12:59 PM PDT 24
Peak memory 203724 kb
Host smart-90246215-1f9a-4860-aaa5-3a2146056085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306121959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1306121959
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2480638954
Short name T188
Test name
Test status
Simulation time 330383593 ps
CPU time 1.65 seconds
Started May 05 01:12:53 PM PDT 24
Finished May 05 01:12:55 PM PDT 24
Peak memory 203392 kb
Host smart-cc9ab343-11a7-4e50-952b-1937badf0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480638954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2480638954
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.715843956
Short name T304
Test name
Test status
Simulation time 669816184 ps
CPU time 8.28 seconds
Started May 05 01:12:53 PM PDT 24
Finished May 05 01:13:01 PM PDT 24
Peak memory 234464 kb
Host smart-f45a1b4f-044e-4efd-b731-696fb39f4196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715843956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.715843956
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3607073247
Short name T695
Test name
Test status
Simulation time 1733060152 ps
CPU time 57.48 seconds
Started May 05 01:12:49 PM PDT 24
Finished May 05 01:13:47 PM PDT 24
Peak memory 634904 kb
Host smart-444b1227-bdfb-4912-b816-d9d947ef023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607073247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3607073247
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3301463902
Short name T1306
Test name
Test status
Simulation time 8156677649 ps
CPU time 62.81 seconds
Started May 05 01:12:48 PM PDT 24
Finished May 05 01:13:51 PM PDT 24
Peak memory 693084 kb
Host smart-ab29346c-a860-4bcc-adef-8ae9504387de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301463902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3301463902
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3535056927
Short name T212
Test name
Test status
Simulation time 171907254 ps
CPU time 1.09 seconds
Started May 05 01:12:48 PM PDT 24
Finished May 05 01:12:49 PM PDT 24
Peak memory 203720 kb
Host smart-72016785-daec-46dd-9354-395e8c2fbbb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535056927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3535056927
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3477891681
Short name T365
Test name
Test status
Simulation time 472606385 ps
CPU time 7.14 seconds
Started May 05 01:12:53 PM PDT 24
Finished May 05 01:13:00 PM PDT 24
Peak memory 223880 kb
Host smart-447dc74b-7483-428a-9d14-8bfc507dd55d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477891681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3477891681
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3290666163
Short name T893
Test name
Test status
Simulation time 5242525958 ps
CPU time 53.25 seconds
Started May 05 01:12:49 PM PDT 24
Finished May 05 01:13:43 PM PDT 24
Peak memory 840804 kb
Host smart-5749a148-4292-4d96-8f23-e7b0a461324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290666163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3290666163
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3542652196
Short name T68
Test name
Test status
Simulation time 458788160 ps
CPU time 5.53 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:13:05 PM PDT 24
Peak memory 203828 kb
Host smart-c30917c8-c4fd-4f1b-8e97-d8925a36522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542652196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3542652196
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1222403254
Short name T1234
Test name
Test status
Simulation time 2251708195 ps
CPU time 21.01 seconds
Started May 05 01:13:04 PM PDT 24
Finished May 05 01:13:26 PM PDT 24
Peak memory 284036 kb
Host smart-29bd6188-18fb-4aae-8700-1b3d9fd73028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222403254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1222403254
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.4276810230
Short name T196
Test name
Test status
Simulation time 56316729 ps
CPU time 0.63 seconds
Started May 05 01:12:48 PM PDT 24
Finished May 05 01:12:49 PM PDT 24
Peak memory 203552 kb
Host smart-ae84982d-09c9-42a6-9c47-18ad87419b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276810230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.4276810230
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.4211049943
Short name T1163
Test name
Test status
Simulation time 12098215019 ps
CPU time 607.03 seconds
Started May 05 01:12:50 PM PDT 24
Finished May 05 01:22:58 PM PDT 24
Peak memory 2538216 kb
Host smart-73153acb-36f6-4a0b-97d7-65333f277096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211049943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4211049943
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3359469823
Short name T336
Test name
Test status
Simulation time 1104471136 ps
CPU time 19.05 seconds
Started May 05 01:12:41 PM PDT 24
Finished May 05 01:13:00 PM PDT 24
Peak memory 263148 kb
Host smart-d8595a61-f8f7-4a0c-a4cd-ed99ca92b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359469823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3359469823
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1582275021
Short name T187
Test name
Test status
Simulation time 849500486 ps
CPU time 7.15 seconds
Started May 05 01:12:50 PM PDT 24
Finished May 05 01:12:58 PM PDT 24
Peak memory 213916 kb
Host smart-14d8512a-89cd-4431-b8bc-0048cf503a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582275021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1582275021
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3163781177
Short name T945
Test name
Test status
Simulation time 676262460 ps
CPU time 3.71 seconds
Started May 05 01:12:54 PM PDT 24
Finished May 05 01:12:58 PM PDT 24
Peak memory 203916 kb
Host smart-4411a039-0d71-4b54-bb35-a0eb492485ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163781177 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3163781177
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1859764790
Short name T1276
Test name
Test status
Simulation time 10190193476 ps
CPU time 14.52 seconds
Started May 05 01:12:51 PM PDT 24
Finished May 05 01:13:06 PM PDT 24
Peak memory 284428 kb
Host smart-bfb0fac4-1b29-49e6-8f78-ac3779bb6681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859764790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1859764790
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1815162348
Short name T983
Test name
Test status
Simulation time 10127881222 ps
CPU time 32.24 seconds
Started May 05 01:12:52 PM PDT 24
Finished May 05 01:13:25 PM PDT 24
Peak memory 398732 kb
Host smart-cc4798a5-ab3a-4bb7-98c0-eb527a6e4ec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815162348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1815162348
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1464219061
Short name T22
Test name
Test status
Simulation time 1052811315 ps
CPU time 1.92 seconds
Started May 05 01:12:52 PM PDT 24
Finished May 05 01:12:54 PM PDT 24
Peak memory 203844 kb
Host smart-53ec56f8-6199-4d9b-b9a7-e9f51c0c8cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464219061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1464219061
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.826650783
Short name T366
Test name
Test status
Simulation time 864004190 ps
CPU time 5.13 seconds
Started May 05 01:12:52 PM PDT 24
Finished May 05 01:12:57 PM PDT 24
Peak memory 212060 kb
Host smart-fb71e96e-83a4-45da-9f35-f922cc25c526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826650783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.826650783
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4155370467
Short name T506
Test name
Test status
Simulation time 15352257460 ps
CPU time 187.18 seconds
Started May 05 01:12:56 PM PDT 24
Finished May 05 01:16:03 PM PDT 24
Peak memory 2216972 kb
Host smart-a2084c95-2822-4eef-8daf-f399fac8aa75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155370467 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4155370467
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.596511722
Short name T1098
Test name
Test status
Simulation time 525094839 ps
CPU time 16.76 seconds
Started May 05 01:12:49 PM PDT 24
Finished May 05 01:13:07 PM PDT 24
Peak memory 203840 kb
Host smart-b940da9c-4375-4481-b03e-c96df943f22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596511722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.596511722
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.106614662
Short name T1221
Test name
Test status
Simulation time 294391107 ps
CPU time 5.06 seconds
Started May 05 01:12:52 PM PDT 24
Finished May 05 01:12:58 PM PDT 24
Peak memory 203804 kb
Host smart-7ebbabdf-69da-4f7f-aa29-fafe5a8bd41f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106614662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.106614662
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.266211336
Short name T451
Test name
Test status
Simulation time 37951774675 ps
CPU time 532.56 seconds
Started May 05 01:12:49 PM PDT 24
Finished May 05 01:21:42 PM PDT 24
Peak memory 4541572 kb
Host smart-23d226dc-503f-4ff9-bb0a-afc537bfdfac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266211336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.266211336
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3269394071
Short name T834
Test name
Test status
Simulation time 24435236107 ps
CPU time 182.84 seconds
Started May 05 01:12:53 PM PDT 24
Finished May 05 01:15:57 PM PDT 24
Peak memory 1483392 kb
Host smart-7f8e2402-d7c0-486c-bade-406b7b9d3c3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269394071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3269394071
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.413004371
Short name T637
Test name
Test status
Simulation time 2487648891 ps
CPU time 6.56 seconds
Started May 05 01:12:52 PM PDT 24
Finished May 05 01:12:58 PM PDT 24
Peak memory 213536 kb
Host smart-e12f11f3-4721-466e-a1ee-ed50e9d67117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413004371 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.413004371
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3756488618
Short name T1038
Test name
Test status
Simulation time 18601685 ps
CPU time 0.64 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:13:03 PM PDT 24
Peak memory 203652 kb
Host smart-d8a0f8af-d206-43c2-b4c0-c59a4e5ada21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756488618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3756488618
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2119349304
Short name T43
Test name
Test status
Simulation time 103203654 ps
CPU time 1.63 seconds
Started May 05 01:12:57 PM PDT 24
Finished May 05 01:12:59 PM PDT 24
Peak memory 212120 kb
Host smart-142010c3-7c03-4231-a924-c43d4d790d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119349304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2119349304
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2930993158
Short name T1135
Test name
Test status
Simulation time 373140110 ps
CPU time 3.91 seconds
Started May 05 01:13:01 PM PDT 24
Finished May 05 01:13:05 PM PDT 24
Peak memory 234768 kb
Host smart-ce119944-a897-47d0-8e33-77eba0c38da3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930993158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2930993158
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3098477061
Short name T93
Test name
Test status
Simulation time 8431426395 ps
CPU time 68.51 seconds
Started May 05 01:13:00 PM PDT 24
Finished May 05 01:14:09 PM PDT 24
Peak memory 630620 kb
Host smart-d053dbd2-d23e-46b6-b79b-698a009d697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098477061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3098477061
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3598841362
Short name T1151
Test name
Test status
Simulation time 3452658084 ps
CPU time 121.54 seconds
Started May 05 01:13:01 PM PDT 24
Finished May 05 01:15:03 PM PDT 24
Peak memory 626148 kb
Host smart-79b2289a-de9c-4a9e-ac6d-eaada36f6838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598841362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3598841362
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2141859916
Short name T1148
Test name
Test status
Simulation time 215350226 ps
CPU time 0.77 seconds
Started May 05 01:13:00 PM PDT 24
Finished May 05 01:13:01 PM PDT 24
Peak memory 203720 kb
Host smart-e4498c4a-12fd-40af-9393-2884a4c8e4f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141859916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2141859916
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.850941797
Short name T794
Test name
Test status
Simulation time 192175357 ps
CPU time 4.44 seconds
Started May 05 01:13:01 PM PDT 24
Finished May 05 01:13:06 PM PDT 24
Peak memory 203816 kb
Host smart-eab8d54f-52cf-4bee-a62c-9f1c21fc36c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850941797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
850941797
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3095640829
Short name T302
Test name
Test status
Simulation time 5751836076 ps
CPU time 204.61 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:16:23 PM PDT 24
Peak memory 889408 kb
Host smart-99c16ee0-7778-4f6b-961a-d23c24f20104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095640829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3095640829
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1110560515
Short name T1094
Test name
Test status
Simulation time 606492150 ps
CPU time 9.21 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:13:12 PM PDT 24
Peak memory 203816 kb
Host smart-991933e4-efea-407c-92ae-6e676704e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110560515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1110560515
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3083079673
Short name T1062
Test name
Test status
Simulation time 26705069415 ps
CPU time 20.86 seconds
Started May 05 01:13:01 PM PDT 24
Finished May 05 01:13:22 PM PDT 24
Peak memory 327488 kb
Host smart-7c2b86fe-c17e-4843-90a5-7224e4ac00a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083079673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3083079673
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3683718816
Short name T965
Test name
Test status
Simulation time 49775018 ps
CPU time 0.63 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:12:59 PM PDT 24
Peak memory 203672 kb
Host smart-1bf1cdf6-dd98-479c-ac11-db4558829b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683718816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3683718816
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.4101627132
Short name T571
Test name
Test status
Simulation time 26141661976 ps
CPU time 165.82 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:15:45 PM PDT 24
Peak memory 203884 kb
Host smart-91e8d976-6c7a-464f-9fb3-1ca0557cc826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101627132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.4101627132
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2747649097
Short name T871
Test name
Test status
Simulation time 2251644614 ps
CPU time 24.91 seconds
Started May 05 01:12:58 PM PDT 24
Finished May 05 01:13:23 PM PDT 24
Peak memory 326556 kb
Host smart-9e87ff6a-5d47-4fa9-b92b-7f1b47f7c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747649097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2747649097
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.4262841030
Short name T1311
Test name
Test status
Simulation time 15493843006 ps
CPU time 363.3 seconds
Started May 05 01:12:57 PM PDT 24
Finished May 05 01:19:01 PM PDT 24
Peak memory 1644248 kb
Host smart-75f04c38-9032-4e3f-a6b9-bfb3c6768afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262841030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.4262841030
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3507716315
Short name T781
Test name
Test status
Simulation time 923156784 ps
CPU time 19.9 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:13:23 PM PDT 24
Peak memory 212060 kb
Host smart-5e1c94bc-f69d-456b-b179-738adf7f3525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507716315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3507716315
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.321149117
Short name T1188
Test name
Test status
Simulation time 875781794 ps
CPU time 4.42 seconds
Started May 05 01:13:04 PM PDT 24
Finished May 05 01:13:08 PM PDT 24
Peak memory 211980 kb
Host smart-41eb0918-35ff-4b9e-b4f5-5a1305b3a584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321149117 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.321149117
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1228987567
Short name T422
Test name
Test status
Simulation time 10091014831 ps
CPU time 74.35 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:14:17 PM PDT 24
Peak memory 567432 kb
Host smart-b75bad8b-4d2f-4182-bd4f-f50eb448af7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228987567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1228987567
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1033808179
Short name T684
Test name
Test status
Simulation time 935342350 ps
CPU time 2.75 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:13:05 PM PDT 24
Peak memory 203768 kb
Host smart-5e7db77f-824f-4018-9322-a48896ee186c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033808179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1033808179
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2200606480
Short name T878
Test name
Test status
Simulation time 1459795549 ps
CPU time 4.18 seconds
Started May 05 01:13:04 PM PDT 24
Finished May 05 01:13:09 PM PDT 24
Peak memory 203840 kb
Host smart-72e3a557-57ef-48e4-8081-ae6f20bec99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200606480 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2200606480
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3947682997
Short name T1345
Test name
Test status
Simulation time 4757123238 ps
CPU time 3.57 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:13:07 PM PDT 24
Peak memory 203912 kb
Host smart-1b0ca2ea-a091-4ba5-b11a-684b4dd77657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947682997 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3947682997
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3846472739
Short name T692
Test name
Test status
Simulation time 3734320446 ps
CPU time 38.2 seconds
Started May 05 01:12:57 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 203884 kb
Host smart-d2cdefa2-3456-4310-8960-b212d16c6175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846472739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3846472739
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3280530931
Short name T441
Test name
Test status
Simulation time 1487026723 ps
CPU time 6.22 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:13:09 PM PDT 24
Peak memory 203824 kb
Host smart-72fcb1d6-7f76-4212-891d-024cc3f5056b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280530931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3280530931
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2504142667
Short name T919
Test name
Test status
Simulation time 38494487842 ps
CPU time 64.16 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:14:08 PM PDT 24
Peak memory 1129760 kb
Host smart-ba2a2ea6-6176-4ec4-b3b1-c004b018a419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504142667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2504142667
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.4286604934
Short name T1086
Test name
Test status
Simulation time 34453110423 ps
CPU time 743.55 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:25:26 PM PDT 24
Peak memory 2028976 kb
Host smart-1a0e3406-adec-474f-b767-97013258e1b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286604934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.4286604934
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3814285572
Short name T1197
Test name
Test status
Simulation time 1186590322 ps
CPU time 7.03 seconds
Started May 05 01:13:04 PM PDT 24
Finished May 05 01:13:12 PM PDT 24
Peak memory 220056 kb
Host smart-462a864c-837d-4ef4-9ad3-e03cc7d3774e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814285572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3814285572
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.865391486
Short name T1301
Test name
Test status
Simulation time 40246306 ps
CPU time 0.63 seconds
Started May 05 01:13:15 PM PDT 24
Finished May 05 01:13:16 PM PDT 24
Peak memory 203524 kb
Host smart-59f83262-a0ba-49fe-b603-acbe611aaca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865391486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.865391486
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3490448628
Short name T310
Test name
Test status
Simulation time 103487960 ps
CPU time 1.45 seconds
Started May 05 01:13:11 PM PDT 24
Finished May 05 01:13:12 PM PDT 24
Peak memory 212060 kb
Host smart-3d6310a5-d602-4832-b4cb-9e535023a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490448628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3490448628
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3356207572
Short name T668
Test name
Test status
Simulation time 502811453 ps
CPU time 4.85 seconds
Started May 05 01:13:10 PM PDT 24
Finished May 05 01:13:15 PM PDT 24
Peak memory 254696 kb
Host smart-7bc50b04-4c90-4e5f-895d-0396c5c2ddfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356207572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3356207572
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3102655229
Short name T1158
Test name
Test status
Simulation time 7310050610 ps
CPU time 135.63 seconds
Started May 05 01:13:09 PM PDT 24
Finished May 05 01:15:25 PM PDT 24
Peak memory 660660 kb
Host smart-88174291-63a9-4f09-a457-a39c081fb1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102655229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3102655229
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2866557726
Short name T859
Test name
Test status
Simulation time 2983919928 ps
CPU time 84.68 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:14:28 PM PDT 24
Peak memory 473328 kb
Host smart-576617fd-a7de-4e77-be01-79ad8cd5bc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866557726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2866557726
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2036626109
Short name T849
Test name
Test status
Simulation time 369158094 ps
CPU time 0.89 seconds
Started May 05 01:13:09 PM PDT 24
Finished May 05 01:13:10 PM PDT 24
Peak memory 203672 kb
Host smart-1afcfd6b-adc1-4d6a-a298-c8b0ebf13f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036626109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2036626109
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1623405343
Short name T1323
Test name
Test status
Simulation time 702088067 ps
CPU time 5.34 seconds
Started May 05 01:13:08 PM PDT 24
Finished May 05 01:13:13 PM PDT 24
Peak memory 203832 kb
Host smart-758ca964-8c91-4220-ad11-6c77c77b22a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623405343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1623405343
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.263126329
Short name T185
Test name
Test status
Simulation time 2583548214 ps
CPU time 55.93 seconds
Started May 05 01:13:04 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 765288 kb
Host smart-689d050e-75d2-4224-ab53-735c3b05b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263126329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.263126329
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.633014488
Short name T805
Test name
Test status
Simulation time 1357710759 ps
CPU time 5.51 seconds
Started May 05 01:13:12 PM PDT 24
Finished May 05 01:13:18 PM PDT 24
Peak memory 203912 kb
Host smart-6912cea3-4113-410b-96e2-2ee822921b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633014488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.633014488
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3940787796
Short name T294
Test name
Test status
Simulation time 3103361235 ps
CPU time 23.81 seconds
Started May 05 01:13:15 PM PDT 24
Finished May 05 01:13:39 PM PDT 24
Peak memory 309484 kb
Host smart-3d0d0ebb-e71a-428b-8836-882719b02953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940787796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3940787796
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1546595172
Short name T197
Test name
Test status
Simulation time 16886005 ps
CPU time 0.65 seconds
Started May 05 01:13:03 PM PDT 24
Finished May 05 01:13:04 PM PDT 24
Peak memory 203620 kb
Host smart-6c0d32b7-d10a-4cc0-b702-03df9215f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546595172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1546595172
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2742225795
Short name T76
Test name
Test status
Simulation time 13201518798 ps
CPU time 50.57 seconds
Started May 05 01:13:07 PM PDT 24
Finished May 05 01:13:58 PM PDT 24
Peak memory 277148 kb
Host smart-51e6e752-4fb1-41d8-8793-6cd457602eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742225795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2742225795
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.4096367897
Short name T8
Test name
Test status
Simulation time 3181172595 ps
CPU time 17.01 seconds
Started May 05 01:13:02 PM PDT 24
Finished May 05 01:13:20 PM PDT 24
Peak memory 293456 kb
Host smart-1cf355a7-dcfa-4b04-9019-287daa6beae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096367897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.4096367897
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.84389307
Short name T892
Test name
Test status
Simulation time 9495630194 ps
CPU time 542.98 seconds
Started May 05 01:13:12 PM PDT 24
Finished May 05 01:22:15 PM PDT 24
Peak memory 847572 kb
Host smart-cdf18ea1-d94c-40ab-8fba-35d8944fa6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84389307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.84389307
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1663514300
Short name T538
Test name
Test status
Simulation time 2313449195 ps
CPU time 11.12 seconds
Started May 05 01:13:06 PM PDT 24
Finished May 05 01:13:18 PM PDT 24
Peak memory 217336 kb
Host smart-162946ac-e838-4d9c-81d0-9ff308663e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663514300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1663514300
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.918398408
Short name T1136
Test name
Test status
Simulation time 3573331880 ps
CPU time 4.44 seconds
Started May 05 01:13:13 PM PDT 24
Finished May 05 01:13:18 PM PDT 24
Peak memory 203900 kb
Host smart-9b43b104-2216-4b24-bab5-fca514822344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918398408 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.918398408
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2255157726
Short name T482
Test name
Test status
Simulation time 10638763661 ps
CPU time 6.06 seconds
Started May 05 01:13:12 PM PDT 24
Finished May 05 01:13:18 PM PDT 24
Peak memory 224084 kb
Host smart-26b7301c-7a82-49d0-a436-c8c1df5d4e29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255157726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2255157726
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3772503031
Short name T107
Test name
Test status
Simulation time 10106007533 ps
CPU time 30.65 seconds
Started May 05 01:13:09 PM PDT 24
Finished May 05 01:13:41 PM PDT 24
Peak memory 323808 kb
Host smart-205447e4-9289-4e82-8c57-08acad7d015d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772503031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3772503031
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.342633460
Short name T461
Test name
Test status
Simulation time 439411419 ps
CPU time 2.54 seconds
Started May 05 01:13:15 PM PDT 24
Finished May 05 01:13:18 PM PDT 24
Peak memory 203604 kb
Host smart-6d9d64d7-c641-47a8-8723-d4413498aae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342633460 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.342633460
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2555692748
Short name T798
Test name
Test status
Simulation time 2542989201 ps
CPU time 3.25 seconds
Started May 05 01:13:11 PM PDT 24
Finished May 05 01:13:14 PM PDT 24
Peak memory 203956 kb
Host smart-a52085b3-32dd-4346-923e-859d53a89df0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555692748 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2555692748
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2539307223
Short name T297
Test name
Test status
Simulation time 6105019586 ps
CPU time 24.59 seconds
Started May 05 01:13:08 PM PDT 24
Finished May 05 01:13:34 PM PDT 24
Peak memory 820576 kb
Host smart-a20a13f3-16f5-4f0a-83da-bf949b920f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539307223 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2539307223
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3026940582
Short name T821
Test name
Test status
Simulation time 3107178196 ps
CPU time 26.57 seconds
Started May 05 01:13:09 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 203892 kb
Host smart-df49d46a-017f-40ac-84a7-74760b7061d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026940582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3026940582
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.47916757
Short name T1171
Test name
Test status
Simulation time 1418458534 ps
CPU time 59.05 seconds
Started May 05 01:13:08 PM PDT 24
Finished May 05 01:14:08 PM PDT 24
Peak memory 205444 kb
Host smart-c4d30cef-40b5-4c98-a83a-e9f345a37497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47916757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stress_rd.47916757
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2059683163
Short name T901
Test name
Test status
Simulation time 23415672511 ps
CPU time 54.13 seconds
Started May 05 01:13:06 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 854472 kb
Host smart-9321edf9-7d6a-40fa-81e8-adf4353a368f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059683163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2059683163
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3499183021
Short name T548
Test name
Test status
Simulation time 4519233406 ps
CPU time 13 seconds
Started May 05 01:13:07 PM PDT 24
Finished May 05 01:13:20 PM PDT 24
Peak memory 319152 kb
Host smart-fe88e7c3-521c-4a7f-9ed4-0421eb22b4aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499183021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3499183021
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3561057472
Short name T349
Test name
Test status
Simulation time 20243212112 ps
CPU time 6.91 seconds
Started May 05 01:13:09 PM PDT 24
Finished May 05 01:13:17 PM PDT 24
Peak memory 212128 kb
Host smart-fea667e4-da35-4175-ac31-48565481cc85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561057472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3561057472
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2326289937
Short name T359
Test name
Test status
Simulation time 17430150 ps
CPU time 0.63 seconds
Started May 05 01:13:22 PM PDT 24
Finished May 05 01:13:23 PM PDT 24
Peak memory 203652 kb
Host smart-37304011-3ee8-4732-8b2c-f9512b92e24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326289937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2326289937
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.4272454202
Short name T715
Test name
Test status
Simulation time 38741794 ps
CPU time 1.2 seconds
Started May 05 01:13:26 PM PDT 24
Finished May 05 01:13:28 PM PDT 24
Peak memory 212108 kb
Host smart-5c49cdd7-252e-4a30-a83b-bcb79b36d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272454202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.4272454202
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1185227597
Short name T470
Test name
Test status
Simulation time 1442544746 ps
CPU time 15.39 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:13:34 PM PDT 24
Peak memory 249784 kb
Host smart-8e34b814-0bd3-45a8-807a-688366a0f451
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185227597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1185227597
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1395934293
Short name T1179
Test name
Test status
Simulation time 2095965273 ps
CPU time 62.87 seconds
Started May 05 01:13:19 PM PDT 24
Finished May 05 01:14:22 PM PDT 24
Peak memory 688680 kb
Host smart-8569af5e-e9b5-49ad-b0f7-84d6a9738755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395934293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1395934293
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.4269159265
Short name T547
Test name
Test status
Simulation time 1962730336 ps
CPU time 69.18 seconds
Started May 05 01:13:20 PM PDT 24
Finished May 05 01:14:29 PM PDT 24
Peak memory 670028 kb
Host smart-2f4fb4be-0013-43f3-a92e-8559a5aaea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269159265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.4269159265
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1202802545
Short name T839
Test name
Test status
Simulation time 769037023 ps
CPU time 0.76 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:13:19 PM PDT 24
Peak memory 203712 kb
Host smart-b66197f9-4e12-4c9f-b79e-135c63555029
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202802545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1202802545
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3200748866
Short name T483
Test name
Test status
Simulation time 574473159 ps
CPU time 3.44 seconds
Started May 05 01:13:20 PM PDT 24
Finished May 05 01:13:23 PM PDT 24
Peak memory 219868 kb
Host smart-f665a2cd-f2f9-4f8a-a26b-46d13a298dfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200748866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3200748866
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3986199087
Short name T352
Test name
Test status
Simulation time 3020975125 ps
CPU time 82.51 seconds
Started May 05 01:13:12 PM PDT 24
Finished May 05 01:14:35 PM PDT 24
Peak memory 906692 kb
Host smart-6e9975ab-166a-444e-8c49-a48d1fa6638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986199087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3986199087
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2425443148
Short name T295
Test name
Test status
Simulation time 3770236697 ps
CPU time 11.34 seconds
Started May 05 01:13:24 PM PDT 24
Finished May 05 01:13:35 PM PDT 24
Peak memory 203892 kb
Host smart-9f95b57b-02ec-46e2-b37e-2d0407fe0c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425443148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2425443148
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1662359453
Short name T1167
Test name
Test status
Simulation time 4695808559 ps
CPU time 70.16 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:14:39 PM PDT 24
Peak memory 299064 kb
Host smart-9a8aee91-5a94-43cd-8751-78e2b8c58650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662359453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1662359453
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2576939640
Short name T389
Test name
Test status
Simulation time 37246672 ps
CPU time 0.63 seconds
Started May 05 01:13:11 PM PDT 24
Finished May 05 01:13:13 PM PDT 24
Peak memory 203676 kb
Host smart-c91f6858-264d-4a30-9f79-d8909fb0c3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576939640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2576939640
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2941210912
Short name T89
Test name
Test status
Simulation time 2796912740 ps
CPU time 103.02 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:15:02 PM PDT 24
Peak memory 225648 kb
Host smart-39ef12b6-9802-47f1-8bef-93764438c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941210912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2941210912
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.150356326
Short name T260
Test name
Test status
Simulation time 2627648342 ps
CPU time 10.88 seconds
Started May 05 01:13:13 PM PDT 24
Finished May 05 01:13:24 PM PDT 24
Peak memory 252064 kb
Host smart-31e2ff68-c10b-456e-bf85-063ce502e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150356326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.150356326
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.4233393207
Short name T743
Test name
Test status
Simulation time 18613692625 ps
CPU time 368.86 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:19:28 PM PDT 24
Peak memory 1092060 kb
Host smart-dc5dc98f-fad8-48f5-8e5b-f3ddb18de8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233393207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.4233393207
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2941351978
Short name T1100
Test name
Test status
Simulation time 712184714 ps
CPU time 11 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:13:29 PM PDT 24
Peak memory 219724 kb
Host smart-05cc2ea7-c780-4b7d-8d31-6eef6b312894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941351978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2941351978
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.2189038598
Short name T1075
Test name
Test status
Simulation time 3706955856 ps
CPU time 4.45 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:33 PM PDT 24
Peak memory 212828 kb
Host smart-134f0862-7e73-455d-a693-4b94fc28aa2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189038598 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2189038598
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3212857919
Short name T1309
Test name
Test status
Simulation time 10066994861 ps
CPU time 26.08 seconds
Started May 05 01:13:22 PM PDT 24
Finished May 05 01:13:49 PM PDT 24
Peak memory 352428 kb
Host smart-2ae33bea-2e96-4bfe-b2ea-99403098f044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212857919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3212857919
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.67475211
Short name T420
Test name
Test status
Simulation time 10157346122 ps
CPU time 31.11 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 341276 kb
Host smart-5ca2bea0-9196-4857-afae-715f917ee206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67475211 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_fifo_reset_tx.67475211
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3439795743
Short name T19
Test name
Test status
Simulation time 1998079388 ps
CPU time 2.61 seconds
Started May 05 01:13:25 PM PDT 24
Finished May 05 01:13:28 PM PDT 24
Peak memory 203816 kb
Host smart-6fb84350-77eb-4428-835f-a2d2a6e01eb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439795743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3439795743
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.376566911
Short name T662
Test name
Test status
Simulation time 19001464856 ps
CPU time 6.11 seconds
Started May 05 01:13:23 PM PDT 24
Finished May 05 01:13:30 PM PDT 24
Peak memory 218412 kb
Host smart-d90a5104-9b0d-4c0a-8b23-8037ecdfdf11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376566911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.376566911
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2182951504
Short name T941
Test name
Test status
Simulation time 12153500097 ps
CPU time 11.19 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:13:40 PM PDT 24
Peak memory 358296 kb
Host smart-85adf958-e483-4f49-8d84-fc52db774e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182951504 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2182951504
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1981203172
Short name T788
Test name
Test status
Simulation time 1260199946 ps
CPU time 19.79 seconds
Started May 05 01:13:18 PM PDT 24
Finished May 05 01:13:38 PM PDT 24
Peak memory 203748 kb
Host smart-8600d6c7-15d3-4419-8429-6bc9aed071d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981203172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1981203172
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2453536013
Short name T1056
Test name
Test status
Simulation time 354717013 ps
CPU time 14.52 seconds
Started May 05 01:13:23 PM PDT 24
Finished May 05 01:13:38 PM PDT 24
Peak memory 203788 kb
Host smart-a2990b1c-816f-4515-98f3-8a0d95276615
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453536013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2453536013
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2421501335
Short name T316
Test name
Test status
Simulation time 26484156055 ps
CPU time 27.06 seconds
Started May 05 01:13:21 PM PDT 24
Finished May 05 01:13:49 PM PDT 24
Peak memory 548804 kb
Host smart-23c571ed-1419-45d8-8ff2-8430aa009f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421501335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2421501335
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1546908646
Short name T1279
Test name
Test status
Simulation time 8631904456 ps
CPU time 293.72 seconds
Started May 05 01:13:22 PM PDT 24
Finished May 05 01:18:16 PM PDT 24
Peak memory 2213404 kb
Host smart-367925a0-3e93-44a8-bb79-79ea961fd3e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546908646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1546908646
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.498218821
Short name T917
Test name
Test status
Simulation time 3091393093 ps
CPU time 7.03 seconds
Started May 05 01:13:22 PM PDT 24
Finished May 05 01:13:30 PM PDT 24
Peak memory 218228 kb
Host smart-43a87f05-1de1-4122-bf3e-0a18f93b6d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498218821 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.498218821
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3397840751
Short name T1270
Test name
Test status
Simulation time 24102489 ps
CPU time 0.59 seconds
Started May 05 01:13:38 PM PDT 24
Finished May 05 01:13:39 PM PDT 24
Peak memory 203732 kb
Host smart-2c6a216f-bd68-4b79-a2f7-a0b3e5e797b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397840751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3397840751
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2085123587
Short name T1077
Test name
Test status
Simulation time 58136412 ps
CPU time 1.14 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:13:31 PM PDT 24
Peak memory 212032 kb
Host smart-2a0e16be-14b6-4070-843c-a696fa31c383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085123587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2085123587
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.1814678350
Short name T358
Test name
Test status
Simulation time 991841470 ps
CPU time 5.53 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:13:35 PM PDT 24
Peak memory 248128 kb
Host smart-7b40742f-1531-4349-b800-25b188fa63d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814678350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.1814678350
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1625582571
Short name T91
Test name
Test status
Simulation time 2154617218 ps
CPU time 140.95 seconds
Started May 05 01:13:27 PM PDT 24
Finished May 05 01:15:48 PM PDT 24
Peak memory 635960 kb
Host smart-26480e02-9a80-42aa-964e-69449278436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625582571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1625582571
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1522357058
Short name T687
Test name
Test status
Simulation time 1575633464 ps
CPU time 39.17 seconds
Started May 05 01:13:30 PM PDT 24
Finished May 05 01:14:10 PM PDT 24
Peak memory 548152 kb
Host smart-9ee1d8cc-ec12-4bc3-bac7-08f77ac0f0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522357058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1522357058
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.266999105
Short name T1113
Test name
Test status
Simulation time 139671643 ps
CPU time 1.09 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:30 PM PDT 24
Peak memory 203860 kb
Host smart-09b1c241-e7ef-4e99-a5a6-8866f6e05068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266999105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.266999105
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1342631772
Short name T1174
Test name
Test status
Simulation time 384966650 ps
CPU time 5.5 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:13:34 PM PDT 24
Peak memory 238672 kb
Host smart-4e0c0070-2c6a-4b86-afaf-c46eb3e2e992
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342631772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1342631772
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.645136815
Short name T1008
Test name
Test status
Simulation time 44787244259 ps
CPU time 322.46 seconds
Started May 05 01:13:36 PM PDT 24
Finished May 05 01:18:59 PM PDT 24
Peak memory 1176076 kb
Host smart-6a26d4be-2674-4d4b-95ed-a4c8cfca9f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645136815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.645136815
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3129737921
Short name T753
Test name
Test status
Simulation time 684463388 ps
CPU time 12.88 seconds
Started May 05 01:13:35 PM PDT 24
Finished May 05 01:13:48 PM PDT 24
Peak memory 203784 kb
Host smart-8ce17a79-72df-490b-8ed8-b3cbda60014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129737921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3129737921
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1383829490
Short name T271
Test name
Test status
Simulation time 6796499244 ps
CPU time 20.2 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 326504 kb
Host smart-14891048-3a3b-4cb7-b2de-5533cb754fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383829490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1383829490
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3766071079
Short name T854
Test name
Test status
Simulation time 40954015 ps
CPU time 0.69 seconds
Started May 05 01:13:31 PM PDT 24
Finished May 05 01:13:32 PM PDT 24
Peak memory 203672 kb
Host smart-c0129b09-5b86-4ba0-9945-bb63bf85af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766071079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3766071079
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.4165684059
Short name T1220
Test name
Test status
Simulation time 6427544413 ps
CPU time 28.8 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:58 PM PDT 24
Peak memory 309764 kb
Host smart-af820d97-feeb-4387-a196-9fb559a8f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165684059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.4165684059
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.345778704
Short name T248
Test name
Test status
Simulation time 33588682024 ps
CPU time 744.64 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:25:54 PM PDT 24
Peak memory 1596436 kb
Host smart-ec480721-efb7-4ca6-a902-fbb011641dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345778704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.345778704
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3817131370
Short name T631
Test name
Test status
Simulation time 2781572957 ps
CPU time 8.41 seconds
Started May 05 01:13:29 PM PDT 24
Finished May 05 01:13:38 PM PDT 24
Peak memory 216676 kb
Host smart-871cd84f-803c-4b39-b595-739cd7e50e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817131370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3817131370
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.468109678
Short name T818
Test name
Test status
Simulation time 539898232 ps
CPU time 3.26 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:13:44 PM PDT 24
Peak memory 211996 kb
Host smart-34e75a35-d9cd-4649-adb4-f4f5af6634bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468109678 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.468109678
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2758487852
Short name T274
Test name
Test status
Simulation time 10468002415 ps
CPU time 13.56 seconds
Started May 05 01:13:37 PM PDT 24
Finished May 05 01:13:51 PM PDT 24
Peak memory 250924 kb
Host smart-54649a33-df36-424a-86fa-c0df947f1392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758487852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2758487852
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1162890572
Short name T1
Test name
Test status
Simulation time 10053881050 ps
CPU time 67.13 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:14:47 PM PDT 24
Peak memory 446612 kb
Host smart-2797dee5-9a12-417a-9d78-0c0dcfb80a78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162890572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1162890572
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4127369124
Short name T870
Test name
Test status
Simulation time 1257818006 ps
CPU time 2.07 seconds
Started May 05 01:13:33 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 203812 kb
Host smart-1aba1295-92a9-4869-898d-c52ebd1f74c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127369124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4127369124
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1750806125
Short name T419
Test name
Test status
Simulation time 1024571401 ps
CPU time 3.18 seconds
Started May 05 01:13:32 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 203804 kb
Host smart-220a0886-1161-4614-9a0f-392ac1b6e9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750806125 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1750806125
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.212456414
Short name T463
Test name
Test status
Simulation time 13047068258 ps
CPU time 14.33 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:43 PM PDT 24
Peak memory 384644 kb
Host smart-d9ce114b-344c-4f64-ba5d-727e47d28f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212456414 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.212456414
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1308238560
Short name T1095
Test name
Test status
Simulation time 5060329321 ps
CPU time 50.9 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:14:19 PM PDT 24
Peak memory 203852 kb
Host smart-7a4535ae-70ef-4668-84b8-80b7026390a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308238560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1308238560
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1947871743
Short name T508
Test name
Test status
Simulation time 17017340468 ps
CPU time 9.85 seconds
Started May 05 01:13:28 PM PDT 24
Finished May 05 01:13:39 PM PDT 24
Peak memory 203932 kb
Host smart-f12c4855-4f56-429a-9e6b-7d9bbc3e9b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947871743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1947871743
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3574830220
Short name T541
Test name
Test status
Simulation time 3635060976 ps
CPU time 7.15 seconds
Started May 05 01:13:27 PM PDT 24
Finished May 05 01:13:35 PM PDT 24
Peak memory 212152 kb
Host smart-23fea0b0-1913-437e-a1a5-cbf76edaf626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574830220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3574830220
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3113423089
Short name T773
Test name
Test status
Simulation time 31238366 ps
CPU time 0.61 seconds
Started May 05 01:13:52 PM PDT 24
Finished May 05 01:13:54 PM PDT 24
Peak memory 203748 kb
Host smart-4f774f0a-a68c-40dd-bae9-edc00cf2df3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113423089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3113423089
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.8224079
Short name T699
Test name
Test status
Simulation time 341340899 ps
CPU time 1.91 seconds
Started May 05 01:13:38 PM PDT 24
Finished May 05 01:13:40 PM PDT 24
Peak memory 212140 kb
Host smart-38c7fa74-3256-48c7-8bfb-833c008ccb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8224079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.8224079
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.575536618
Short name T1308
Test name
Test status
Simulation time 628822634 ps
CPU time 15.56 seconds
Started May 05 01:13:33 PM PDT 24
Finished May 05 01:13:49 PM PDT 24
Peak memory 255828 kb
Host smart-746c1938-99b7-4d02-a3a3-2e33f02a36c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575536618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.575536618
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.4244734450
Short name T67
Test name
Test status
Simulation time 13227174921 ps
CPU time 59.63 seconds
Started May 05 01:13:35 PM PDT 24
Finished May 05 01:14:35 PM PDT 24
Peak memory 641752 kb
Host smart-6b147bba-71a9-49ac-818a-93821da8a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244734450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.4244734450
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4165333926
Short name T279
Test name
Test status
Simulation time 1463216751 ps
CPU time 44.63 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:14:24 PM PDT 24
Peak memory 474792 kb
Host smart-fa41c7b7-f038-415a-803c-1e12565993d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165333926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4165333926
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.4014306293
Short name T1026
Test name
Test status
Simulation time 127554203 ps
CPU time 1.06 seconds
Started May 05 01:13:35 PM PDT 24
Finished May 05 01:13:36 PM PDT 24
Peak memory 203788 kb
Host smart-c8ff2194-74c2-4d3a-a7dd-b9eac07d295d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014306293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.4014306293
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1098899275
Short name T94
Test name
Test status
Simulation time 162079444 ps
CPU time 3.74 seconds
Started May 05 01:13:33 PM PDT 24
Finished May 05 01:13:37 PM PDT 24
Peak memory 203776 kb
Host smart-ed7182d8-4229-4675-831a-0dda402f045f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098899275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1098899275
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.57004838
Short name T179
Test name
Test status
Simulation time 3881691080 ps
CPU time 87.62 seconds
Started May 05 01:13:34 PM PDT 24
Finished May 05 01:15:02 PM PDT 24
Peak memory 1021372 kb
Host smart-b49828fd-336f-4f6a-ac30-13894b9f5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57004838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.57004838
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2096732428
Short name T990
Test name
Test status
Simulation time 206969543 ps
CPU time 8.39 seconds
Started May 05 01:13:50 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 203892 kb
Host smart-3ff4d547-3e12-4ba6-9f22-cb8037d0e3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096732428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2096732428
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.778600320
Short name T1292
Test name
Test status
Simulation time 7057443374 ps
CPU time 80.41 seconds
Started May 05 01:13:45 PM PDT 24
Finished May 05 01:15:06 PM PDT 24
Peak memory 339756 kb
Host smart-90c4da75-72dc-4d4f-98b2-40cc7c6da8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778600320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.778600320
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3556370083
Short name T200
Test name
Test status
Simulation time 36283511 ps
CPU time 0.65 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:13:41 PM PDT 24
Peak memory 203668 kb
Host smart-38f10e81-fa9a-4186-ab29-b9abcfa07bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556370083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3556370083
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1529706596
Short name T74
Test name
Test status
Simulation time 390581097 ps
CPU time 17.33 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:13:58 PM PDT 24
Peak memory 231376 kb
Host smart-295ad849-fc57-4e9c-9a03-2e8251e749c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529706596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1529706596
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1081456807
Short name T324
Test name
Test status
Simulation time 3167907307 ps
CPU time 25.8 seconds
Started May 05 01:13:34 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 348236 kb
Host smart-18296657-e698-4c7c-b3d7-c9b78bf227a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081456807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1081456807
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.4145629989
Short name T1152
Test name
Test status
Simulation time 909654636 ps
CPU time 8.31 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:13:48 PM PDT 24
Peak memory 212040 kb
Host smart-5cdb50ca-ba02-471a-a272-0ccfb7291a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145629989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.4145629989
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.314994176
Short name T24
Test name
Test status
Simulation time 2297509957 ps
CPU time 3.22 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:13:42 PM PDT 24
Peak memory 203868 kb
Host smart-ffff88b0-0d1f-4c5b-b029-507c4b283f0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314994176 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.314994176
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2281248878
Short name T448
Test name
Test status
Simulation time 10180812282 ps
CPU time 13.65 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:13:55 PM PDT 24
Peak memory 269648 kb
Host smart-c9b6f6d5-33f0-47f5-b31b-5180a16f73fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281248878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2281248878
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.55668472
Short name T873
Test name
Test status
Simulation time 10117595331 ps
CPU time 23.55 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:14:03 PM PDT 24
Peak memory 305168 kb
Host smart-33e13923-a40e-4395-8019-149ace27a9d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55668472 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_fifo_reset_tx.55668472
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4093179938
Short name T1007
Test name
Test status
Simulation time 385983522 ps
CPU time 2.31 seconds
Started May 05 01:13:41 PM PDT 24
Finished May 05 01:13:44 PM PDT 24
Peak memory 203848 kb
Host smart-b8317b98-b4b7-4b6f-a98e-30b914586736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093179938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4093179938
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3278147437
Short name T511
Test name
Test status
Simulation time 18910943803 ps
CPU time 5.04 seconds
Started May 05 01:13:42 PM PDT 24
Finished May 05 01:13:47 PM PDT 24
Peak memory 203800 kb
Host smart-8e10ce47-5c84-4319-92cd-a990f3170cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278147437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3278147437
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2013931450
Short name T331
Test name
Test status
Simulation time 4887200654 ps
CPU time 18.32 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 730348 kb
Host smart-e89ec8bb-497b-441b-b195-297f37e4eddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013931450 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2013931450
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2536209360
Short name T862
Test name
Test status
Simulation time 998703975 ps
CPU time 18.81 seconds
Started May 05 01:13:40 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 203836 kb
Host smart-82bc7e2b-9921-4efa-8fe8-4542f5e0e452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536209360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2536209360
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2127394741
Short name T916
Test name
Test status
Simulation time 2124679175 ps
CPU time 8.48 seconds
Started May 05 01:13:37 PM PDT 24
Finished May 05 01:13:46 PM PDT 24
Peak memory 206660 kb
Host smart-d20963c6-82f1-4ccc-a7f0-2b05934e3f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127394741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2127394741
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2278613377
Short name T863
Test name
Test status
Simulation time 24596198896 ps
CPU time 7.05 seconds
Started May 05 01:13:41 PM PDT 24
Finished May 05 01:13:48 PM PDT 24
Peak memory 203880 kb
Host smart-58e84964-37e0-4835-9a49-32ff0b7cb1c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278613377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2278613377
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.168198089
Short name T269
Test name
Test status
Simulation time 14051585899 ps
CPU time 70.21 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 848312 kb
Host smart-85cfbc4b-84c2-489c-a416-e066ecef5640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168198089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.168198089
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2040560097
Short name T705
Test name
Test status
Simulation time 1998204633 ps
CPU time 7.43 seconds
Started May 05 01:13:39 PM PDT 24
Finished May 05 01:13:47 PM PDT 24
Peak memory 203900 kb
Host smart-3573802a-32e1-4998-af15-552312b3f98b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040560097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2040560097
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.744531726
Short name T756
Test name
Test status
Simulation time 36506607 ps
CPU time 0.6 seconds
Started May 05 01:13:53 PM PDT 24
Finished May 05 01:13:54 PM PDT 24
Peak memory 203744 kb
Host smart-11e6418a-e5ef-4007-b04e-9f6bf9e3fde4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744531726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.744531726
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1133508506
Short name T593
Test name
Test status
Simulation time 247000321 ps
CPU time 1.7 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:13:45 PM PDT 24
Peak memory 212052 kb
Host smart-564103a9-ece3-418b-9f7d-b561883252ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133508506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1133508506
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2209982801
Short name T906
Test name
Test status
Simulation time 888164648 ps
CPU time 4.58 seconds
Started May 05 01:13:45 PM PDT 24
Finished May 05 01:13:50 PM PDT 24
Peak memory 234800 kb
Host smart-7819fe89-c206-40d0-9cfc-2f80f050906f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209982801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2209982801
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2517525000
Short name T368
Test name
Test status
Simulation time 8570434554 ps
CPU time 67.54 seconds
Started May 05 01:13:45 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 618620 kb
Host smart-2aef12dc-8c36-405f-abf8-d5bbb1536886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517525000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2517525000
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1790422097
Short name T378
Test name
Test status
Simulation time 2053877509 ps
CPU time 69.44 seconds
Started May 05 01:13:47 PM PDT 24
Finished May 05 01:14:57 PM PDT 24
Peak memory 682904 kb
Host smart-ec068930-c02c-49af-9f61-38e408887638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790422097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1790422097
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.838779682
Short name T1049
Test name
Test status
Simulation time 412031928 ps
CPU time 0.93 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:13:45 PM PDT 24
Peak memory 203708 kb
Host smart-1dba7bb5-112f-41e8-bd18-92038637d4e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838779682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.838779682
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3359267959
Short name T817
Test name
Test status
Simulation time 144205737 ps
CPU time 7.89 seconds
Started May 05 01:13:53 PM PDT 24
Finished May 05 01:14:01 PM PDT 24
Peak memory 203852 kb
Host smart-3ffed767-0514-4c15-82cd-7ffe624bbb0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359267959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3359267959
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3714598494
Short name T182
Test name
Test status
Simulation time 9609759798 ps
CPU time 56.4 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:14:40 PM PDT 24
Peak memory 789748 kb
Host smart-5073039c-23d2-4a1b-80c2-0b5aa2dc6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714598494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3714598494
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.2208080720
Short name T226
Test name
Test status
Simulation time 388128328 ps
CPU time 3.71 seconds
Started May 05 01:13:54 PM PDT 24
Finished May 05 01:13:59 PM PDT 24
Peak memory 203804 kb
Host smart-771c7c7f-501c-44a8-a142-4e4aee698004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208080720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2208080720
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.583747829
Short name T1139
Test name
Test status
Simulation time 3034772231 ps
CPU time 71.63 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:15:08 PM PDT 24
Peak memory 285032 kb
Host smart-7c3465c1-c4be-484a-ad5f-30af53cb6086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583747829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.583747829
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1103267337
Short name T533
Test name
Test status
Simulation time 62991651 ps
CPU time 0.6 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:13:44 PM PDT 24
Peak memory 203668 kb
Host smart-fa86b60f-6e21-4f45-a746-910152d25276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103267337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1103267337
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3243766050
Short name T992
Test name
Test status
Simulation time 48216941997 ps
CPU time 1152.15 seconds
Started May 05 01:13:52 PM PDT 24
Finished May 05 01:33:05 PM PDT 24
Peak memory 2439068 kb
Host smart-3b3e0e84-425f-49fd-b1f7-956787709ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243766050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3243766050
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3264692778
Short name T440
Test name
Test status
Simulation time 6593518650 ps
CPU time 22.57 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:14:06 PM PDT 24
Peak memory 310800 kb
Host smart-cde6be5d-9b63-4ba7-bda1-05fdff61ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264692778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3264692778
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.46511993
Short name T973
Test name
Test status
Simulation time 772271841 ps
CPU time 6.27 seconds
Started May 05 01:13:50 PM PDT 24
Finished May 05 01:13:57 PM PDT 24
Peak memory 212060 kb
Host smart-ed4721c3-e296-4b45-b7dd-4f0eb39eef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46511993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.46511993
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.394996650
Short name T239
Test name
Test status
Simulation time 2741772965 ps
CPU time 3.48 seconds
Started May 05 01:13:49 PM PDT 24
Finished May 05 01:13:53 PM PDT 24
Peak memory 203924 kb
Host smart-64c8bf5d-6fc6-4f36-8bac-4642105c8ea3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394996650 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.394996650
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2028091456
Short name T619
Test name
Test status
Simulation time 10037013554 ps
CPU time 66.48 seconds
Started May 05 01:13:48 PM PDT 24
Finished May 05 01:14:55 PM PDT 24
Peak memory 529164 kb
Host smart-d8c88338-7f88-4561-b5d2-b3bf4f67b01a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028091456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2028091456
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2355463551
Short name T579
Test name
Test status
Simulation time 10075162050 ps
CPU time 27.48 seconds
Started May 05 01:13:48 PM PDT 24
Finished May 05 01:14:16 PM PDT 24
Peak memory 378944 kb
Host smart-9ba0b523-6d83-4b86-a224-85276effc1eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355463551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2355463551
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2254765675
Short name T1123
Test name
Test status
Simulation time 1294791728 ps
CPU time 2.46 seconds
Started May 05 01:13:48 PM PDT 24
Finished May 05 01:13:52 PM PDT 24
Peak memory 203856 kb
Host smart-339437e1-082e-439b-8126-430195c8472d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254765675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2254765675
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3640412619
Short name T754
Test name
Test status
Simulation time 1481841503 ps
CPU time 7.31 seconds
Started May 05 01:13:50 PM PDT 24
Finished May 05 01:13:58 PM PDT 24
Peak memory 220124 kb
Host smart-b16bf4da-b63f-4592-be44-f8baaa323d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640412619 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3640412619
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1734634638
Short name T1299
Test name
Test status
Simulation time 21550638445 ps
CPU time 188.34 seconds
Started May 05 01:13:48 PM PDT 24
Finished May 05 01:16:57 PM PDT 24
Peak memory 2584364 kb
Host smart-c8be080d-b930-43f3-a0df-5a39ae11653c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734634638 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1734634638
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4174271437
Short name T926
Test name
Test status
Simulation time 698662050 ps
CPU time 12.03 seconds
Started May 05 01:13:43 PM PDT 24
Finished May 05 01:13:55 PM PDT 24
Peak memory 203736 kb
Host smart-2501966b-8850-4f2c-badf-180307efe4ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174271437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4174271437
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3366527734
Short name T342
Test name
Test status
Simulation time 1514521926 ps
CPU time 26.82 seconds
Started May 05 01:13:49 PM PDT 24
Finished May 05 01:14:17 PM PDT 24
Peak memory 220016 kb
Host smart-f624d6c4-7e78-4819-9550-d33bc522339f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366527734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3366527734
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.546364772
Short name T1289
Test name
Test status
Simulation time 30011794795 ps
CPU time 216.83 seconds
Started May 05 01:13:47 PM PDT 24
Finished May 05 01:17:25 PM PDT 24
Peak memory 2537628 kb
Host smart-8483413c-4565-4186-8b6c-0c3dd1afdb3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546364772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.546364772
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3799595351
Short name T644
Test name
Test status
Simulation time 35861979176 ps
CPU time 2326.24 seconds
Started May 05 01:13:49 PM PDT 24
Finished May 05 01:52:36 PM PDT 24
Peak memory 4105148 kb
Host smart-14e307c1-6b66-40f2-a6d0-9d71aca192e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799595351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3799595351
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2438015610
Short name T1126
Test name
Test status
Simulation time 1409042330 ps
CPU time 7.39 seconds
Started May 05 01:13:47 PM PDT 24
Finished May 05 01:13:56 PM PDT 24
Peak memory 211000 kb
Host smart-a7a328ec-c632-4a05-980b-ae581bbf937e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438015610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2438015610
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.907584357
Short name T604
Test name
Test status
Simulation time 16143611 ps
CPU time 0.6 seconds
Started May 05 01:14:08 PM PDT 24
Finished May 05 01:14:10 PM PDT 24
Peak memory 203680 kb
Host smart-ef1a60a2-88dd-4a63-938b-2f48c5dbbb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907584357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.907584357
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3488404473
Short name T635
Test name
Test status
Simulation time 577834832 ps
CPU time 1.16 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:13:57 PM PDT 24
Peak memory 212072 kb
Host smart-8f34e0b3-1a92-4e89-96aa-410823bbc2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488404473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3488404473
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.486979122
Short name T266
Test name
Test status
Simulation time 229023969 ps
CPU time 5.11 seconds
Started May 05 01:13:54 PM PDT 24
Finished May 05 01:14:00 PM PDT 24
Peak memory 246732 kb
Host smart-30e27a2b-ba8f-4b34-bb18-75865dbf30e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486979122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.486979122
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3276185057
Short name T369
Test name
Test status
Simulation time 1956917422 ps
CPU time 68.79 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:15:05 PM PDT 24
Peak memory 690704 kb
Host smart-7ee5d798-9074-4eec-80b1-f2f8fa4b59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276185057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3276185057
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.719616994
Short name T608
Test name
Test status
Simulation time 4375897780 ps
CPU time 42.44 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:14:38 PM PDT 24
Peak memory 553928 kb
Host smart-55ef8ddc-b5bd-4540-89a3-f13d7774f28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719616994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.719616994
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.907114870
Short name T374
Test name
Test status
Simulation time 494388322 ps
CPU time 0.94 seconds
Started May 05 01:13:54 PM PDT 24
Finished May 05 01:13:56 PM PDT 24
Peak memory 203728 kb
Host smart-81d99919-a75a-41d6-87d6-325837f4f4ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907114870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.907114870
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2602224308
Short name T758
Test name
Test status
Simulation time 296277739 ps
CPU time 3.22 seconds
Started May 05 01:13:54 PM PDT 24
Finished May 05 01:13:57 PM PDT 24
Peak memory 223772 kb
Host smart-ed0d895f-2531-44a6-b416-673a9d43115a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602224308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2602224308
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3640549715
Short name T1114
Test name
Test status
Simulation time 11672185723 ps
CPU time 189.54 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:17:05 PM PDT 24
Peak memory 866356 kb
Host smart-e6892fa8-9c3d-4e94-b873-795e17e051df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640549715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3640549715
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.4177223339
Short name T536
Test name
Test status
Simulation time 447390118 ps
CPU time 3.74 seconds
Started May 05 01:14:09 PM PDT 24
Finished May 05 01:14:13 PM PDT 24
Peak memory 203860 kb
Host smart-e9f60b78-35c9-418e-aac8-411d782dfd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177223339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.4177223339
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2651052208
Short name T1287
Test name
Test status
Simulation time 1304746511 ps
CPU time 19.51 seconds
Started May 05 01:14:10 PM PDT 24
Finished May 05 01:14:30 PM PDT 24
Peak memory 293344 kb
Host smart-50d6727a-1642-447e-acb0-1af5b0c35f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651052208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2651052208
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.4034804383
Short name T681
Test name
Test status
Simulation time 18593049 ps
CPU time 0.64 seconds
Started May 05 01:13:53 PM PDT 24
Finished May 05 01:13:54 PM PDT 24
Peak memory 203680 kb
Host smart-e6405037-e746-4a32-8090-536a8274c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034804383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4034804383
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.142531245
Short name T621
Test name
Test status
Simulation time 1106381044 ps
CPU time 11 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:14:07 PM PDT 24
Peak memory 203900 kb
Host smart-5f412fe4-145d-443a-91f6-b16a845675a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142531245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.142531245
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3617470144
Short name T1045
Test name
Test status
Simulation time 921798291 ps
CPU time 15.03 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:14:11 PM PDT 24
Peak memory 233592 kb
Host smart-58c500ff-6c9d-4259-90dc-2cdfb2441e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617470144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3617470144
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.475558273
Short name T247
Test name
Test status
Simulation time 45077583458 ps
CPU time 1332.57 seconds
Started May 05 01:13:52 PM PDT 24
Finished May 05 01:36:05 PM PDT 24
Peak memory 1565372 kb
Host smart-c5ef4dc7-9755-48a6-a298-6d5d2233e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475558273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.475558273
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3040440171
Short name T401
Test name
Test status
Simulation time 5019303339 ps
CPU time 19.44 seconds
Started May 05 01:13:54 PM PDT 24
Finished May 05 01:14:14 PM PDT 24
Peak memory 212132 kb
Host smart-8cd2018e-6d82-4a4c-abf0-5004b5cc4596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040440171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3040440171
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3007951483
Short name T732
Test name
Test status
Simulation time 3762724522 ps
CPU time 3.99 seconds
Started May 05 01:14:08 PM PDT 24
Finished May 05 01:14:13 PM PDT 24
Peak memory 212084 kb
Host smart-43f2d231-72ae-4afc-a3fe-ed64c97ef158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007951483 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3007951483
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2865196237
Short name T727
Test name
Test status
Simulation time 10274204902 ps
CPU time 14.16 seconds
Started May 05 01:14:03 PM PDT 24
Finished May 05 01:14:18 PM PDT 24
Peak memory 269900 kb
Host smart-01c1120c-05f6-4bb7-bbab-881060b12994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865196237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2865196237
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1585670105
Short name T57
Test name
Test status
Simulation time 10383967627 ps
CPU time 7.59 seconds
Started May 05 01:14:03 PM PDT 24
Finished May 05 01:14:11 PM PDT 24
Peak memory 244960 kb
Host smart-600dca5a-8195-48c4-9435-12f18bc59740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585670105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1585670105
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3278789329
Short name T829
Test name
Test status
Simulation time 742826971 ps
CPU time 2.37 seconds
Started May 05 01:14:09 PM PDT 24
Finished May 05 01:14:12 PM PDT 24
Peak memory 203952 kb
Host smart-66015bb0-65d6-4886-96cb-52d399a11c8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278789329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3278789329
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.69131778
Short name T98
Test name
Test status
Simulation time 2140549794 ps
CPU time 6.78 seconds
Started May 05 01:14:04 PM PDT 24
Finished May 05 01:14:12 PM PDT 24
Peak memory 212080 kb
Host smart-17ce5515-77d5-46cb-8f0d-935ee4623225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69131778 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.69131778
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.133616106
Short name T280
Test name
Test status
Simulation time 11202836647 ps
CPU time 197.57 seconds
Started May 05 01:14:05 PM PDT 24
Finished May 05 01:17:23 PM PDT 24
Peak memory 2869932 kb
Host smart-5d2a1842-e63e-40b3-8919-28665f118910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133616106 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.133616106
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1101616248
Short name T572
Test name
Test status
Simulation time 1291843027 ps
CPU time 16.07 seconds
Started May 05 01:13:55 PM PDT 24
Finished May 05 01:14:12 PM PDT 24
Peak memory 203836 kb
Host smart-b6569b5c-1819-4a26-8f52-1f44d4b7e13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101616248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1101616248
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1009885592
Short name T961
Test name
Test status
Simulation time 825292724 ps
CPU time 14.92 seconds
Started May 05 01:14:04 PM PDT 24
Finished May 05 01:14:19 PM PDT 24
Peak memory 208364 kb
Host smart-ddd9e1e4-13a3-47e5-8f15-8ab274a33268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009885592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1009885592
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2174392280
Short name T675
Test name
Test status
Simulation time 20715498643 ps
CPU time 300.85 seconds
Started May 05 01:14:03 PM PDT 24
Finished May 05 01:19:05 PM PDT 24
Peak memory 1960368 kb
Host smart-81d163d1-1346-4f21-b4ec-dd4f30625257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174392280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2174392280
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1092590959
Short name T504
Test name
Test status
Simulation time 6158815116 ps
CPU time 6.94 seconds
Started May 05 01:14:04 PM PDT 24
Finished May 05 01:14:12 PM PDT 24
Peak memory 212120 kb
Host smart-66e2e5fd-2844-4f9f-97c9-d516e076065d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092590959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1092590959
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2064105756
Short name T840
Test name
Test status
Simulation time 40700672 ps
CPU time 0.57 seconds
Started May 05 01:14:30 PM PDT 24
Finished May 05 01:14:31 PM PDT 24
Peak memory 203752 kb
Host smart-cc30bfd8-cda9-46c7-a5a8-079cbf695ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064105756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2064105756
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.336898573
Short name T363
Test name
Test status
Simulation time 121184450 ps
CPU time 1.53 seconds
Started May 05 01:14:39 PM PDT 24
Finished May 05 01:14:40 PM PDT 24
Peak memory 212216 kb
Host smart-cfa19bb6-ad4a-4519-b042-d618d12a885f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336898573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.336898573
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2875273242
Short name T802
Test name
Test status
Simulation time 686597910 ps
CPU time 17.51 seconds
Started May 05 01:14:09 PM PDT 24
Finished May 05 01:14:27 PM PDT 24
Peak memory 276036 kb
Host smart-74148742-56a2-4662-8ae6-ef935367aa48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875273242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2875273242
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3132441437
Short name T311
Test name
Test status
Simulation time 3569372783 ps
CPU time 58.68 seconds
Started May 05 01:14:37 PM PDT 24
Finished May 05 01:15:36 PM PDT 24
Peak memory 631568 kb
Host smart-9847b13e-2afc-4a7c-9242-1b0fbcbdf959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132441437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3132441437
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3659688505
Short name T103
Test name
Test status
Simulation time 3204821548 ps
CPU time 42.65 seconds
Started May 05 01:14:08 PM PDT 24
Finished May 05 01:14:51 PM PDT 24
Peak memory 573304 kb
Host smart-10113222-c519-49bc-beb7-7803213a99bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659688505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3659688505
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3637454830
Short name T838
Test name
Test status
Simulation time 279549379 ps
CPU time 0.98 seconds
Started May 05 01:14:08 PM PDT 24
Finished May 05 01:14:09 PM PDT 24
Peak memory 203672 kb
Host smart-6192d411-4bc5-477b-9280-88191ccb7b30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637454830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3637454830
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2599876757
Short name T332
Test name
Test status
Simulation time 120184596 ps
CPU time 6.04 seconds
Started May 05 01:14:34 PM PDT 24
Finished May 05 01:14:41 PM PDT 24
Peak memory 219820 kb
Host smart-059187ce-b9a1-461d-994c-7bcb0f8ae923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599876757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2599876757
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2445602431
Short name T1228
Test name
Test status
Simulation time 16631257235 ps
CPU time 275.35 seconds
Started May 05 01:14:09 PM PDT 24
Finished May 05 01:18:45 PM PDT 24
Peak memory 1115892 kb
Host smart-51d438a7-b10b-454e-a270-556eed8935f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445602431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2445602431
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2484363499
Short name T542
Test name
Test status
Simulation time 580922362 ps
CPU time 4.61 seconds
Started May 05 01:14:36 PM PDT 24
Finished May 05 01:14:40 PM PDT 24
Peak memory 203788 kb
Host smart-14e42019-08ca-425e-9b5d-f7ba8d9cddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484363499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2484363499
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1746366727
Short name T305
Test name
Test status
Simulation time 1083275292 ps
CPU time 17.76 seconds
Started May 05 01:14:35 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 298276 kb
Host smart-67f2add8-5be7-4544-b9f9-5ba1c756f815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746366727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1746366727
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2007370838
Short name T1224
Test name
Test status
Simulation time 70588376 ps
CPU time 0.6 seconds
Started May 05 01:14:08 PM PDT 24
Finished May 05 01:14:09 PM PDT 24
Peak memory 203584 kb
Host smart-91890b4b-751a-478f-bdcf-27d86850e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007370838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2007370838
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2048573505
Short name T588
Test name
Test status
Simulation time 2938003754 ps
CPU time 119.07 seconds
Started May 05 01:14:23 PM PDT 24
Finished May 05 01:16:23 PM PDT 24
Peak memory 204124 kb
Host smart-b6ce6000-cdf3-46aa-9df4-b0720e6266b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048573505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2048573505
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.375076566
Short name T642
Test name
Test status
Simulation time 6551030303 ps
CPU time 32.74 seconds
Started May 05 01:14:09 PM PDT 24
Finished May 05 01:14:42 PM PDT 24
Peak memory 462852 kb
Host smart-8490b14e-a2f7-4f97-9d6f-8337f6640430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375076566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.375076566
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.726836754
Short name T1240
Test name
Test status
Simulation time 15393043847 ps
CPU time 629.41 seconds
Started May 05 01:14:32 PM PDT 24
Finished May 05 01:25:02 PM PDT 24
Peak memory 1306076 kb
Host smart-a153c8b2-9a32-480c-b295-9a1545cc75dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726836754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.726836754
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3411784527
Short name T902
Test name
Test status
Simulation time 1058386779 ps
CPU time 10.51 seconds
Started May 05 01:14:32 PM PDT 24
Finished May 05 01:14:43 PM PDT 24
Peak memory 216148 kb
Host smart-41b548a3-ba76-48e0-b522-768d2cc86fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411784527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3411784527
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.205756466
Short name T1187
Test name
Test status
Simulation time 958431119 ps
CPU time 4.57 seconds
Started May 05 01:14:33 PM PDT 24
Finished May 05 01:14:38 PM PDT 24
Peak memory 212932 kb
Host smart-f0e9b3ae-152f-4377-8158-f5bbe3d88dbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205756466 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.205756466
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2627918042
Short name T944
Test name
Test status
Simulation time 10115960168 ps
CPU time 85.35 seconds
Started May 05 01:14:33 PM PDT 24
Finished May 05 01:15:59 PM PDT 24
Peak memory 440436 kb
Host smart-3efbed8f-e2c3-4503-aa68-8a3516c679d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627918042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2627918042
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3886747948
Short name T509
Test name
Test status
Simulation time 10185162695 ps
CPU time 15.42 seconds
Started May 05 01:14:33 PM PDT 24
Finished May 05 01:14:49 PM PDT 24
Peak memory 275380 kb
Host smart-a93c63b5-e10e-40ce-8847-4cfaa888b515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886747948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3886747948
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2537278933
Short name T701
Test name
Test status
Simulation time 354811154 ps
CPU time 2.38 seconds
Started May 05 01:14:35 PM PDT 24
Finished May 05 01:14:38 PM PDT 24
Peak memory 203868 kb
Host smart-0aa882c6-5787-4ead-bc76-b563b2acf421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537278933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2537278933
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1159707596
Short name T1025
Test name
Test status
Simulation time 5360314533 ps
CPU time 6.46 seconds
Started May 05 01:14:26 PM PDT 24
Finished May 05 01:14:33 PM PDT 24
Peak memory 218504 kb
Host smart-52ad5cdc-4969-4ed8-bd6b-08fbf4fa4b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159707596 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1159707596
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3680283402
Short name T1288
Test name
Test status
Simulation time 16882382426 ps
CPU time 70.41 seconds
Started May 05 01:14:37 PM PDT 24
Finished May 05 01:15:48 PM PDT 24
Peak memory 1195376 kb
Host smart-9b617729-a9b4-4948-a346-91a753dfe99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680283402 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3680283402
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1739280512
Short name T1318
Test name
Test status
Simulation time 18975563972 ps
CPU time 15.52 seconds
Started May 05 01:14:38 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 203936 kb
Host smart-9fb3314e-84d7-4c15-857e-4a1c1a01fbff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739280512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1739280512
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2446752911
Short name T1130
Test name
Test status
Simulation time 227552220 ps
CPU time 4.6 seconds
Started May 05 01:14:30 PM PDT 24
Finished May 05 01:14:35 PM PDT 24
Peak memory 203832 kb
Host smart-c10cb3ab-cae8-4064-a935-ea0231f146d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446752911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2446752911
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1833505106
Short name T875
Test name
Test status
Simulation time 7740710432 ps
CPU time 5.1 seconds
Started May 05 01:14:34 PM PDT 24
Finished May 05 01:14:39 PM PDT 24
Peak memory 203832 kb
Host smart-e6bc1c92-9ee8-413f-bb1e-37cdb46c02e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833505106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1833505106
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.820499759
Short name T1041
Test name
Test status
Simulation time 17688900803 ps
CPU time 1162.61 seconds
Started May 05 01:14:30 PM PDT 24
Finished May 05 01:33:54 PM PDT 24
Peak memory 4247172 kb
Host smart-da7a87fa-35e1-4892-83ec-7e20755cf3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820499759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.820499759
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.320484876
Short name T1125
Test name
Test status
Simulation time 5456349857 ps
CPU time 6.69 seconds
Started May 05 01:14:32 PM PDT 24
Finished May 05 01:14:39 PM PDT 24
Peak memory 212144 kb
Host smart-be397d35-5ce7-4722-82c5-ac8409ad4bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320484876 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.320484876
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.1282786902
Short name T848
Test name
Test status
Simulation time 638330615 ps
CPU time 3.85 seconds
Started May 05 01:14:31 PM PDT 24
Finished May 05 01:14:35 PM PDT 24
Peak memory 203752 kb
Host smart-d0a6af14-6db9-496a-9020-c8a6e22b3469
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282786902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.1282786902
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2630879954
Short name T645
Test name
Test status
Simulation time 18834163 ps
CPU time 0.6 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:14:41 PM PDT 24
Peak memory 203728 kb
Host smart-2cec9f3f-afd4-4c5b-a32b-aba92ec81baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630879954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2630879954
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.785183796
Short name T1022
Test name
Test status
Simulation time 164214362 ps
CPU time 1.95 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:14:42 PM PDT 24
Peak memory 215872 kb
Host smart-ef877d41-add2-45f6-83d0-581900a1efd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785183796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.785183796
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.873154814
Short name T300
Test name
Test status
Simulation time 433029721 ps
CPU time 3.98 seconds
Started May 05 01:14:34 PM PDT 24
Finished May 05 01:14:39 PM PDT 24
Peak memory 238552 kb
Host smart-0a03ec00-ac17-47e9-b3fb-ca8e7c246d43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873154814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.873154814
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3740862769
Short name T50
Test name
Test status
Simulation time 2011827958 ps
CPU time 141.22 seconds
Started May 05 01:14:31 PM PDT 24
Finished May 05 01:16:52 PM PDT 24
Peak memory 693964 kb
Host smart-90b8efea-9050-4174-b9f2-769659a1a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740862769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3740862769
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3204706491
Short name T882
Test name
Test status
Simulation time 20737797785 ps
CPU time 53.81 seconds
Started May 05 01:14:31 PM PDT 24
Finished May 05 01:15:25 PM PDT 24
Peak memory 589608 kb
Host smart-9e5eeaf2-946f-4f8f-9aae-c5056f7f0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204706491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3204706491
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1401316244
Short name T775
Test name
Test status
Simulation time 261823446 ps
CPU time 1.15 seconds
Started May 05 01:14:34 PM PDT 24
Finished May 05 01:14:36 PM PDT 24
Peak memory 203832 kb
Host smart-dbe2caa8-4f4a-4cfa-842d-d1812f38733f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401316244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1401316244
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.636205920
Short name T320
Test name
Test status
Simulation time 324869904 ps
CPU time 3.29 seconds
Started May 05 01:14:29 PM PDT 24
Finished May 05 01:14:33 PM PDT 24
Peak memory 203816 kb
Host smart-cbd87cd4-2401-43e9-8bf0-e67075e17bf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636205920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
636205920
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1328767881
Short name T1052
Test name
Test status
Simulation time 6970584403 ps
CPU time 86.31 seconds
Started May 05 01:14:32 PM PDT 24
Finished May 05 01:15:58 PM PDT 24
Peak memory 979612 kb
Host smart-d38dbd6d-3dcd-4e1f-b9d4-bda2e1d4172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328767881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1328767881
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.2710892840
Short name T596
Test name
Test status
Simulation time 1066413675 ps
CPU time 22.07 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:15:07 PM PDT 24
Peak memory 203828 kb
Host smart-39bb0bc2-967a-4ae0-9af0-2ef930792b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710892840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2710892840
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.478300123
Short name T744
Test name
Test status
Simulation time 932579123 ps
CPU time 42.21 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:15:24 PM PDT 24
Peak memory 278332 kb
Host smart-d74bb3e8-b825-4792-b592-294dc0620dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478300123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.478300123
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1124100191
Short name T1160
Test name
Test status
Simulation time 29351455 ps
CPU time 0.67 seconds
Started May 05 01:14:36 PM PDT 24
Finished May 05 01:14:37 PM PDT 24
Peak memory 203876 kb
Host smart-e50a71a5-2bc8-4a7e-948d-d0f85403cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124100191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1124100191
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2999728458
Short name T1330
Test name
Test status
Simulation time 1640788060 ps
CPU time 16.25 seconds
Started May 05 01:14:32 PM PDT 24
Finished May 05 01:14:48 PM PDT 24
Peak memory 212136 kb
Host smart-d97b7899-4b9f-4970-91c6-1f526c509ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999728458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2999728458
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2239568431
Short name T653
Test name
Test status
Simulation time 3950121018 ps
CPU time 30.38 seconds
Started May 05 01:14:38 PM PDT 24
Finished May 05 01:15:09 PM PDT 24
Peak memory 293296 kb
Host smart-d877a82e-d559-4ef6-ba16-a1726862764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239568431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2239568431
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3078403924
Short name T205
Test name
Test status
Simulation time 74954114212 ps
CPU time 2853.72 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 02:02:17 PM PDT 24
Peak memory 1740544 kb
Host smart-8183b6ce-7366-4062-919f-d831e90e5146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078403924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3078403924
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.610797133
Short name T1254
Test name
Test status
Simulation time 8444236078 ps
CPU time 18.62 seconds
Started May 05 01:14:36 PM PDT 24
Finished May 05 01:14:55 PM PDT 24
Peak memory 231300 kb
Host smart-b30ef6c1-c223-4c59-8274-6da73900eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610797133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.610797133
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1882093955
Short name T769
Test name
Test status
Simulation time 4459533097 ps
CPU time 5.36 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:14:46 PM PDT 24
Peak memory 212524 kb
Host smart-782bd6bc-c131-4b81-9c3c-8ade69a9fb4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882093955 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1882093955
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2656392407
Short name T1245
Test name
Test status
Simulation time 10059028647 ps
CPU time 55.48 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:38 PM PDT 24
Peak memory 462752 kb
Host smart-b61d29de-48bf-4d96-98c9-52d06b358555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656392407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2656392407
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1281141752
Short name T386
Test name
Test status
Simulation time 10250612979 ps
CPU time 16.67 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:14:58 PM PDT 24
Peak memory 281264 kb
Host smart-8898a6c6-a148-4189-8e0b-a1505e9dec08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281141752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1281141752
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2467109838
Short name T943
Test name
Test status
Simulation time 994684143 ps
CPU time 5.58 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:48 PM PDT 24
Peak memory 215016 kb
Host smart-16b75f55-c7fd-4728-b3bf-edc4fb0cd15a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467109838 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2467109838
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2298014190
Short name T1251
Test name
Test status
Simulation time 5157299183 ps
CPU time 6.87 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 373596 kb
Host smart-e9b2118b-77d3-4b5f-ac54-e6cedce2791a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298014190 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2298014190
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2494647253
Short name T955
Test name
Test status
Simulation time 2853990515 ps
CPU time 23.91 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:06 PM PDT 24
Peak memory 203888 kb
Host smart-1ecce169-fbc5-403b-9ff8-734e4f117d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494647253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2494647253
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.106543554
Short name T1258
Test name
Test status
Simulation time 34419962883 ps
CPU time 559.99 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:24:01 PM PDT 24
Peak memory 2944132 kb
Host smart-532fe36a-c9ea-410c-8395-af682c0435ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106543554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_stress_all.106543554
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.61791008
Short name T317
Test name
Test status
Simulation time 1744419090 ps
CPU time 32.04 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:15:13 PM PDT 24
Peak memory 225572 kb
Host smart-914e669d-7fc5-41db-9116-90d3984bbed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61791008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stress_rd.61791008
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.385575298
Short name T409
Test name
Test status
Simulation time 51522426171 ps
CPU time 448.26 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:22:09 PM PDT 24
Peak memory 4046256 kb
Host smart-37f44876-c58e-4f35-ac51-1966fe4784ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385575298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.385575298
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.4046668248
Short name T256
Test name
Test status
Simulation time 24184876086 ps
CPU time 1733.7 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:43:37 PM PDT 24
Peak memory 5810920 kb
Host smart-6b2740f3-a739-4d6e-b4cb-ca07c658b301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046668248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.4046668248
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3896382482
Short name T282
Test name
Test status
Simulation time 1152384317 ps
CPU time 6.45 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:49 PM PDT 24
Peak memory 208944 kb
Host smart-9c9303a3-ed94-4175-b855-0cc12cc05a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896382482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3896382482
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.156893047
Short name T1194
Test name
Test status
Simulation time 22001834 ps
CPU time 0.57 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:09:54 PM PDT 24
Peak memory 203672 kb
Host smart-482e174e-dcb7-405d-9086-38879dd83ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156893047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.156893047
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.693246754
Short name T257
Test name
Test status
Simulation time 381641386 ps
CPU time 1.45 seconds
Started May 05 01:09:49 PM PDT 24
Finished May 05 01:09:51 PM PDT 24
Peak memory 215504 kb
Host smart-8ab8213e-b7aa-4049-98fa-111edbc79aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693246754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.693246754
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.601627303
Short name T799
Test name
Test status
Simulation time 1823196016 ps
CPU time 25.57 seconds
Started May 05 01:09:50 PM PDT 24
Finished May 05 01:10:16 PM PDT 24
Peak memory 311152 kb
Host smart-51ad68b6-e394-4dbc-835c-90cf446c635d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601627303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.601627303
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.232895870
Short name T444
Test name
Test status
Simulation time 1859623872 ps
CPU time 133.36 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:12:01 PM PDT 24
Peak memory 647620 kb
Host smart-00b70965-695c-4740-ac1b-bd60860648dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232895870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.232895870
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2079346588
Short name T971
Test name
Test status
Simulation time 290342955 ps
CPU time 1.2 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:09:50 PM PDT 24
Peak memory 203680 kb
Host smart-67c72028-f6b1-426d-80f3-cfd9b3015035
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079346588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2079346588
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2029638076
Short name T1175
Test name
Test status
Simulation time 108340799 ps
CPU time 3.21 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:09:52 PM PDT 24
Peak memory 218628 kb
Host smart-b21ff2f2-6254-4306-b6e1-5d3b68676e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029638076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2029638076
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.704732627
Short name T466
Test name
Test status
Simulation time 2340504401 ps
CPU time 9.1 seconds
Started May 05 01:09:57 PM PDT 24
Finished May 05 01:10:06 PM PDT 24
Peak memory 203960 kb
Host smart-fb5ff2b8-e6c8-410c-8523-af8e252fb997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704732627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.704732627
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.595256952
Short name T733
Test name
Test status
Simulation time 3390566588 ps
CPU time 31.67 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:10:25 PM PDT 24
Peak memory 350900 kb
Host smart-3908992c-48e9-4e1f-afe2-56a8fce72ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595256952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.595256952
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2708441004
Short name T1312
Test name
Test status
Simulation time 56870238 ps
CPU time 0.62 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:09:49 PM PDT 24
Peak memory 203616 kb
Host smart-4aa6f8a1-7bb4-4578-a535-aa5321a90f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708441004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2708441004
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3629114455
Short name T1090
Test name
Test status
Simulation time 26669703175 ps
CPU time 179.12 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:12:48 PM PDT 24
Peak memory 203948 kb
Host smart-3b9a8bec-1002-4c31-b8ba-c9b9ba954996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629114455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3629114455
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3251711221
Short name T335
Test name
Test status
Simulation time 4396679700 ps
CPU time 19.86 seconds
Started May 05 01:09:42 PM PDT 24
Finished May 05 01:10:02 PM PDT 24
Peak memory 299280 kb
Host smart-9dc812bc-8dc7-423e-8fb4-7d5247b034d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251711221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3251711221
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2193334428
Short name T598
Test name
Test status
Simulation time 564809344 ps
CPU time 24.66 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:10:13 PM PDT 24
Peak memory 212096 kb
Host smart-b7ba7d55-cc71-4748-aad8-d7ddf208db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193334428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2193334428
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3049283211
Short name T117
Test name
Test status
Simulation time 114651404 ps
CPU time 0.9 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:09:54 PM PDT 24
Peak memory 222344 kb
Host smart-9ee37b7c-9a8b-4239-add6-753362d9729d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049283211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3049283211
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3693198007
Short name T553
Test name
Test status
Simulation time 7670898290 ps
CPU time 4.9 seconds
Started May 05 01:09:54 PM PDT 24
Finished May 05 01:09:59 PM PDT 24
Peak memory 212136 kb
Host smart-2367a3cd-149c-42b2-9d58-d33dd64956c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693198007 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3693198007
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2232194906
Short name T835
Test name
Test status
Simulation time 10178565453 ps
CPU time 31.37 seconds
Started May 05 01:09:57 PM PDT 24
Finished May 05 01:10:28 PM PDT 24
Peak memory 296976 kb
Host smart-c433e31a-8107-4370-a87b-ba1da3dd3236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232194906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2232194906
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1039332356
Short name T473
Test name
Test status
Simulation time 10143370855 ps
CPU time 79.06 seconds
Started May 05 01:09:55 PM PDT 24
Finished May 05 01:11:15 PM PDT 24
Peak memory 490140 kb
Host smart-f5399380-b7a5-4c55-af9c-47823f42bf59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039332356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1039332356
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.662749380
Short name T976
Test name
Test status
Simulation time 1033242801 ps
CPU time 2.85 seconds
Started May 05 01:09:54 PM PDT 24
Finished May 05 01:09:57 PM PDT 24
Peak memory 203768 kb
Host smart-babadd83-e568-427b-bd36-69e464f17668
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662749380 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.662749380
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.4110624733
Short name T612
Test name
Test status
Simulation time 3463101953 ps
CPU time 5.12 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:09:53 PM PDT 24
Peak memory 208684 kb
Host smart-64504dac-abb4-428c-841b-4c4f4ef4354b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110624733 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.4110624733
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2659459253
Short name T915
Test name
Test status
Simulation time 1353524682 ps
CPU time 2.85 seconds
Started May 05 01:09:51 PM PDT 24
Finished May 05 01:09:54 PM PDT 24
Peak memory 235344 kb
Host smart-6832db86-4dad-40c0-a156-6e829848b9be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659459253 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2659459253
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.637427599
Short name T1117
Test name
Test status
Simulation time 1042747099 ps
CPU time 13.26 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:10:00 PM PDT 24
Peak memory 203760 kb
Host smart-1f23682e-3918-4a27-8de8-9d6cca242d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637427599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.637427599
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1741148332
Short name T610
Test name
Test status
Simulation time 3931280224 ps
CPU time 42.37 seconds
Started May 05 01:09:46 PM PDT 24
Finished May 05 01:10:29 PM PDT 24
Peak memory 203956 kb
Host smart-aad66e39-a29d-4f9c-9f1c-0decedbc96c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741148332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1741148332
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2340544392
Short name T456
Test name
Test status
Simulation time 35038970451 ps
CPU time 57.68 seconds
Started May 05 01:09:48 PM PDT 24
Finished May 05 01:10:47 PM PDT 24
Peak memory 1007988 kb
Host smart-5c7d958f-123a-4bd8-aee5-cfaea0339fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340544392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2340544392
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2594133097
Short name T1215
Test name
Test status
Simulation time 19691608284 ps
CPU time 308.41 seconds
Started May 05 01:09:47 PM PDT 24
Finished May 05 01:14:56 PM PDT 24
Peak memory 1107628 kb
Host smart-e3e9b231-a09e-400b-86a5-9fe6ce53af25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594133097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2594133097
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.4070902231
Short name T1217
Test name
Test status
Simulation time 1108101091 ps
CPU time 6.3 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:10:00 PM PDT 24
Peak memory 214052 kb
Host smart-564a98bc-b80b-4bf0-a694-1818427f9900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070902231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.4070902231
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.44984712
Short name T928
Test name
Test status
Simulation time 744401908 ps
CPU time 4.63 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:09:59 PM PDT 24
Peak memory 203828 kb
Host smart-8f99887e-e891-4f25-9f78-3313a3f998a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44984712 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_unexp_stop.44984712
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2743826391
Short name T832
Test name
Test status
Simulation time 27098689 ps
CPU time 0.62 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:45 PM PDT 24
Peak memory 203720 kb
Host smart-50752671-1902-49b3-8fe0-cdff71fb9c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743826391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2743826391
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.336505351
Short name T284
Test name
Test status
Simulation time 73852973 ps
CPU time 1.57 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:45 PM PDT 24
Peak memory 215572 kb
Host smart-2dcb8d2d-6590-4005-97da-80d93453cb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336505351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.336505351
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.31497542
Short name T78
Test name
Test status
Simulation time 612715203 ps
CPU time 8.81 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:51 PM PDT 24
Peak memory 235404 kb
Host smart-025a2435-9dbb-46d8-874a-04a96ddc8150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty
.31497542
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1255960240
Short name T518
Test name
Test status
Simulation time 1559893905 ps
CPU time 102.81 seconds
Started May 05 01:14:39 PM PDT 24
Finished May 05 01:16:22 PM PDT 24
Peak memory 591604 kb
Host smart-17af13e9-8801-4da6-9c72-f580ff6ede66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255960240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1255960240
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1653899206
Short name T879
Test name
Test status
Simulation time 1803792699 ps
CPU time 52.26 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 582376 kb
Host smart-e16be3de-9f5e-45c7-9477-2d57d37bdc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653899206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1653899206
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.292794914
Short name T657
Test name
Test status
Simulation time 462118162 ps
CPU time 1.06 seconds
Started May 05 01:14:40 PM PDT 24
Finished May 05 01:14:42 PM PDT 24
Peak memory 203832 kb
Host smart-0cf19e0d-efb8-4c3e-a323-a7db7b4c9b86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292794914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.292794914
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1355710877
Short name T556
Test name
Test status
Simulation time 285541405 ps
CPU time 3.93 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:14:48 PM PDT 24
Peak memory 225812 kb
Host smart-597f2f40-4165-4519-bbd1-9e8139bcce74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355710877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1355710877
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1647791301
Short name T1059
Test name
Test status
Simulation time 15253102407 ps
CPU time 262.85 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:19:08 PM PDT 24
Peak memory 1116012 kb
Host smart-1f0b433e-6419-4661-bf2e-8eb9f2390b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647791301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1647791301
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3080350234
Short name T1099
Test name
Test status
Simulation time 436944864 ps
CPU time 5.35 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 203916 kb
Host smart-a823b465-1c2e-477b-8e4d-1bea830c8be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080350234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3080350234
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1576347443
Short name T1169
Test name
Test status
Simulation time 1109247189 ps
CPU time 22.86 seconds
Started May 05 01:14:29 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 341028 kb
Host smart-44159a86-1feb-4e62-8172-0aff212ced08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576347443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1576347443
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3283443931
Short name T1134
Test name
Test status
Simulation time 41038798 ps
CPU time 0.69 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:43 PM PDT 24
Peak memory 203668 kb
Host smart-cc9824bd-03ab-4e8d-a0c7-20779c45795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283443931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3283443931
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.618786025
Short name T1235
Test name
Test status
Simulation time 47922961192 ps
CPU time 1689.05 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:42:52 PM PDT 24
Peak memory 203916 kb
Host smart-3883e2d5-da4e-4980-bfb5-df59f70c8eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618786025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.618786025
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1686573331
Short name T718
Test name
Test status
Simulation time 985814524 ps
CPU time 45.99 seconds
Started May 05 01:14:39 PM PDT 24
Finished May 05 01:15:26 PM PDT 24
Peak memory 297628 kb
Host smart-8002f976-1961-445c-82b5-d1de50815d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686573331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1686573331
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2596829267
Short name T1161
Test name
Test status
Simulation time 1115759244 ps
CPU time 25.28 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:08 PM PDT 24
Peak memory 212092 kb
Host smart-0d580537-a6cf-4ae3-a4bb-82560d3974fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596829267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2596829267
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3500878255
Short name T1035
Test name
Test status
Simulation time 4684361041 ps
CPU time 3.83 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:14:49 PM PDT 24
Peak memory 203952 kb
Host smart-845e6fae-dab0-47b1-89db-dc7b44e584b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500878255 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3500878255
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2284537620
Short name T411
Test name
Test status
Simulation time 10743937682 ps
CPU time 6.84 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:14:52 PM PDT 24
Peak memory 230056 kb
Host smart-5477bc1d-64fc-4a78-97d8-4b655c233619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284537620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2284537620
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.723469951
Short name T905
Test name
Test status
Simulation time 10065815550 ps
CPU time 92.71 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:16:18 PM PDT 24
Peak memory 591212 kb
Host smart-6d2a6a99-ec00-498c-a360-b82e143c5f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723469951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.723469951
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.144136532
Short name T273
Test name
Test status
Simulation time 551684446 ps
CPU time 2.88 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:14:46 PM PDT 24
Peak memory 203808 kb
Host smart-c6293231-4f38-4a7b-a3b6-29eb36795d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144136532 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.144136532
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.898857193
Short name T1211
Test name
Test status
Simulation time 1089528540 ps
CPU time 5.33 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 205600 kb
Host smart-e34c3e67-a30d-45cf-83d4-f04344b2c6bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898857193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.898857193
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2664885558
Short name T477
Test name
Test status
Simulation time 29539932852 ps
CPU time 268.32 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:19:13 PM PDT 24
Peak memory 3529476 kb
Host smart-e8672dca-f2ab-4be3-adc8-415f0afc23df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664885558 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2664885558
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1662789907
Short name T395
Test name
Test status
Simulation time 4101294396 ps
CPU time 46.93 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:29 PM PDT 24
Peak memory 203896 kb
Host smart-27f6ecb0-052a-40e5-a943-a922e78b1381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662789907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1662789907
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.714015947
Short name T1118
Test name
Test status
Simulation time 1514699104 ps
CPU time 22.78 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:06 PM PDT 24
Peak memory 228448 kb
Host smart-2a9e8a86-9165-407d-b08a-ba7fe26f5020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714015947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.714015947
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1367940608
Short name T618
Test name
Test status
Simulation time 29264433012 ps
CPU time 29.08 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:15:11 PM PDT 24
Peak memory 652772 kb
Host smart-e0e9cad2-c8d4-45c3-a76a-7b7c0281b82f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367940608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1367940608
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1537784156
Short name T951
Test name
Test status
Simulation time 11942630517 ps
CPU time 386.41 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:21:11 PM PDT 24
Peak memory 1302448 kb
Host smart-ca4397e3-2969-4fd5-944c-33de4ec63c63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537784156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1537784156
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.394576799
Short name T1313
Test name
Test status
Simulation time 6562445552 ps
CPU time 7.45 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 214812 kb
Host smart-215e386e-d443-4810-9bfa-c11610f78bc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394576799 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.394576799
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2056322819
Short name T833
Test name
Test status
Simulation time 25047887 ps
CPU time 0.62 seconds
Started May 05 01:14:51 PM PDT 24
Finished May 05 01:14:52 PM PDT 24
Peak memory 203664 kb
Host smart-a175ab1e-a95f-4a60-a933-28ff51e1051b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056322819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2056322819
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2105949585
Short name T652
Test name
Test status
Simulation time 1468580266 ps
CPU time 7.14 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 272740 kb
Host smart-30f2888e-51e8-4cf6-9c01-8c2dc3f0c9c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105949585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2105949585
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.4036628088
Short name T1115
Test name
Test status
Simulation time 2751396083 ps
CPU time 40.69 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:15:25 PM PDT 24
Peak memory 485964 kb
Host smart-cf7b615d-5e4c-4b88-baf6-ebbd5bc107b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036628088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.4036628088
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3932772368
Short name T680
Test name
Test status
Simulation time 14079055546 ps
CPU time 134.07 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:16:57 PM PDT 24
Peak memory 598252 kb
Host smart-ecd4022f-ebd5-4d3b-8e12-55ac30ffce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932772368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3932772368
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3338055740
Short name T1021
Test name
Test status
Simulation time 127571290 ps
CPU time 0.9 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:14:47 PM PDT 24
Peak memory 203680 kb
Host smart-f6a25f4d-553c-47f0-88ca-53dccd5d4356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338055740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3338055740
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.936989703
Short name T664
Test name
Test status
Simulation time 346520484 ps
CPU time 10.25 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 238940 kb
Host smart-e15c1ac6-a99c-4c90-9a93-6e383cc5e8fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936989703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
936989703
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.962479426
Short name T236
Test name
Test status
Simulation time 8374367466 ps
CPU time 305.56 seconds
Started May 05 01:14:47 PM PDT 24
Finished May 05 01:19:54 PM PDT 24
Peak memory 1177892 kb
Host smart-61ae256a-63f0-4789-9626-dfe5e04ea174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962479426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.962479426
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.1580878603
Short name T847
Test name
Test status
Simulation time 1023893078 ps
CPU time 4.71 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:14:51 PM PDT 24
Peak memory 203836 kb
Host smart-46aa3631-e37a-4485-a5f4-ae453bf5182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580878603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1580878603
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3755004355
Short name T763
Test name
Test status
Simulation time 1536101338 ps
CPU time 82.7 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:16:06 PM PDT 24
Peak memory 397576 kb
Host smart-a8a0e114-0a83-4f61-9834-68129c0fd9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755004355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3755004355
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1563332142
Short name T195
Test name
Test status
Simulation time 137758033 ps
CPU time 0.64 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:46 PM PDT 24
Peak memory 203572 kb
Host smart-df49768f-6a22-42e8-862e-3d66c5d77e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563332142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1563332142
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1588844422
Short name T445
Test name
Test status
Simulation time 24753614120 ps
CPU time 984.91 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:31:10 PM PDT 24
Peak memory 371192 kb
Host smart-fad0f919-be33-48f4-9b54-308064a18485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588844422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1588844422
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.4039243166
Short name T1242
Test name
Test status
Simulation time 21295639450 ps
CPU time 30.49 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:15:15 PM PDT 24
Peak memory 361368 kb
Host smart-98881a56-c3ec-431f-988d-3afb39692a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039243166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.4039243166
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1974852136
Short name T174
Test name
Test status
Simulation time 12726091008 ps
CPU time 700.33 seconds
Started May 05 01:14:41 PM PDT 24
Finished May 05 01:26:22 PM PDT 24
Peak memory 2975128 kb
Host smart-0a166366-90d3-47e7-8474-a12c11ba5126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974852136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1974852136
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3306798269
Short name T1088
Test name
Test status
Simulation time 525187844 ps
CPU time 8.08 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 217440 kb
Host smart-5f2490ad-f1a0-4fb9-8db1-fcb162fcecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306798269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3306798269
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.139605024
Short name T452
Test name
Test status
Simulation time 596994882 ps
CPU time 3.16 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 203748 kb
Host smart-e2a7dfa4-4459-4560-a26c-b47292c15946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139605024 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.139605024
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.856113657
Short name T392
Test name
Test status
Simulation time 10150248077 ps
CPU time 15.12 seconds
Started May 05 01:14:47 PM PDT 24
Finished May 05 01:15:03 PM PDT 24
Peak memory 271252 kb
Host smart-ed3df8c7-7935-4c12-8f8e-c0c6ed22fc2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856113657 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.856113657
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2833721613
Short name T58
Test name
Test status
Simulation time 10146309743 ps
CPU time 29.17 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:15:13 PM PDT 24
Peak memory 357212 kb
Host smart-68297186-fd43-4709-b91d-2a34eb6bdbdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833721613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2833721613
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.647333560
Short name T1127
Test name
Test status
Simulation time 654128259 ps
CPU time 2.26 seconds
Started May 05 01:14:48 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 203736 kb
Host smart-633f9ae8-c136-40f1-aecd-829d2c219fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647333560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.647333560
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.760704056
Short name T423
Test name
Test status
Simulation time 5295403092 ps
CPU time 6.98 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 219896 kb
Host smart-3dd19ff9-432b-4c91-afe4-39eeedca7774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760704056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.760704056
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.688062324
Short name T628
Test name
Test status
Simulation time 5558245097 ps
CPU time 4.94 seconds
Started May 05 01:14:44 PM PDT 24
Finished May 05 01:14:50 PM PDT 24
Peak memory 203832 kb
Host smart-1bfa220d-2cc5-46f2-8b86-a62d4f46b2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688062324 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.688062324
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3480657688
Short name T846
Test name
Test status
Simulation time 1053200641 ps
CPU time 18.58 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:15:01 PM PDT 24
Peak memory 203764 kb
Host smart-4524ec35-0e29-4e15-971e-c697c436262f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480657688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3480657688
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3442791542
Short name T383
Test name
Test status
Simulation time 1639851630 ps
CPU time 55.68 seconds
Started May 05 01:14:47 PM PDT 24
Finished May 05 01:15:43 PM PDT 24
Peak memory 203972 kb
Host smart-0f4534a9-d557-47f3-b188-e1fd9aaea22b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442791542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3442791542
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3995191595
Short name T17
Test name
Test status
Simulation time 52664237997 ps
CPU time 1359.3 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:37:26 PM PDT 24
Peak memory 8303948 kb
Host smart-c015133e-ec83-439b-abd8-8af4f8bb0aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995191595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3995191595
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1376616010
Short name T1305
Test name
Test status
Simulation time 34362657569 ps
CPU time 2709.26 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:59:55 PM PDT 24
Peak memory 8115196 kb
Host smart-183a7b70-08ce-489f-b8ca-b6374de6030b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376616010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1376616010
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.418042283
Short name T1140
Test name
Test status
Simulation time 6143087726 ps
CPU time 7.41 seconds
Started May 05 01:14:48 PM PDT 24
Finished May 05 01:14:56 PM PDT 24
Peak memory 220076 kb
Host smart-900d4499-c8b4-497a-8882-d1b6a8afc18c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418042283 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.418042283
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3194403116
Short name T1144
Test name
Test status
Simulation time 14218002 ps
CPU time 0.61 seconds
Started May 05 01:14:54 PM PDT 24
Finished May 05 01:14:55 PM PDT 24
Peak memory 203724 kb
Host smart-edbce563-7d32-4b32-b2e0-89acca805c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194403116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3194403116
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2459072339
Short name T822
Test name
Test status
Simulation time 88872346 ps
CPU time 1.52 seconds
Started May 05 01:14:51 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 212056 kb
Host smart-0cabd1b0-c0df-4ad7-a8c2-8c992756d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459072339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2459072339
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4249310833
Short name T1057
Test name
Test status
Simulation time 414615907 ps
CPU time 22.6 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:15:09 PM PDT 24
Peak memory 294204 kb
Host smart-fe8ad930-02e7-4776-8d5f-775373632031
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249310833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4249310833
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2158967722
Short name T230
Test name
Test status
Simulation time 9389169040 ps
CPU time 59.39 seconds
Started May 05 01:14:43 PM PDT 24
Finished May 05 01:15:43 PM PDT 24
Peak memory 491332 kb
Host smart-38b101e0-0048-40c9-ae0c-13a2e357d994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158967722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2158967722
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.583032738
Short name T1069
Test name
Test status
Simulation time 1050077219 ps
CPU time 65.23 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:15:55 PM PDT 24
Peak memory 429608 kb
Host smart-74567ba9-196f-49ea-9901-383344990694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583032738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.583032738
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.689361623
Short name T1338
Test name
Test status
Simulation time 556802893 ps
CPU time 0.89 seconds
Started May 05 01:14:42 PM PDT 24
Finished May 05 01:14:44 PM PDT 24
Peak memory 203724 kb
Host smart-bed6a918-5a9f-4a65-b088-0241a66b3f61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689361623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.689361623
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2869148971
Short name T651
Test name
Test status
Simulation time 726484532 ps
CPU time 10.01 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:14:59 PM PDT 24
Peak memory 237364 kb
Host smart-2bc576f0-178f-4d8d-8793-b0684614115f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869148971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2869148971
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3369798742
Short name T183
Test name
Test status
Simulation time 26901234122 ps
CPU time 63.5 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:15:53 PM PDT 24
Peak memory 803880 kb
Host smart-5440c55e-1131-462b-80f7-5a3ffb45bca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369798742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3369798742
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2885873887
Short name T620
Test name
Test status
Simulation time 2158248375 ps
CPU time 7.76 seconds
Started May 05 01:14:56 PM PDT 24
Finished May 05 01:15:04 PM PDT 24
Peak memory 203980 kb
Host smart-5d357f70-492d-4275-88ea-8c0840565eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885873887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2885873887
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_override.3837445917
Short name T968
Test name
Test status
Simulation time 26197554 ps
CPU time 0.72 seconds
Started May 05 01:14:51 PM PDT 24
Finished May 05 01:14:52 PM PDT 24
Peak memory 203664 kb
Host smart-6ec201cf-2f6c-4589-b5e6-bac14199d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837445917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3837445917
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.513496902
Short name T1087
Test name
Test status
Simulation time 7110770501 ps
CPU time 296.62 seconds
Started May 05 01:14:51 PM PDT 24
Finished May 05 01:19:48 PM PDT 24
Peak memory 254120 kb
Host smart-2677b97d-e619-49f8-a277-60a1de6d5556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513496902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.513496902
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2085978419
Short name T455
Test name
Test status
Simulation time 1228890758 ps
CPU time 58.8 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:15:45 PM PDT 24
Peak memory 325464 kb
Host smart-903e269e-0410-40bb-aaac-45b55ac8229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085978419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2085978419
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2811210626
Short name T1085
Test name
Test status
Simulation time 26067455284 ps
CPU time 414.47 seconds
Started May 05 01:14:45 PM PDT 24
Finished May 05 01:21:40 PM PDT 24
Peak memory 1411404 kb
Host smart-a692e5a3-039e-4b3d-9731-378b3bca75c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811210626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2811210626
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1996769002
Short name T914
Test name
Test status
Simulation time 2360019681 ps
CPU time 8.91 seconds
Started May 05 01:14:48 PM PDT 24
Finished May 05 01:14:58 PM PDT 24
Peak memory 220212 kb
Host smart-2eca33fa-b9c8-4315-a94a-d523f8baf570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996769002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1996769002
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2030137123
Short name T837
Test name
Test status
Simulation time 2825424217 ps
CPU time 4.26 seconds
Started May 05 01:14:47 PM PDT 24
Finished May 05 01:14:52 PM PDT 24
Peak memory 212116 kb
Host smart-d36e292c-449c-4050-aadb-7eacf3b05cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030137123 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2030137123
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.907908950
Short name T690
Test name
Test status
Simulation time 10134283668 ps
CPU time 29.04 seconds
Started May 05 01:14:50 PM PDT 24
Finished May 05 01:15:19 PM PDT 24
Peak memory 325476 kb
Host smart-6b001a02-1c87-4ca0-8ff9-e1cd596c3bc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907908950 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.907908950
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1063067925
Short name T856
Test name
Test status
Simulation time 10356334563 ps
CPU time 19.25 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:15:08 PM PDT 24
Peak memory 276716 kb
Host smart-b5ad8d4f-26f4-4547-a325-c51d60542ae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063067925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1063067925
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2115630402
Short name T534
Test name
Test status
Simulation time 1952746377 ps
CPU time 2.91 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:14:53 PM PDT 24
Peak memory 203836 kb
Host smart-52068e78-1754-43fb-b365-7646c1e476b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115630402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2115630402
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1311379765
Short name T1053
Test name
Test status
Simulation time 758943260 ps
CPU time 4.26 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:14:54 PM PDT 24
Peak memory 203844 kb
Host smart-61f733e8-cf1c-42fc-ad1f-0f456b363a01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311379765 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1311379765
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.287261151
Short name T712
Test name
Test status
Simulation time 18705300309 ps
CPU time 40.47 seconds
Started May 05 01:14:50 PM PDT 24
Finished May 05 01:15:31 PM PDT 24
Peak memory 774532 kb
Host smart-6d122986-85e0-481e-a67d-78ab3ff93e9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287261151 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.287261151
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2645480280
Short name T1222
Test name
Test status
Simulation time 851825754 ps
CPU time 14.01 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:15:03 PM PDT 24
Peak memory 203820 kb
Host smart-35a1f8b8-7416-4976-952c-eecc53639efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645480280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2645480280
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3213502489
Short name T925
Test name
Test status
Simulation time 4460253410 ps
CPU time 15.04 seconds
Started May 05 01:14:51 PM PDT 24
Finished May 05 01:15:07 PM PDT 24
Peak memory 212108 kb
Host smart-beaac8cd-cb35-4c79-adae-b23cf8c0a14a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213502489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3213502489
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3716229593
Short name T672
Test name
Test status
Simulation time 53641997063 ps
CPU time 106.55 seconds
Started May 05 01:14:49 PM PDT 24
Finished May 05 01:16:37 PM PDT 24
Peak memory 1537648 kb
Host smart-8cae5c75-20a4-439d-b291-68074197417d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716229593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3716229593
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1851713255
Short name T949
Test name
Test status
Simulation time 21993183222 ps
CPU time 1269.51 seconds
Started May 05 01:14:46 PM PDT 24
Finished May 05 01:35:57 PM PDT 24
Peak memory 4715784 kb
Host smart-6f3d3999-7d3e-420b-abf7-e79f525c88c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851713255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1851713255
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1030623740
Short name T1042
Test name
Test status
Simulation time 3471108230 ps
CPU time 7.34 seconds
Started May 05 01:14:48 PM PDT 24
Finished May 05 01:14:56 PM PDT 24
Peak memory 212156 kb
Host smart-4c9e4b78-2ea8-4d7f-8471-3a1e7aff7060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030623740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1030623740
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2912285252
Short name T484
Test name
Test status
Simulation time 17550954 ps
CPU time 0.62 seconds
Started May 05 01:15:09 PM PDT 24
Finished May 05 01:15:10 PM PDT 24
Peak memory 203716 kb
Host smart-caa956aa-ede7-4159-b689-52d64d788a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912285252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2912285252
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2346579109
Short name T726
Test name
Test status
Simulation time 89768080 ps
CPU time 1.75 seconds
Started May 05 01:15:07 PM PDT 24
Finished May 05 01:15:09 PM PDT 24
Peak memory 212164 kb
Host smart-b265796c-164d-4e9d-b3f6-21e601ef473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346579109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2346579109
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2472485337
Short name T1155
Test name
Test status
Simulation time 1828173008 ps
CPU time 11.62 seconds
Started May 05 01:14:59 PM PDT 24
Finished May 05 01:15:11 PM PDT 24
Peak memory 317876 kb
Host smart-c19d8aa9-8f93-445e-8b3a-96701768acaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472485337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2472485337
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2565416918
Short name T797
Test name
Test status
Simulation time 11937978957 ps
CPU time 53.98 seconds
Started May 05 01:15:06 PM PDT 24
Finished May 05 01:16:01 PM PDT 24
Peak memory 628080 kb
Host smart-a0f81b5b-af08-411e-8566-5259e1319cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565416918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2565416918
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3617963976
Short name T746
Test name
Test status
Simulation time 9393261538 ps
CPU time 77.86 seconds
Started May 05 01:14:57 PM PDT 24
Finished May 05 01:16:15 PM PDT 24
Peak memory 741920 kb
Host smart-5c47572d-a025-4250-afcb-bdbf77ee3ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617963976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3617963976
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1957051033
Short name T210
Test name
Test status
Simulation time 137997563 ps
CPU time 1.05 seconds
Started May 05 01:14:57 PM PDT 24
Finished May 05 01:14:59 PM PDT 24
Peak memory 203828 kb
Host smart-99a82583-3199-4fb4-bec8-fbde388e3b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957051033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1957051033
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1440132601
Short name T1209
Test name
Test status
Simulation time 816023836 ps
CPU time 6.08 seconds
Started May 05 01:15:00 PM PDT 24
Finished May 05 01:15:07 PM PDT 24
Peak memory 203832 kb
Host smart-53672c90-9f7e-46ca-bcee-4e75105838cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440132601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1440132601
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2454453604
Short name T186
Test name
Test status
Simulation time 5397243666 ps
CPU time 58.63 seconds
Started May 05 01:15:00 PM PDT 24
Finished May 05 01:15:59 PM PDT 24
Peak memory 846664 kb
Host smart-aee2301d-eb9d-4ac1-8edc-5c64dfd63d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454453604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2454453604
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2616478558
Short name T1145
Test name
Test status
Simulation time 299645707 ps
CPU time 12.37 seconds
Started May 05 01:15:10 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 203832 kb
Host smart-e32b957c-a398-445a-bec1-4b2a39f70f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616478558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2616478558
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.792032933
Short name T259
Test name
Test status
Simulation time 916827715 ps
CPU time 40.53 seconds
Started May 05 01:15:10 PM PDT 24
Finished May 05 01:15:51 PM PDT 24
Peak memory 280672 kb
Host smart-467b82e4-7cc6-4ab6-96a6-3f2b232c2597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792032933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.792032933
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.4050906867
Short name T739
Test name
Test status
Simulation time 102772818 ps
CPU time 0.67 seconds
Started May 05 01:15:00 PM PDT 24
Finished May 05 01:15:01 PM PDT 24
Peak memory 203652 kb
Host smart-b69e4cfc-a9b2-4ca5-b11e-2a3f48124543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050906867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4050906867
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3659654847
Short name T465
Test name
Test status
Simulation time 186388001 ps
CPU time 2.57 seconds
Started May 05 01:15:05 PM PDT 24
Finished May 05 01:15:08 PM PDT 24
Peak memory 227172 kb
Host smart-fd6cb9fe-2c76-496e-82cd-bf34121e9bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659654847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3659654847
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2111976729
Short name T251
Test name
Test status
Simulation time 5630844491 ps
CPU time 22.42 seconds
Started May 05 01:14:57 PM PDT 24
Finished May 05 01:15:20 PM PDT 24
Peak memory 335292 kb
Host smart-cb99ea9f-7a3d-4c4f-9f43-f7aeddefff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111976729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2111976729
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2787393555
Short name T281
Test name
Test status
Simulation time 364049919 ps
CPU time 16.99 seconds
Started May 05 01:15:05 PM PDT 24
Finished May 05 01:15:22 PM PDT 24
Peak memory 212036 kb
Host smart-b1653389-2697-4f22-b4bf-c72f50b10682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787393555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2787393555
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.623421646
Short name T979
Test name
Test status
Simulation time 2868214284 ps
CPU time 3.57 seconds
Started May 05 01:15:09 PM PDT 24
Finished May 05 01:15:13 PM PDT 24
Peak memory 212144 kb
Host smart-c94b06e2-57c2-40de-89f8-0803f8dffa94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623421646 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.623421646
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3257137566
Short name T1073
Test name
Test status
Simulation time 10063912148 ps
CPU time 28.28 seconds
Started May 05 01:15:08 PM PDT 24
Finished May 05 01:15:37 PM PDT 24
Peak memory 314232 kb
Host smart-2e41a64d-bae8-4ce0-97f3-14b44b80b885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257137566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3257137566
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3711924072
Short name T894
Test name
Test status
Simulation time 10079905331 ps
CPU time 32.5 seconds
Started May 05 01:15:09 PM PDT 24
Finished May 05 01:15:42 PM PDT 24
Peak memory 381244 kb
Host smart-855d62bb-af94-49e1-8c77-62976e5d79b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711924072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3711924072
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2073390963
Short name T1129
Test name
Test status
Simulation time 2046826583 ps
CPU time 3.18 seconds
Started May 05 01:15:09 PM PDT 24
Finished May 05 01:15:13 PM PDT 24
Peak memory 203808 kb
Host smart-08c6b83a-75d3-4ec9-bb4f-86eee97bd405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073390963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2073390963
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3884647870
Short name T1229
Test name
Test status
Simulation time 851814773 ps
CPU time 4.71 seconds
Started May 05 01:15:04 PM PDT 24
Finished May 05 01:15:10 PM PDT 24
Peak memory 204720 kb
Host smart-fb1563ad-baf1-4a9e-ae6b-e2d055951479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884647870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3884647870
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1639309464
Short name T1014
Test name
Test status
Simulation time 9360434822 ps
CPU time 135.9 seconds
Started May 05 01:15:04 PM PDT 24
Finished May 05 01:17:20 PM PDT 24
Peak memory 2318532 kb
Host smart-dfab3772-f01f-4aff-b473-3d28306b2477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639309464 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1639309464
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1087686651
Short name T29
Test name
Test status
Simulation time 946606804 ps
CPU time 38 seconds
Started May 05 01:15:08 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 203824 kb
Host smart-623ce381-ac3e-47f3-854c-4cfbd0475159
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087686651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1087686651
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2101030895
Short name T1335
Test name
Test status
Simulation time 334516058 ps
CPU time 4.99 seconds
Started May 05 01:15:06 PM PDT 24
Finished May 05 01:15:11 PM PDT 24
Peak memory 205044 kb
Host smart-c53a91e6-5dbd-4ad0-be58-36af31692430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101030895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2101030895
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.4227715921
Short name T487
Test name
Test status
Simulation time 61122219820 ps
CPU time 2000.82 seconds
Started May 05 01:15:06 PM PDT 24
Finished May 05 01:48:27 PM PDT 24
Peak memory 10491460 kb
Host smart-d406be5c-368b-4631-b524-fb53dc3fac57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227715921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.4227715921
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1074238136
Short name T431
Test name
Test status
Simulation time 32216420758 ps
CPU time 2926.73 seconds
Started May 05 01:15:07 PM PDT 24
Finished May 05 02:03:54 PM PDT 24
Peak memory 7719392 kb
Host smart-93f4b1aa-fc81-4e47-a41a-8d03761cc9fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074238136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1074238136
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1568644884
Short name T406
Test name
Test status
Simulation time 1364899738 ps
CPU time 6.83 seconds
Started May 05 01:15:07 PM PDT 24
Finished May 05 01:15:14 PM PDT 24
Peak memory 203788 kb
Host smart-554bb8f3-c374-42ab-85a7-6c03eeb89ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568644884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1568644884
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.4240584745
Short name T394
Test name
Test status
Simulation time 47848640 ps
CPU time 0.63 seconds
Started May 05 01:15:24 PM PDT 24
Finished May 05 01:15:25 PM PDT 24
Peak memory 203740 kb
Host smart-e1648490-1a9f-4210-b16e-833a614117de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240584745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.4240584745
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3562622491
Short name T627
Test name
Test status
Simulation time 685154569 ps
CPU time 1.78 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:18 PM PDT 24
Peak memory 220320 kb
Host smart-7bc74a57-1a7a-4d14-9c6f-22f4bf067a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562622491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3562622491
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.391437281
Short name T1333
Test name
Test status
Simulation time 286941137 ps
CPU time 5.1 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:21 PM PDT 24
Peak memory 252952 kb
Host smart-0fc24311-3b48-4c0c-8302-a6552d119488
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391437281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.391437281
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.950107101
Short name T84
Test name
Test status
Simulation time 2111697290 ps
CPU time 61.21 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:16:17 PM PDT 24
Peak memory 668776 kb
Host smart-d5b3f3a3-c204-474f-a52f-a7e892ed5c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950107101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.950107101
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2897537565
Short name T702
Test name
Test status
Simulation time 7379017414 ps
CPU time 37.42 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:53 PM PDT 24
Peak memory 496176 kb
Host smart-9cf8dced-2d3a-4df9-b2d0-29a340174338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897537565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2897537565
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3205325556
Short name T1226
Test name
Test status
Simulation time 269797395 ps
CPU time 1.12 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:16 PM PDT 24
Peak memory 203776 kb
Host smart-7f104b3c-9cca-4f79-8891-099199316960
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205325556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3205325556
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.4044186631
Short name T415
Test name
Test status
Simulation time 554220464 ps
CPU time 3.95 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:20 PM PDT 24
Peak memory 229268 kb
Host smart-77d28a03-3424-4a00-85eb-f80b133fdcee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044186631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.4044186631
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1115885336
Short name T344
Test name
Test status
Simulation time 25896152874 ps
CPU time 170.17 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:18:06 PM PDT 24
Peak memory 828828 kb
Host smart-c212b48d-114e-475b-9891-59092c942ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115885336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1115885336
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1345527894
Short name T3
Test name
Test status
Simulation time 974924372 ps
CPU time 9.92 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:33 PM PDT 24
Peak memory 203760 kb
Host smart-610c1ca3-3056-4056-911b-eec386c1a6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345527894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1345527894
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3040678738
Short name T857
Test name
Test status
Simulation time 1675403563 ps
CPU time 26.93 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:49 PM PDT 24
Peak memory 325716 kb
Host smart-2f0e46cc-92d5-4f64-92dd-aad5c601924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040678738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3040678738
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3458088547
Short name T370
Test name
Test status
Simulation time 51502937 ps
CPU time 0.61 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:17 PM PDT 24
Peak memory 203676 kb
Host smart-e5255a8e-0596-480b-9b2c-53a0a2303007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458088547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3458088547
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2919202912
Short name T575
Test name
Test status
Simulation time 32470279209 ps
CPU time 391.31 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:21:47 PM PDT 24
Peak memory 1878296 kb
Host smart-4104bea9-20a5-4e6f-bcf0-8c43bb1d1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919202912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2919202912
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1286562455
Short name T731
Test name
Test status
Simulation time 1096624630 ps
CPU time 50.4 seconds
Started May 05 01:15:16 PM PDT 24
Finished May 05 01:16:07 PM PDT 24
Peak memory 284912 kb
Host smart-3f57e763-029c-4cca-bf85-e27f1fa1472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286562455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1286562455
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.1182488840
Short name T46
Test name
Test status
Simulation time 6844500429 ps
CPU time 205.38 seconds
Started May 05 01:15:14 PM PDT 24
Finished May 05 01:18:40 PM PDT 24
Peak memory 1486708 kb
Host smart-5ff3a38b-71a5-4059-81cc-5894f02c6fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182488840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1182488840
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2224188841
Short name T812
Test name
Test status
Simulation time 2060751400 ps
CPU time 22.99 seconds
Started May 05 01:15:13 PM PDT 24
Finished May 05 01:15:37 PM PDT 24
Peak memory 212096 kb
Host smart-c804d500-c79b-4817-92a8-3e31079c3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224188841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2224188841
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2634728452
Short name T994
Test name
Test status
Simulation time 4049219584 ps
CPU time 5.01 seconds
Started May 05 01:15:24 PM PDT 24
Finished May 05 01:15:29 PM PDT 24
Peak memory 213972 kb
Host smart-3821a053-388b-4fed-9537-7b9f120d8e1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634728452 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2634728452
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.712587216
Short name T903
Test name
Test status
Simulation time 10048531687 ps
CPU time 71.1 seconds
Started May 05 01:15:14 PM PDT 24
Finished May 05 01:16:25 PM PDT 24
Peak memory 418604 kb
Host smart-abf15dcf-5b31-4382-b291-8b9237e18e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712587216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.712587216
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.4247433212
Short name T105
Test name
Test status
Simulation time 10133743702 ps
CPU time 15.09 seconds
Started May 05 01:15:24 PM PDT 24
Finished May 05 01:15:40 PM PDT 24
Peak memory 308936 kb
Host smart-b33d0d0f-6f8b-4e22-a234-3961189279a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247433212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.4247433212
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.954390879
Short name T436
Test name
Test status
Simulation time 438531283 ps
CPU time 2.45 seconds
Started May 05 01:15:20 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 203808 kb
Host smart-7deddc65-b6e2-43aa-a711-66fb1f8facae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954390879 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.954390879
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2850625759
Short name T828
Test name
Test status
Simulation time 959508715 ps
CPU time 4.78 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:21 PM PDT 24
Peak memory 204780 kb
Host smart-889118ab-0da1-43d1-8a1d-563422c85ee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850625759 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2850625759
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.990230628
Short name T889
Test name
Test status
Simulation time 14182093528 ps
CPU time 19.78 seconds
Started May 05 01:15:14 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 486020 kb
Host smart-059dee8b-7793-4c9e-b293-1a18ebb207b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990230628 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.990230628
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2188780870
Short name T1010
Test name
Test status
Simulation time 953413639 ps
CPU time 16.64 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:32 PM PDT 24
Peak memory 203836 kb
Host smart-29897bca-d68a-41d3-9cc2-600ecb514553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188780870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2188780870
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.533778450
Short name T1238
Test name
Test status
Simulation time 286438042 ps
CPU time 5.1 seconds
Started May 05 01:15:17 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 203828 kb
Host smart-5b569497-9a20-4e09-a8ba-8c5460c50717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533778450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.533778450
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3842143366
Short name T307
Test name
Test status
Simulation time 13290480766 ps
CPU time 6.69 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:22 PM PDT 24
Peak memory 203872 kb
Host smart-c0c67841-86b4-4345-a776-2b687cbec864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842143366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3842143366
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1433820351
Short name T578
Test name
Test status
Simulation time 24534666594 ps
CPU time 1456.39 seconds
Started May 05 01:15:14 PM PDT 24
Finished May 05 01:39:31 PM PDT 24
Peak memory 6125372 kb
Host smart-79d72c6e-4e03-4acf-a27c-631bd4387c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433820351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1433820351
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3443959005
Short name T568
Test name
Test status
Simulation time 1170757295 ps
CPU time 6.82 seconds
Started May 05 01:15:15 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 220180 kb
Host smart-7422d9c8-7486-4bf2-a6ef-308728786a37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443959005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3443959005
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.1193451071
Short name T1286
Test name
Test status
Simulation time 2507387956 ps
CPU time 7.08 seconds
Started May 05 01:15:14 PM PDT 24
Finished May 05 01:15:22 PM PDT 24
Peak memory 214424 kb
Host smart-f9ac9455-2ee1-4041-af40-53145d0bbecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193451071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.1193451071
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.4093400706
Short name T629
Test name
Test status
Simulation time 63461556 ps
CPU time 0.59 seconds
Started May 05 01:15:25 PM PDT 24
Finished May 05 01:15:26 PM PDT 24
Peak memory 203704 kb
Host smart-1d1e63aa-1a94-42bd-92e6-cf928e04c46c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093400706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.4093400706
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1947375975
Short name T1291
Test name
Test status
Simulation time 203603308 ps
CPU time 1.66 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:24 PM PDT 24
Peak memory 212164 kb
Host smart-970da717-cf36-4338-95de-141e5c2b9033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947375975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1947375975
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1366219077
Short name T946
Test name
Test status
Simulation time 311535936 ps
CPU time 6.95 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:30 PM PDT 24
Peak memory 267884 kb
Host smart-614769dd-461c-49c5-969f-e0540c2e8a2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366219077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1366219077
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3363940904
Short name T1064
Test name
Test status
Simulation time 1354745086 ps
CPU time 90.48 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:16:53 PM PDT 24
Peak memory 531280 kb
Host smart-dec4d787-ce29-4cca-b3db-ce9e927b1f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363940904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3363940904
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2212844486
Short name T1020
Test name
Test status
Simulation time 1140285447 ps
CPU time 71.22 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:16:34 PM PDT 24
Peak memory 456012 kb
Host smart-f501d532-3eda-411b-b8e4-1b928fb56b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212844486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2212844486
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3824901791
Short name T319
Test name
Test status
Simulation time 90760182 ps
CPU time 0.87 seconds
Started May 05 01:15:20 PM PDT 24
Finished May 05 01:15:21 PM PDT 24
Peak memory 203704 kb
Host smart-e252d815-1a7a-41b3-8d86-2213c0142474
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824901791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3824901791
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3148978995
Short name T993
Test name
Test status
Simulation time 698443596 ps
CPU time 4.15 seconds
Started May 05 01:15:21 PM PDT 24
Finished May 05 01:15:26 PM PDT 24
Peak memory 203848 kb
Host smart-ea6c7a39-5b9a-4a01-bf3b-5ff25d4b2b46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148978995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3148978995
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.126864468
Short name T1199
Test name
Test status
Simulation time 36393074860 ps
CPU time 205.34 seconds
Started May 05 01:15:21 PM PDT 24
Finished May 05 01:18:47 PM PDT 24
Peak memory 904640 kb
Host smart-402578ca-9b97-4386-9ac5-68ab8d1705b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126864468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.126864468
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.741926191
Short name T70
Test name
Test status
Simulation time 287164739 ps
CPU time 3.69 seconds
Started May 05 01:15:25 PM PDT 24
Finished May 05 01:15:30 PM PDT 24
Peak memory 203904 kb
Host smart-dfa08489-ab33-43fd-95b1-b0209dce23a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741926191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.741926191
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.619146504
Short name T443
Test name
Test status
Simulation time 2006524319 ps
CPU time 17.85 seconds
Started May 05 01:15:25 PM PDT 24
Finished May 05 01:15:43 PM PDT 24
Peak memory 261940 kb
Host smart-b36e594c-31b7-46ac-91d7-055eec502613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619146504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.619146504
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2921292979
Short name T203
Test name
Test status
Simulation time 58702182 ps
CPU time 0.61 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:23 PM PDT 24
Peak memory 203572 kb
Host smart-8e1f8afa-bd22-44fc-afb2-c41e8467773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921292979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2921292979
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2017031452
Short name T764
Test name
Test status
Simulation time 17744190446 ps
CPU time 255.2 seconds
Started May 05 01:15:23 PM PDT 24
Finished May 05 01:19:38 PM PDT 24
Peak memory 251784 kb
Host smart-a5dace2f-7385-4411-bfcd-f9a9864006b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017031452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2017031452
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1541559086
Short name T948
Test name
Test status
Simulation time 4453541816 ps
CPU time 23.13 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 291668 kb
Host smart-99d1e852-16fe-43b2-9e6c-90c3c93ab27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541559086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1541559086
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1263248537
Short name T245
Test name
Test status
Simulation time 29955280106 ps
CPU time 1670.79 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:43:18 PM PDT 24
Peak memory 3706160 kb
Host smart-762d0193-7759-4e0e-b5ad-334bcd9d19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263248537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1263248537
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3901982825
Short name T540
Test name
Test status
Simulation time 532637957 ps
CPU time 10.64 seconds
Started May 05 01:15:22 PM PDT 24
Finished May 05 01:15:33 PM PDT 24
Peak memory 216168 kb
Host smart-6a8b66c4-52c3-4be7-a2d2-f3188c7576d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901982825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3901982825
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2925823536
Short name T498
Test name
Test status
Simulation time 1795683458 ps
CPU time 4.31 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:36 PM PDT 24
Peak memory 212036 kb
Host smart-dfb99bfb-017f-4b1f-87aa-7f7e9c9f02bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925823536 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2925823536
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.700314114
Short name T1178
Test name
Test status
Simulation time 10290517249 ps
CPU time 14.28 seconds
Started May 05 01:15:30 PM PDT 24
Finished May 05 01:15:45 PM PDT 24
Peak memory 249544 kb
Host smart-8d3af6a2-61e0-40cb-829b-6fe2cffdb98f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700314114 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.700314114
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1572038349
Short name T723
Test name
Test status
Simulation time 10167145538 ps
CPU time 14.44 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 301388 kb
Host smart-2fcfc9b2-e6eb-49c9-afe2-c92c175ff01d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572038349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1572038349
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3082823679
Short name T552
Test name
Test status
Simulation time 1471672186 ps
CPU time 2.77 seconds
Started May 05 01:15:28 PM PDT 24
Finished May 05 01:15:31 PM PDT 24
Peak memory 203820 kb
Host smart-c9dbb8ea-8045-4e3b-a6e2-01b3a8b6230c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082823679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3082823679
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1245437900
Short name T313
Test name
Test status
Simulation time 896450323 ps
CPU time 4.59 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:15:31 PM PDT 24
Peak memory 203812 kb
Host smart-2355793b-a0e4-478a-86be-f34fb952288c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245437900 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1245437900
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.273105348
Short name T348
Test name
Test status
Simulation time 2729923397 ps
CPU time 5.35 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:37 PM PDT 24
Peak memory 203880 kb
Host smart-78dbe63c-1ba8-4615-8f7d-97990819254a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273105348 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.273105348
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3170895988
Short name T108
Test name
Test status
Simulation time 6222655109 ps
CPU time 33.36 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:16:00 PM PDT 24
Peak memory 203884 kb
Host smart-7f612911-8fc9-4d96-9ee6-82d84b782ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170895988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3170895988
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.258200155
Short name T435
Test name
Test status
Simulation time 2099807339 ps
CPU time 20.52 seconds
Started May 05 01:15:29 PM PDT 24
Finished May 05 01:15:50 PM PDT 24
Peak memory 219776 kb
Host smart-687cf904-9c85-4d5d-8d05-e33d1a2896b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258200155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.258200155
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1466852576
Short name T844
Test name
Test status
Simulation time 45195843033 ps
CPU time 377.74 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:21:44 PM PDT 24
Peak memory 3812252 kb
Host smart-189312d4-d964-448a-a598-9013a581e616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466852576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1466852576
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2347786797
Short name T972
Test name
Test status
Simulation time 5540479476 ps
CPU time 69.7 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:16:37 PM PDT 24
Peak memory 494476 kb
Host smart-26b1e9d3-d50b-4742-a4ca-919789d2814a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347786797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2347786797
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1885427882
Short name T315
Test name
Test status
Simulation time 4610018060 ps
CPU time 6.52 seconds
Started May 05 01:15:28 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 212060 kb
Host smart-60f0b040-f597-4320-9118-9badc4a2c478
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885427882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1885427882
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1980755313
Short name T1341
Test name
Test status
Simulation time 94365827 ps
CPU time 0.59 seconds
Started May 05 01:15:38 PM PDT 24
Finished May 05 01:15:39 PM PDT 24
Peak memory 203652 kb
Host smart-93481a75-a4b3-41a3-a062-d5433a7f3510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980755313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1980755313
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3847094891
Short name T1324
Test name
Test status
Simulation time 516273350 ps
CPU time 1.58 seconds
Started May 05 01:15:27 PM PDT 24
Finished May 05 01:15:29 PM PDT 24
Peak memory 212064 kb
Host smart-3119a9f4-ba80-45ef-8834-bf11e03e82ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847094891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3847094891
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3034890973
Short name T388
Test name
Test status
Simulation time 1987675166 ps
CPU time 3.87 seconds
Started May 05 01:15:30 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 233636 kb
Host smart-ef8cc3f6-7252-40a2-8ce1-ba1d6ce8f87d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034890973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3034890973
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2014306788
Short name T51
Test name
Test status
Simulation time 2015680129 ps
CPU time 94.32 seconds
Started May 05 01:15:29 PM PDT 24
Finished May 05 01:17:04 PM PDT 24
Peak memory 505848 kb
Host smart-81d860aa-4acd-4696-913f-e49ddc3e07de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014306788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2014306788
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3213343682
Short name T1043
Test name
Test status
Simulation time 31040213765 ps
CPU time 138.11 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:17:45 PM PDT 24
Peak memory 647796 kb
Host smart-eade54f9-7f2b-4269-ab50-a433ecd9f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213343682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3213343682
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2307827338
Short name T71
Test name
Test status
Simulation time 84200710 ps
CPU time 0.95 seconds
Started May 05 01:15:30 PM PDT 24
Finished May 05 01:15:31 PM PDT 24
Peak memory 203660 kb
Host smart-110ba0ac-3326-4e70-b1b3-c2fed5813364
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307827338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2307827338
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3104622182
Short name T325
Test name
Test status
Simulation time 783358293 ps
CPU time 7.72 seconds
Started May 05 01:15:27 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 203836 kb
Host smart-a56bc011-fe09-4c79-924b-841d346c9d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104622182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3104622182
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1603071715
Short name T890
Test name
Test status
Simulation time 9224264538 ps
CPU time 99.82 seconds
Started May 05 01:15:28 PM PDT 24
Finished May 05 01:17:08 PM PDT 24
Peak memory 1051564 kb
Host smart-c6e6b262-f22c-42f1-888a-562da15abeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603071715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1603071715
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.2308486792
Short name T1326
Test name
Test status
Simulation time 779051641 ps
CPU time 15.42 seconds
Started May 05 01:15:32 PM PDT 24
Finished May 05 01:15:48 PM PDT 24
Peak memory 203868 kb
Host smart-cbce4647-0a4e-44b1-86d1-6509aa86ecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308486792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2308486792
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3531260082
Short name T32
Test name
Test status
Simulation time 1465512562 ps
CPU time 63.12 seconds
Started May 05 01:15:33 PM PDT 24
Finished May 05 01:16:37 PM PDT 24
Peak memory 319004 kb
Host smart-e13441fa-3a71-4285-81db-45679a0b87e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531260082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3531260082
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3284559511
Short name T199
Test name
Test status
Simulation time 203446750 ps
CPU time 0.66 seconds
Started May 05 01:15:25 PM PDT 24
Finished May 05 01:15:26 PM PDT 24
Peak memory 203620 kb
Host smart-4a0d65a6-73cb-4ce3-939d-dccdc71bd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284559511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3284559511
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3995702244
Short name T1003
Test name
Test status
Simulation time 5715544080 ps
CPU time 22.83 seconds
Started May 05 01:15:26 PM PDT 24
Finished May 05 01:15:50 PM PDT 24
Peak memory 341452 kb
Host smart-432f60b3-58a8-471d-b5cb-d51c401277d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995702244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3995702244
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1806845550
Short name T554
Test name
Test status
Simulation time 2402036559 ps
CPU time 17.65 seconds
Started May 05 01:15:28 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 251448 kb
Host smart-c37d4f17-da40-452d-89d1-bed6a5734c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806845550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1806845550
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1671695679
Short name T688
Test name
Test status
Simulation time 539342604 ps
CPU time 8.75 seconds
Started May 05 01:15:25 PM PDT 24
Finished May 05 01:15:34 PM PDT 24
Peak memory 217772 kb
Host smart-a6adedd6-cb59-4711-9d0a-75ad8384cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671695679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1671695679
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2008593894
Short name T766
Test name
Test status
Simulation time 8300738879 ps
CPU time 4.37 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:36 PM PDT 24
Peak memory 203896 kb
Host smart-473119e9-5360-48b5-b316-adf14e02351e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008593894 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2008593894
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3409810426
Short name T55
Test name
Test status
Simulation time 10039265107 ps
CPU time 70.17 seconds
Started May 05 01:15:38 PM PDT 24
Finished May 05 01:16:48 PM PDT 24
Peak memory 492936 kb
Host smart-6ffbbeba-a46e-45d3-97d4-b80a1ea2cbca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409810426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3409810426
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.941438273
Short name T1259
Test name
Test status
Simulation time 10086150854 ps
CPU time 82.28 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:16:54 PM PDT 24
Peak memory 470616 kb
Host smart-b8ab99c9-5cca-446b-ad98-aa9cfbfaad29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941438273 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.941438273
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3919799166
Short name T21
Test name
Test status
Simulation time 777035376 ps
CPU time 2.48 seconds
Started May 05 01:15:32 PM PDT 24
Finished May 05 01:15:35 PM PDT 24
Peak memory 203748 kb
Host smart-83111b41-c5fe-4b07-83ac-2cce2c6479c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919799166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3919799166
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2350604636
Short name T314
Test name
Test status
Simulation time 5779706136 ps
CPU time 7.04 seconds
Started May 05 01:15:36 PM PDT 24
Finished May 05 01:15:44 PM PDT 24
Peak memory 216944 kb
Host smart-9923e870-f5cb-407a-9036-9cde98a59615
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350604636 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2350604636
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2340594746
Short name T752
Test name
Test status
Simulation time 23709609798 ps
CPU time 63.28 seconds
Started May 05 01:15:32 PM PDT 24
Finished May 05 01:16:36 PM PDT 24
Peak memory 1350028 kb
Host smart-654856e7-757b-4538-afd9-4d436319d806
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340594746 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2340594746
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.661687756
Short name T558
Test name
Test status
Simulation time 797491647 ps
CPU time 10.47 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:42 PM PDT 24
Peak memory 203836 kb
Host smart-aef9a3a4-56fb-4c1f-b608-93a4b02e8a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661687756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.661687756
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2751407764
Short name T296
Test name
Test status
Simulation time 478050473 ps
CPU time 8.15 seconds
Started May 05 01:15:32 PM PDT 24
Finished May 05 01:15:41 PM PDT 24
Peak memory 203820 kb
Host smart-9873f982-6fcd-4c48-b084-56ae835e7a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751407764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2751407764
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.775174378
Short name T326
Test name
Test status
Simulation time 49058634903 ps
CPU time 138.98 seconds
Started May 05 01:15:33 PM PDT 24
Finished May 05 01:17:53 PM PDT 24
Peak memory 1913120 kb
Host smart-97a1a1c9-fb45-4443-af1e-19152c2c4a86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775174378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.775174378
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2913195304
Short name T121
Test name
Test status
Simulation time 29475702262 ps
CPU time 171.56 seconds
Started May 05 01:15:32 PM PDT 24
Finished May 05 01:18:24 PM PDT 24
Peak memory 1590312 kb
Host smart-fbc47041-d6d0-4b11-9daf-f9aa0f896a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913195304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2913195304
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3252623129
Short name T808
Test name
Test status
Simulation time 1796151373 ps
CPU time 7.34 seconds
Started May 05 01:15:31 PM PDT 24
Finished May 05 01:15:39 PM PDT 24
Peak memory 220068 kb
Host smart-0607677f-8b68-41fa-afcd-034c2c1668c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252623129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3252623129
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.719510368
Short name T111
Test name
Test status
Simulation time 45490711 ps
CPU time 0.59 seconds
Started May 05 01:15:41 PM PDT 24
Finished May 05 01:15:42 PM PDT 24
Peak memory 203712 kb
Host smart-a00888aa-8088-4459-b6e6-066c497cdeec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719510368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.719510368
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2476636262
Short name T1329
Test name
Test status
Simulation time 67061076 ps
CPU time 1.62 seconds
Started May 05 01:15:38 PM PDT 24
Finished May 05 01:15:40 PM PDT 24
Peak memory 212148 kb
Host smart-c4b42c1c-165a-4afb-85f5-3dc2d12d54b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476636262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2476636262
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1374416346
Short name T911
Test name
Test status
Simulation time 1356906327 ps
CPU time 6.01 seconds
Started May 05 01:15:39 PM PDT 24
Finished May 05 01:15:45 PM PDT 24
Peak memory 274140 kb
Host smart-00c4ec33-24f0-4bd5-b584-e22ea70fa830
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374416346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1374416346
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1929546972
Short name T602
Test name
Test status
Simulation time 1978937109 ps
CPU time 61.33 seconds
Started May 05 01:15:39 PM PDT 24
Finished May 05 01:16:41 PM PDT 24
Peak memory 618180 kb
Host smart-87b5bc7f-3fb4-47ed-bf39-a1e99fe1ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929546972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1929546972
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3955422791
Short name T1120
Test name
Test status
Simulation time 11100457124 ps
CPU time 34.06 seconds
Started May 05 01:15:40 PM PDT 24
Finished May 05 01:16:14 PM PDT 24
Peak memory 478452 kb
Host smart-28206b1e-4dc2-4b79-9313-9a56b4fe6891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955422791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3955422791
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4294214783
Short name T881
Test name
Test status
Simulation time 95833156 ps
CPU time 0.88 seconds
Started May 05 01:15:37 PM PDT 24
Finished May 05 01:15:39 PM PDT 24
Peak memory 203640 kb
Host smart-77cb60a7-7722-4ec5-a998-ac562e847cc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294214783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4294214783
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3155790060
Short name T79
Test name
Test status
Simulation time 488021519 ps
CPU time 3.1 seconds
Started May 05 01:15:37 PM PDT 24
Finished May 05 01:15:41 PM PDT 24
Peak memory 221896 kb
Host smart-d471f264-c8b2-4f4d-a391-94fd22880d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155790060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3155790060
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3637482115
Short name T1237
Test name
Test status
Simulation time 61601562339 ps
CPU time 210.34 seconds
Started May 05 01:15:36 PM PDT 24
Finished May 05 01:19:07 PM PDT 24
Peak memory 969316 kb
Host smart-189f6ef1-deac-4ab7-921c-08d8ec9e729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637482115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3637482115
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2082445544
Short name T991
Test name
Test status
Simulation time 197925053 ps
CPU time 7.22 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:15:55 PM PDT 24
Peak memory 203804 kb
Host smart-eb00e178-ecdd-4cdc-825b-0e18166992be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082445544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2082445544
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1454919328
Short name T565
Test name
Test status
Simulation time 4096646578 ps
CPU time 93.68 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:17:17 PM PDT 24
Peak memory 349252 kb
Host smart-889cf78f-ff7a-4dab-bd34-4bd1fec3738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454919328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1454919328
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3063957268
Short name T900
Test name
Test status
Simulation time 71464764 ps
CPU time 0.64 seconds
Started May 05 01:15:36 PM PDT 24
Finished May 05 01:15:37 PM PDT 24
Peak memory 203660 kb
Host smart-89b4de22-7221-4c42-9ddc-e716e56488be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063957268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3063957268
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.386352312
Short name T1186
Test name
Test status
Simulation time 578864086 ps
CPU time 10.04 seconds
Started May 05 01:15:39 PM PDT 24
Finished May 05 01:15:50 PM PDT 24
Peak memory 268492 kb
Host smart-c925fbbc-ccea-4b6e-b90e-aa98ebedfdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386352312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.386352312
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1544061674
Short name T258
Test name
Test status
Simulation time 2013010822 ps
CPU time 28.96 seconds
Started May 05 01:15:35 PM PDT 24
Finished May 05 01:16:05 PM PDT 24
Peak memory 291552 kb
Host smart-7b1e2826-05f2-4edc-81dd-3f9e5abd13fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544061674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1544061674
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1179979947
Short name T1354
Test name
Test status
Simulation time 494256610 ps
CPU time 8.26 seconds
Started May 05 01:15:37 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 212036 kb
Host smart-80a08dd6-b462-48ec-b435-d39b03c48797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179979947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1179979947
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1565454210
Short name T1092
Test name
Test status
Simulation time 4119323698 ps
CPU time 4.48 seconds
Started May 05 01:15:41 PM PDT 24
Finished May 05 01:15:46 PM PDT 24
Peak memory 212888 kb
Host smart-5dd22ada-6963-4d9e-b001-4b84cfa0533f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565454210 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1565454210
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2372853480
Short name T921
Test name
Test status
Simulation time 10076427368 ps
CPU time 66.37 seconds
Started May 05 01:15:41 PM PDT 24
Finished May 05 01:16:48 PM PDT 24
Peak memory 468804 kb
Host smart-faeadd9c-f669-4f00-88c2-d7c61fc9fcda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372853480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2372853480
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2738411145
Short name T1093
Test name
Test status
Simulation time 10053054744 ps
CPU time 26.96 seconds
Started May 05 01:15:42 PM PDT 24
Finished May 05 01:16:10 PM PDT 24
Peak memory 316056 kb
Host smart-5cfff6ea-5def-49cf-a798-039cbb7ff8ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738411145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2738411145
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3622687663
Short name T1218
Test name
Test status
Simulation time 338102241 ps
CPU time 2.24 seconds
Started May 05 01:15:46 PM PDT 24
Finished May 05 01:15:48 PM PDT 24
Peak memory 203788 kb
Host smart-dac294a4-28af-4e0d-ab5d-56a5dac1f4be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622687663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3622687663
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1085383872
Short name T96
Test name
Test status
Simulation time 2639821082 ps
CPU time 3.57 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:15:47 PM PDT 24
Peak memory 203908 kb
Host smart-663c4841-93fd-4603-ae86-e364b835855e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085383872 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1085383872
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2224302532
Short name T957
Test name
Test status
Simulation time 27765299377 ps
CPU time 34.54 seconds
Started May 05 01:15:44 PM PDT 24
Finished May 05 01:16:19 PM PDT 24
Peak memory 806932 kb
Host smart-d0662e18-d77c-46b4-a516-7bedc5708062
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224302532 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2224302532
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3036121970
Short name T995
Test name
Test status
Simulation time 18349108799 ps
CPU time 50.78 seconds
Started May 05 01:15:41 PM PDT 24
Finished May 05 01:16:32 PM PDT 24
Peak memory 203984 kb
Host smart-0e89a27b-cb03-4ae9-9082-611b6eb07a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036121970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3036121970
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1191850121
Short name T1271
Test name
Test status
Simulation time 787240304 ps
CPU time 13.48 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:15:57 PM PDT 24
Peak memory 208132 kb
Host smart-9dab1f03-bb7f-48d2-9d03-d51deaa44bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191850121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1191850121
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3015871598
Short name T286
Test name
Test status
Simulation time 10202075873 ps
CPU time 4.76 seconds
Started May 05 01:15:44 PM PDT 24
Finished May 05 01:15:49 PM PDT 24
Peak memory 203900 kb
Host smart-484128ff-af60-4527-a3b7-7094e611f1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015871598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3015871598
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3294379258
Short name T123
Test name
Test status
Simulation time 18982721569 ps
CPU time 1020.24 seconds
Started May 05 01:15:44 PM PDT 24
Finished May 05 01:32:45 PM PDT 24
Peak memory 4669612 kb
Host smart-5584ff58-8b04-4518-8515-d25ba46fc18c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294379258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3294379258
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3706990744
Short name T1210
Test name
Test status
Simulation time 6150992507 ps
CPU time 7.54 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:15:51 PM PDT 24
Peak memory 219664 kb
Host smart-50d3a94e-3a16-4e39-9d18-89eb54715567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706990744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3706990744
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.824203968
Short name T1000
Test name
Test status
Simulation time 45299470 ps
CPU time 0.61 seconds
Started May 05 01:15:57 PM PDT 24
Finished May 05 01:15:58 PM PDT 24
Peak memory 203724 kb
Host smart-23526614-1129-4d3d-be3d-a5bc6255c875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824203968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.824203968
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.389619005
Short name T852
Test name
Test status
Simulation time 1131973182 ps
CPU time 1.49 seconds
Started May 05 01:15:48 PM PDT 24
Finished May 05 01:15:50 PM PDT 24
Peak memory 215768 kb
Host smart-6e981f82-7c2d-457c-8718-8ae484fa8a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389619005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.389619005
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2194448047
Short name T261
Test name
Test status
Simulation time 359223683 ps
CPU time 6.34 seconds
Started May 05 01:15:48 PM PDT 24
Finished May 05 01:15:55 PM PDT 24
Peak memory 275084 kb
Host smart-11c9b05e-4ec6-4ede-badd-5933d9e23205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194448047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2194448047
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3323122332
Short name T1265
Test name
Test status
Simulation time 11772406356 ps
CPU time 45.76 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:16:33 PM PDT 24
Peak memory 532708 kb
Host smart-4cc1be92-4b4e-479b-abde-15ecc4aad351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323122332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3323122332
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3600390852
Short name T495
Test name
Test status
Simulation time 2299311563 ps
CPU time 70.64 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:16:58 PM PDT 24
Peak memory 767988 kb
Host smart-d9fe9fc8-6e08-4d63-a353-ef42ac8c6ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600390852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3600390852
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2947464623
Short name T1302
Test name
Test status
Simulation time 875584020 ps
CPU time 0.88 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:15:49 PM PDT 24
Peak memory 203736 kb
Host smart-d7224101-9302-4552-8e68-23d1ddb72316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947464623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2947464623
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.654766795
Short name T405
Test name
Test status
Simulation time 252103372 ps
CPU time 3.22 seconds
Started May 05 01:15:48 PM PDT 24
Finished May 05 01:15:52 PM PDT 24
Peak memory 203836 kb
Host smart-dc42b047-01d5-4369-b366-251c0c32bd7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654766795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
654766795
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1348843265
Short name T1233
Test name
Test status
Simulation time 12088732322 ps
CPU time 64.7 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:16:48 PM PDT 24
Peak memory 838456 kb
Host smart-b25131da-7938-452c-a2e1-c48baee9a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348843265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1348843265
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3686822721
Short name T749
Test name
Test status
Simulation time 6484857452 ps
CPU time 7.12 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:16:07 PM PDT 24
Peak memory 203856 kb
Host smart-24597353-eff5-4fdd-8f60-2119e6b06af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686822721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3686822721
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.617558168
Short name T34
Test name
Test status
Simulation time 4506411996 ps
CPU time 15.68 seconds
Started May 05 01:15:52 PM PDT 24
Finished May 05 01:16:09 PM PDT 24
Peak memory 260756 kb
Host smart-c71e9ca5-280f-4eaa-bb73-4df2a0057925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617558168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.617558168
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1796256996
Short name T1357
Test name
Test status
Simulation time 47210076 ps
CPU time 0.71 seconds
Started May 05 01:15:42 PM PDT 24
Finished May 05 01:15:43 PM PDT 24
Peak memory 203652 kb
Host smart-c3c35c54-ce48-46c7-a7b0-3377fc44c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796256996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1796256996
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.779859383
Short name T407
Test name
Test status
Simulation time 2559018723 ps
CPU time 36.6 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:16:24 PM PDT 24
Peak memory 223644 kb
Host smart-c2428888-d36e-4bfb-8d67-d704a77f8ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779859383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.779859383
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2992581851
Short name T954
Test name
Test status
Simulation time 3750004976 ps
CPU time 56.16 seconds
Started May 05 01:15:43 PM PDT 24
Finished May 05 01:16:40 PM PDT 24
Peak memory 326656 kb
Host smart-2a8cc20e-95e3-4af2-827f-6c9a4d2d0724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992581851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2992581851
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.3905122621
Short name T249
Test name
Test status
Simulation time 20968838609 ps
CPU time 267.22 seconds
Started May 05 01:15:48 PM PDT 24
Finished May 05 01:20:16 PM PDT 24
Peak memory 1187412 kb
Host smart-6040a583-a17b-4e8b-8566-cb6aa7f201f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905122621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3905122621
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2622441180
Short name T486
Test name
Test status
Simulation time 8354058223 ps
CPU time 9.44 seconds
Started May 05 01:15:49 PM PDT 24
Finished May 05 01:15:59 PM PDT 24
Peak memory 228064 kb
Host smart-5f52e53a-b5f5-4bcb-b875-7e837a9658b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622441180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2622441180
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.5078126
Short name T717
Test name
Test status
Simulation time 4455044206 ps
CPU time 3.31 seconds
Started May 05 01:15:51 PM PDT 24
Finished May 05 01:15:55 PM PDT 24
Peak memory 203888 kb
Host smart-9dfb47dd-4935-4de2-9a7a-3b04a8d376f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5078126 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_bad_addr.5078126
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.924899274
Short name T896
Test name
Test status
Simulation time 10552333390 ps
CPU time 7.89 seconds
Started May 05 01:15:54 PM PDT 24
Finished May 05 01:16:02 PM PDT 24
Peak memory 251300 kb
Host smart-027c1819-dab2-4356-a75e-2694a9ead47e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924899274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.924899274
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.911204151
Short name T450
Test name
Test status
Simulation time 10537622674 ps
CPU time 13.03 seconds
Started May 05 01:15:52 PM PDT 24
Finished May 05 01:16:06 PM PDT 24
Peak memory 266228 kb
Host smart-172e92a7-f2fe-4bf0-97d1-5e22ee2be597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911204151 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.911204151
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.758470454
Short name T780
Test name
Test status
Simulation time 1281477392 ps
CPU time 2.73 seconds
Started May 05 01:15:54 PM PDT 24
Finished May 05 01:15:57 PM PDT 24
Peak memory 203844 kb
Host smart-d2685567-fc07-48db-b4a4-0312f47d7cb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758470454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.758470454
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1771968408
Short name T464
Test name
Test status
Simulation time 6428262796 ps
CPU time 3.74 seconds
Started May 05 01:15:53 PM PDT 24
Finished May 05 01:15:57 PM PDT 24
Peak memory 203976 kb
Host smart-546b3b18-49f6-4a89-9a20-5d3df0edc6ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771968408 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1771968408
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1785737908
Short name T1208
Test name
Test status
Simulation time 13210067160 ps
CPU time 48.09 seconds
Started May 05 01:15:54 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 1155208 kb
Host smart-9198a888-9a26-4bc3-99f4-fe420c6cf045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785737908 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1785737908
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1068028797
Short name T275
Test name
Test status
Simulation time 3562778922 ps
CPU time 33.28 seconds
Started May 05 01:15:47 PM PDT 24
Finished May 05 01:16:21 PM PDT 24
Peak memory 203856 kb
Host smart-82cd9c76-39df-4df1-9969-11edc299b118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068028797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1068028797
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.501339056
Short name T1239
Test name
Test status
Simulation time 957127771 ps
CPU time 20.62 seconds
Started May 05 01:15:49 PM PDT 24
Finished May 05 01:16:10 PM PDT 24
Peak memory 203896 kb
Host smart-5a9dcf7f-e371-4b99-afd0-6467cabf8766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501339056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.501339056
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3571152726
Short name T18
Test name
Test status
Simulation time 60557189869 ps
CPU time 589.25 seconds
Started May 05 01:15:48 PM PDT 24
Finished May 05 01:25:38 PM PDT 24
Peak memory 4861104 kb
Host smart-c33d2079-2bf4-4a8d-81ec-571f8a018600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571152726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3571152726
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.438676863
Short name T614
Test name
Test status
Simulation time 10487991545 ps
CPU time 1076.09 seconds
Started May 05 01:15:53 PM PDT 24
Finished May 05 01:33:50 PM PDT 24
Peak memory 2600732 kb
Host smart-658324cd-166f-4d32-a3d7-15033745b144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438676863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.438676863
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.226658897
Short name T1030
Test name
Test status
Simulation time 6173064062 ps
CPU time 6.27 seconds
Started May 05 01:15:51 PM PDT 24
Finished May 05 01:15:59 PM PDT 24
Peak memory 203896 kb
Host smart-07f0c058-4bdc-4539-856a-866dee4c8c85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226658897 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.226658897
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2159039240
Short name T986
Test name
Test status
Simulation time 46945496 ps
CPU time 0.59 seconds
Started May 05 01:16:04 PM PDT 24
Finished May 05 01:16:05 PM PDT 24
Peak memory 203732 kb
Host smart-fc45fd88-4d8c-48ec-8d28-4ad2a4cd72f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159039240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2159039240
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3580307983
Short name T641
Test name
Test status
Simulation time 462233076 ps
CPU time 1.3 seconds
Started May 05 01:16:00 PM PDT 24
Finished May 05 01:16:01 PM PDT 24
Peak memory 212148 kb
Host smart-724fbd6f-356e-49ea-983f-b3ae56570bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580307983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3580307983
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1827837878
Short name T1203
Test name
Test status
Simulation time 5201851979 ps
CPU time 7.06 seconds
Started May 05 01:15:57 PM PDT 24
Finished May 05 01:16:05 PM PDT 24
Peak memory 267216 kb
Host smart-48821577-66f9-4b66-8f0e-10192250b5d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827837878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1827837878
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3273192097
Short name T95
Test name
Test status
Simulation time 2350843568 ps
CPU time 41.2 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:16:41 PM PDT 24
Peak memory 482472 kb
Host smart-43168ca7-abf2-400d-bcfd-54b0d72ac666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273192097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3273192097
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.4177183994
Short name T125
Test name
Test status
Simulation time 2224540677 ps
CPU time 78.92 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:17:19 PM PDT 24
Peak memory 733464 kb
Host smart-2248df0c-f7fd-452e-b6ca-78e70f8b504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177183994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.4177183994
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3998767840
Short name T72
Test name
Test status
Simulation time 137621394 ps
CPU time 1.1 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:16:00 PM PDT 24
Peak memory 203788 kb
Host smart-b1b1fd60-81cb-48a1-8e27-6bde09eb3b3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998767840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3998767840
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.136764060
Short name T290
Test name
Test status
Simulation time 105608481 ps
CPU time 3.34 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:16:03 PM PDT 24
Peak memory 219148 kb
Host smart-6fd5b9ea-ad45-4df4-a9ba-5f9ca51c27e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136764060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
136764060
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3915952162
Short name T851
Test name
Test status
Simulation time 5750619945 ps
CPU time 59.99 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:16:59 PM PDT 24
Peak memory 811528 kb
Host smart-8c1f1042-479a-4485-9560-1723e17c785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915952162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3915952162
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3865881712
Short name T777
Test name
Test status
Simulation time 251132050 ps
CPU time 9.33 seconds
Started May 05 01:16:05 PM PDT 24
Finished May 05 01:16:15 PM PDT 24
Peak memory 203836 kb
Host smart-df8a390f-84b7-4af2-a475-91adb482f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865881712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3865881712
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1803048857
Short name T745
Test name
Test status
Simulation time 4620397978 ps
CPU time 62.48 seconds
Started May 05 01:16:05 PM PDT 24
Finished May 05 01:17:08 PM PDT 24
Peak memory 333832 kb
Host smart-d2494f2a-c391-418f-969e-7033a748e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803048857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1803048857
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2006315241
Short name T471
Test name
Test status
Simulation time 27184841 ps
CPU time 0.65 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:15:59 PM PDT 24
Peak memory 203680 kb
Host smart-93883c2e-bbae-46ac-9ea4-789377a3369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006315241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2006315241
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.252221664
Short name T1076
Test name
Test status
Simulation time 776849577 ps
CPU time 3.19 seconds
Started May 05 01:15:57 PM PDT 24
Finished May 05 01:16:00 PM PDT 24
Peak memory 220164 kb
Host smart-12f9e7e1-96dd-4397-9293-4be4d345ec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252221664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.252221664
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2350816263
Short name T887
Test name
Test status
Simulation time 2407476174 ps
CPU time 22.19 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:16:21 PM PDT 24
Peak memory 349600 kb
Host smart-9cb38c0a-5791-4af2-84a5-80ecb2ba86e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350816263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2350816263
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.925856519
Short name T1300
Test name
Test status
Simulation time 1944403561 ps
CPU time 8.41 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:16:08 PM PDT 24
Peak memory 217128 kb
Host smart-fdbb02ba-7245-4d39-9de9-a61d41d2af82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925856519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.925856519
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2126010385
Short name T876
Test name
Test status
Simulation time 1149818907 ps
CPU time 5 seconds
Started May 05 01:16:08 PM PDT 24
Finished May 05 01:16:13 PM PDT 24
Peak memory 203888 kb
Host smart-6196f070-294d-4928-83c2-a8abd32918fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126010385 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2126010385
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2330496560
Short name T1356
Test name
Test status
Simulation time 10100138468 ps
CPU time 28.62 seconds
Started May 05 01:16:04 PM PDT 24
Finished May 05 01:16:33 PM PDT 24
Peak memory 326484 kb
Host smart-fadc7778-b388-49d4-9eaf-aa82be583348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330496560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2330496560
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3458939876
Short name T584
Test name
Test status
Simulation time 10475863855 ps
CPU time 15.96 seconds
Started May 05 01:16:07 PM PDT 24
Finished May 05 01:16:23 PM PDT 24
Peak memory 290524 kb
Host smart-d8c959ba-afbd-465c-8d33-bc5eb78c9a0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458939876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3458939876
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.3040807234
Short name T410
Test name
Test status
Simulation time 1723176929 ps
CPU time 2.37 seconds
Started May 05 01:16:07 PM PDT 24
Finished May 05 01:16:10 PM PDT 24
Peak memory 203816 kb
Host smart-b01fa079-87ed-454d-97bc-09ce08b66aea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040807234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.3040807234
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.383685833
Short name T341
Test name
Test status
Simulation time 2791131651 ps
CPU time 4.1 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:16:03 PM PDT 24
Peak memory 203924 kb
Host smart-aec9fe20-5251-4b0d-80ef-e998fd9e60b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383685833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.383685833
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.783460700
Short name T1040
Test name
Test status
Simulation time 12568773568 ps
CPU time 30.81 seconds
Started May 05 01:16:01 PM PDT 24
Finished May 05 01:16:32 PM PDT 24
Peak memory 862864 kb
Host smart-f7c7ab53-8dfc-460e-9087-2a2148df5a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783460700 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.783460700
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1788156442
Short name T750
Test name
Test status
Simulation time 938316047 ps
CPU time 13.01 seconds
Started May 05 01:15:59 PM PDT 24
Finished May 05 01:16:13 PM PDT 24
Peak memory 203840 kb
Host smart-164d13f9-ff9c-472b-a6f8-31c50cf9fb50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788156442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1788156442
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4093640245
Short name T607
Test name
Test status
Simulation time 535681435 ps
CPU time 10.16 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:16:09 PM PDT 24
Peak memory 208360 kb
Host smart-d5324538-29b7-4112-8cb2-6128ba94e8f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093640245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4093640245
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.563543086
Short name T776
Test name
Test status
Simulation time 25298186140 ps
CPU time 73.78 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:17:13 PM PDT 24
Peak memory 1145832 kb
Host smart-eca42064-d0fa-478f-9d75-2e6b7cf18170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563543086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.563543086
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3627414616
Short name T861
Test name
Test status
Simulation time 15494208160 ps
CPU time 82.54 seconds
Started May 05 01:15:58 PM PDT 24
Finished May 05 01:17:22 PM PDT 24
Peak memory 973596 kb
Host smart-d05ab55f-b812-4fe2-99fa-44a9ba418a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627414616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3627414616
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2066803160
Short name T605
Test name
Test status
Simulation time 8292559970 ps
CPU time 7 seconds
Started May 05 01:16:06 PM PDT 24
Finished May 05 01:16:13 PM PDT 24
Peak memory 203928 kb
Host smart-4f16d7c3-1d96-40d0-9ec1-8db76bbf160e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066803160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2066803160
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1815473642
Short name T617
Test name
Test status
Simulation time 92717390 ps
CPU time 0.61 seconds
Started May 05 01:10:06 PM PDT 24
Finished May 05 01:10:07 PM PDT 24
Peak memory 203736 kb
Host smart-9cfd386c-3981-44e7-b52e-56341e1f0b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815473642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1815473642
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.91956656
Short name T557
Test name
Test status
Simulation time 236079397 ps
CPU time 1.13 seconds
Started May 05 01:09:58 PM PDT 24
Finished May 05 01:10:00 PM PDT 24
Peak memory 215248 kb
Host smart-315989be-b8b5-4565-a9b4-eb2a87f267cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91956656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.91956656
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1155097334
Short name T1331
Test name
Test status
Simulation time 355830357 ps
CPU time 17.01 seconds
Started May 05 01:09:55 PM PDT 24
Finished May 05 01:10:13 PM PDT 24
Peak memory 244532 kb
Host smart-c6b7c3fa-601f-41f5-8611-c4651fb1afe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155097334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1155097334
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3020370125
Short name T804
Test name
Test status
Simulation time 2282278894 ps
CPU time 72.63 seconds
Started May 05 01:10:01 PM PDT 24
Finished May 05 01:11:15 PM PDT 24
Peak memory 724228 kb
Host smart-253a86d4-cf65-42f6-8b8e-6abd592f0478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020370125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3020370125
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2519580499
Short name T922
Test name
Test status
Simulation time 1899789378 ps
CPU time 54.93 seconds
Started May 05 01:09:54 PM PDT 24
Finished May 05 01:10:50 PM PDT 24
Peak memory 642472 kb
Host smart-b1acb663-34c8-40ec-b856-41bb376eab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519580499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2519580499
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2643714916
Short name T587
Test name
Test status
Simulation time 691134555 ps
CPU time 1.02 seconds
Started May 05 01:09:53 PM PDT 24
Finished May 05 01:09:55 PM PDT 24
Peak memory 203724 kb
Host smart-d2c2fa4e-bfda-450d-8719-ecb21531aa36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643714916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2643714916
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2392276487
Short name T865
Test name
Test status
Simulation time 1010850827 ps
CPU time 3.94 seconds
Started May 05 01:09:54 PM PDT 24
Finished May 05 01:09:59 PM PDT 24
Peak memory 203832 kb
Host smart-49b8d9b8-713e-4128-bcab-622a0897a420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392276487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2392276487
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1246899533
Short name T180
Test name
Test status
Simulation time 10007624198 ps
CPU time 53.89 seconds
Started May 05 01:09:57 PM PDT 24
Finished May 05 01:10:51 PM PDT 24
Peak memory 799400 kb
Host smart-1a1fd37b-a6f7-42e0-bff1-344e0fcf35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246899533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1246899533
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2783347845
Short name T1297
Test name
Test status
Simulation time 1096770842 ps
CPU time 11.23 seconds
Started May 05 01:10:03 PM PDT 24
Finished May 05 01:10:15 PM PDT 24
Peak memory 203820 kb
Host smart-2f40bf1e-6556-4fe0-bd3b-d39c274e79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783347845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2783347845
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3618314871
Short name T783
Test name
Test status
Simulation time 1367439486 ps
CPU time 64.98 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:11:10 PM PDT 24
Peak memory 353008 kb
Host smart-403d9407-2218-4138-ac81-32271aaece59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618314871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3618314871
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3783923314
Short name T590
Test name
Test status
Simulation time 28735111 ps
CPU time 0.66 seconds
Started May 05 01:09:55 PM PDT 24
Finished May 05 01:09:56 PM PDT 24
Peak memory 203668 kb
Host smart-bb7b8241-bcbe-4ed7-ad6b-ac179db46f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783923314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3783923314
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3762475844
Short name T918
Test name
Test status
Simulation time 2961137319 ps
CPU time 89.12 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:11:29 PM PDT 24
Peak memory 843732 kb
Host smart-39e8888a-02e3-4dd5-b03f-74c81bd9e8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762475844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3762475844
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2728679821
Short name T785
Test name
Test status
Simulation time 2150536503 ps
CPU time 50.58 seconds
Started May 05 01:09:54 PM PDT 24
Finished May 05 01:10:45 PM PDT 24
Peak memory 314692 kb
Host smart-8331c01b-86c5-464e-9f42-c400a5bbf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728679821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2728679821
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2643014427
Short name T244
Test name
Test status
Simulation time 71411747495 ps
CPU time 1680.74 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:38:00 PM PDT 24
Peak memory 2097796 kb
Host smart-4187a384-023f-4537-8584-c5c305b8aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643014427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2643014427
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1556730848
Short name T318
Test name
Test status
Simulation time 2798246843 ps
CPU time 7.75 seconds
Started May 05 01:09:58 PM PDT 24
Finished May 05 01:10:06 PM PDT 24
Peak memory 212128 kb
Host smart-d782c4b3-f3e9-42ca-9f08-184f8755e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556730848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1556730848
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3050276410
Short name T119
Test name
Test status
Simulation time 34125216 ps
CPU time 0.8 seconds
Started May 05 01:10:03 PM PDT 24
Finished May 05 01:10:04 PM PDT 24
Peak memory 221372 kb
Host smart-107f5c84-d396-4258-b636-96c6bd6e5fee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050276410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3050276410
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1949081701
Short name T391
Test name
Test status
Simulation time 3880427642 ps
CPU time 5.83 seconds
Started May 05 01:10:01 PM PDT 24
Finished May 05 01:10:08 PM PDT 24
Peak memory 212688 kb
Host smart-3fe9a080-684e-40f8-b2ff-324f89371af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949081701 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1949081701
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3852597562
Short name T253
Test name
Test status
Simulation time 11305281760 ps
CPU time 5.46 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:10:10 PM PDT 24
Peak memory 244912 kb
Host smart-991a110d-4f1a-4add-b185-9fb30528791b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852597562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3852597562
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1045665691
Short name T208
Test name
Test status
Simulation time 10179924244 ps
CPU time 34.98 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:10:39 PM PDT 24
Peak memory 341044 kb
Host smart-54249538-6689-4ad3-ada7-d7a41117ecbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045665691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1045665691
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2718023435
Short name T1314
Test name
Test status
Simulation time 469142915 ps
CPU time 2.5 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:10:07 PM PDT 24
Peak memory 203872 kb
Host smart-475088da-e556-45de-a3e5-d24f8cb86e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718023435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2718023435
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1198406766
Short name T7
Test name
Test status
Simulation time 7801363976 ps
CPU time 5.14 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:10:05 PM PDT 24
Peak memory 206176 kb
Host smart-ed4c0bb9-45be-4f96-8bae-73b948a698b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198406766 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1198406766
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2712813199
Short name T1149
Test name
Test status
Simulation time 3678103206 ps
CPU time 2.65 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:10:02 PM PDT 24
Peak memory 203868 kb
Host smart-a8aa88ff-8d2a-4a1e-b480-badce0ad2d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712813199 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2712813199
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2973876333
Short name T606
Test name
Test status
Simulation time 3024820724 ps
CPU time 30.38 seconds
Started May 05 01:09:58 PM PDT 24
Finished May 05 01:10:29 PM PDT 24
Peak memory 203892 kb
Host smart-81ef56a3-04e7-41c7-bcc3-ec1072636f61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973876333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2973876333
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3915484662
Short name T897
Test name
Test status
Simulation time 1698799407 ps
CPU time 68.32 seconds
Started May 05 01:10:01 PM PDT 24
Finished May 05 01:11:10 PM PDT 24
Peak memory 206220 kb
Host smart-32a5b12a-0b37-4cce-95d6-93383d87a3df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915484662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3915484662
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2981299173
Short name T734
Test name
Test status
Simulation time 35414198518 ps
CPU time 400 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:16:40 PM PDT 24
Peak memory 3897508 kb
Host smart-6bd76751-1e13-44e5-88ca-cdcbc4aa610b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981299173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2981299173
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.359749048
Short name T550
Test name
Test status
Simulation time 27847387975 ps
CPU time 174.22 seconds
Started May 05 01:09:58 PM PDT 24
Finished May 05 01:12:53 PM PDT 24
Peak memory 1681152 kb
Host smart-d042d8ad-4d00-46b0-9147-ee163c86bf1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359749048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.359749048
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3126904062
Short name T563
Test name
Test status
Simulation time 9122279756 ps
CPU time 7.23 seconds
Started May 05 01:09:59 PM PDT 24
Finished May 05 01:10:07 PM PDT 24
Peak memory 218224 kb
Host smart-75679555-ad88-4d3d-b6ff-8d8cfac91bae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126904062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3126904062
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1400161445
Short name T869
Test name
Test status
Simulation time 776497851 ps
CPU time 4.57 seconds
Started May 05 01:10:05 PM PDT 24
Finished May 05 01:10:10 PM PDT 24
Peak memory 207896 kb
Host smart-a42ab6da-d221-4e6b-b58e-a238ecca9c52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400161445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1400161445
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1115657918
Short name T1101
Test name
Test status
Simulation time 35299136 ps
CPU time 0.61 seconds
Started May 05 01:16:20 PM PDT 24
Finished May 05 01:16:22 PM PDT 24
Peak memory 203460 kb
Host smart-b36354ef-c0e9-4c3e-be3e-ab17b1db15ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115657918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1115657918
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.81740224
Short name T577
Test name
Test status
Simulation time 112194067 ps
CPU time 1.21 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:16:16 PM PDT 24
Peak memory 212092 kb
Host smart-3e65dd65-d6b3-4ea9-a8cd-a87fc8e49743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81740224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.81740224
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2408731068
Short name T1269
Test name
Test status
Simulation time 703836999 ps
CPU time 18.72 seconds
Started May 05 01:16:11 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 276748 kb
Host smart-cc6b7f20-b628-4753-91e3-f5cb341d78a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408731068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2408731068
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.808992336
Short name T357
Test name
Test status
Simulation time 1200876406 ps
CPU time 27.68 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:16:43 PM PDT 24
Peak memory 213424 kb
Host smart-2854c92c-5748-4810-b5ea-5d76396b58df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808992336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.808992336
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.4131790086
Short name T811
Test name
Test status
Simulation time 1331669610 ps
CPU time 87.95 seconds
Started May 05 01:16:13 PM PDT 24
Finished May 05 01:17:41 PM PDT 24
Peak memory 501716 kb
Host smart-99becc1a-b247-4f51-9169-90c7c59aa911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131790086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.4131790086
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2930632859
Short name T1133
Test name
Test status
Simulation time 128012128 ps
CPU time 1.07 seconds
Started May 05 01:16:09 PM PDT 24
Finished May 05 01:16:11 PM PDT 24
Peak memory 203700 kb
Host smart-ac9d191c-4048-445a-b4d4-795fba26575e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930632859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2930632859
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3756807021
Short name T1347
Test name
Test status
Simulation time 158041102 ps
CPU time 8.11 seconds
Started May 05 01:16:10 PM PDT 24
Finished May 05 01:16:19 PM PDT 24
Peak memory 229324 kb
Host smart-ebc489b3-7373-43f2-a99f-ba3ff3e4b681
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756807021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3756807021
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.4043645136
Short name T90
Test name
Test status
Simulation time 2836980872 ps
CPU time 72.83 seconds
Started May 05 01:16:07 PM PDT 24
Finished May 05 01:17:20 PM PDT 24
Peak memory 851460 kb
Host smart-dd555174-9fb1-465b-96fe-1f24872b278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043645136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4043645136
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.594159962
Short name T724
Test name
Test status
Simulation time 703113311 ps
CPU time 5.51 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:16:21 PM PDT 24
Peak memory 203804 kb
Host smart-016a0a7b-3db0-4fdf-819e-f871794184d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594159962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.594159962
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1430654
Short name T947
Test name
Test status
Simulation time 1044445162 ps
CPU time 17.55 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:16:33 PM PDT 24
Peak memory 314604 kb
Host smart-0ec79beb-9cfd-439e-9238-0e1ff368c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1430654
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2815676238
Short name T288
Test name
Test status
Simulation time 31137950 ps
CPU time 0.66 seconds
Started May 05 01:16:05 PM PDT 24
Finished May 05 01:16:06 PM PDT 24
Peak memory 203660 kb
Host smart-9d754e6e-2d18-46bb-8fbc-398df17ddce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815676238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2815676238
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2792426606
Short name T1005
Test name
Test status
Simulation time 27391754715 ps
CPU time 1338.51 seconds
Started May 05 01:16:11 PM PDT 24
Finished May 05 01:38:30 PM PDT 24
Peak memory 504236 kb
Host smart-e0587d51-b528-4894-9a0d-90739ca199d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792426606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2792426606
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2861782949
Short name T479
Test name
Test status
Simulation time 5379536052 ps
CPU time 63.4 seconds
Started May 05 01:16:04 PM PDT 24
Finished May 05 01:17:08 PM PDT 24
Peak memory 289028 kb
Host smart-3afff67c-9a24-45ba-9e3d-43954a8bbaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861782949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2861782949
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2970894508
Short name T787
Test name
Test status
Simulation time 18059113041 ps
CPU time 994.19 seconds
Started May 05 01:16:11 PM PDT 24
Finished May 05 01:32:46 PM PDT 24
Peak memory 2431904 kb
Host smart-c3eac808-7bf5-4735-b10e-cbc65118a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970894508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2970894508
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2920507509
Short name T235
Test name
Test status
Simulation time 2338927615 ps
CPU time 25.71 seconds
Started May 05 01:16:10 PM PDT 24
Finished May 05 01:16:36 PM PDT 24
Peak memory 212144 kb
Host smart-a326bfb8-ae34-40ec-bfe4-37216a9b00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920507509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2920507509
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1393440669
Short name T1206
Test name
Test status
Simulation time 3215615760 ps
CPU time 4.02 seconds
Started May 05 01:16:09 PM PDT 24
Finished May 05 01:16:14 PM PDT 24
Peak memory 212192 kb
Host smart-80158da6-60ad-4a1d-8217-135fa879847f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393440669 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1393440669
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2662043369
Short name T60
Test name
Test status
Simulation time 10081391923 ps
CPU time 87.48 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:17:43 PM PDT 24
Peak memory 432232 kb
Host smart-6c3dd458-1ea7-4b6d-b1f4-36d6912324ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662043369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2662043369
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.741695124
Short name T1165
Test name
Test status
Simulation time 10120516572 ps
CPU time 81.67 seconds
Started May 05 01:16:12 PM PDT 24
Finished May 05 01:17:34 PM PDT 24
Peak memory 511812 kb
Host smart-426b2a7d-b2b3-4020-89f7-646f2d613e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741695124 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.741695124
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.528138182
Short name T721
Test name
Test status
Simulation time 1682108163 ps
CPU time 2.45 seconds
Started May 05 01:16:13 PM PDT 24
Finished May 05 01:16:16 PM PDT 24
Peak memory 203820 kb
Host smart-046e5149-36be-48e9-82c1-28db9aa9d167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528138182 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.528138182
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3417842057
Short name T1285
Test name
Test status
Simulation time 1100375852 ps
CPU time 5.44 seconds
Started May 05 01:16:10 PM PDT 24
Finished May 05 01:16:15 PM PDT 24
Peak memory 206744 kb
Host smart-f8479100-6ea0-43ff-8865-f31321af9c81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417842057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3417842057
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.788660903
Short name T1184
Test name
Test status
Simulation time 12762299237 ps
CPU time 20.5 seconds
Started May 05 01:16:10 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 505040 kb
Host smart-3e904329-a7d2-4b19-94b6-7c4c7796a8fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788660903 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.788660903
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3298767709
Short name T1162
Test name
Test status
Simulation time 2955346978 ps
CPU time 9.62 seconds
Started May 05 01:16:10 PM PDT 24
Finished May 05 01:16:20 PM PDT 24
Peak memory 203856 kb
Host smart-8d4caf3f-1915-4f03-8539-9df686cee30b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298767709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3298767709
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3542212415
Short name T1103
Test name
Test status
Simulation time 4384780702 ps
CPU time 18.29 seconds
Started May 05 01:16:11 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 213828 kb
Host smart-3ebd43c3-32d7-467e-9516-43688e116a77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542212415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3542212415
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.723372473
Short name T1128
Test name
Test status
Simulation time 10271477260 ps
CPU time 5.18 seconds
Started May 05 01:16:13 PM PDT 24
Finished May 05 01:16:19 PM PDT 24
Peak memory 203912 kb
Host smart-c7287e4f-2f74-4698-a575-8c3001c4a94d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723372473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.723372473
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2075633277
Short name T345
Test name
Test status
Simulation time 8580158063 ps
CPU time 288.62 seconds
Started May 05 01:16:09 PM PDT 24
Finished May 05 01:20:58 PM PDT 24
Peak memory 2122292 kb
Host smart-094581f7-865a-4e70-b994-a824eae171f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075633277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2075633277
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.853029899
Short name T669
Test name
Test status
Simulation time 1387200504 ps
CPU time 7.1 seconds
Started May 05 01:16:09 PM PDT 24
Finished May 05 01:16:17 PM PDT 24
Peak memory 214588 kb
Host smart-fee5bc4b-0b33-45f2-9537-d3dd53c0fbac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853029899 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.853029899
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3067078315
Short name T960
Test name
Test status
Simulation time 19794608 ps
CPU time 0.63 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:26 PM PDT 24
Peak memory 203692 kb
Host smart-64f291ad-cd27-4a61-9175-495456b1a64a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067078315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3067078315
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.565659414
Short name T1083
Test name
Test status
Simulation time 1628215125 ps
CPU time 1.36 seconds
Started May 05 01:16:23 PM PDT 24
Finished May 05 01:16:25 PM PDT 24
Peak memory 212032 kb
Host smart-018b2710-a144-482c-ab9b-d0396005fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565659414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.565659414
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.746188425
Short name T729
Test name
Test status
Simulation time 1165556471 ps
CPU time 8.21 seconds
Started May 05 01:16:15 PM PDT 24
Finished May 05 01:16:24 PM PDT 24
Peak memory 282004 kb
Host smart-fcc5de34-8e4d-4888-86eb-176f1358b74b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746188425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.746188425
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.4100440366
Short name T1320
Test name
Test status
Simulation time 4460670878 ps
CPU time 31.29 seconds
Started May 05 01:16:24 PM PDT 24
Finished May 05 01:16:56 PM PDT 24
Peak memory 480524 kb
Host smart-2b610ae6-e104-49bb-bc52-ebd75bed3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100440366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.4100440366
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2113530548
Short name T728
Test name
Test status
Simulation time 3376843276 ps
CPU time 96.35 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:18:03 PM PDT 24
Peak memory 549792 kb
Host smart-eba0a3bc-1e8c-4e00-a8ff-f84d0a260681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113530548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2113530548
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3952634194
Short name T1253
Test name
Test status
Simulation time 122209501 ps
CPU time 1.02 seconds
Started May 05 01:16:20 PM PDT 24
Finished May 05 01:16:22 PM PDT 24
Peak memory 203728 kb
Host smart-d8cf40a8-2e6a-4e63-a904-666d22965a2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952634194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3952634194
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1367688045
Short name T510
Test name
Test status
Simulation time 185732421 ps
CPU time 5.07 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 235596 kb
Host smart-951ab69b-f45c-41a2-9455-86bc4e1d0649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367688045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1367688045
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2752488563
Short name T329
Test name
Test status
Simulation time 12891326455 ps
CPU time 193.34 seconds
Started May 05 01:16:16 PM PDT 24
Finished May 05 01:19:30 PM PDT 24
Peak memory 855616 kb
Host smart-716e825c-8bd5-439c-8c85-6e822437f286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752488563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2752488563
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2721288275
Short name T1281
Test name
Test status
Simulation time 4386483285 ps
CPU time 10.54 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:16:37 PM PDT 24
Peak memory 203840 kb
Host smart-1409b9bf-8702-49fa-92fd-c5577624198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721288275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2721288275
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1255260331
Short name T39
Test name
Test status
Simulation time 10479080370 ps
CPU time 21.31 seconds
Started May 05 01:16:22 PM PDT 24
Finished May 05 01:16:43 PM PDT 24
Peak memory 308964 kb
Host smart-f8e599c6-238e-4fe4-babf-c5b61a63b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255260331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1255260331
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3479592046
Short name T1214
Test name
Test status
Simulation time 21618829 ps
CPU time 0.69 seconds
Started May 05 01:16:16 PM PDT 24
Finished May 05 01:16:17 PM PDT 24
Peak memory 203584 kb
Host smart-a964e307-3f03-4560-9d4e-3c4bc8c331ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479592046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3479592046
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1199569981
Short name T414
Test name
Test status
Simulation time 26888829888 ps
CPU time 187.35 seconds
Started May 05 01:16:21 PM PDT 24
Finished May 05 01:19:29 PM PDT 24
Peak memory 480760 kb
Host smart-7bacbcae-8a31-4b9a-863b-f4d6b09e3882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199569981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1199569981
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2243770617
Short name T1067
Test name
Test status
Simulation time 3704848932 ps
CPU time 73.03 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:17:38 PM PDT 24
Peak memory 335568 kb
Host smart-2859a35d-cc7b-477d-84e6-4dc770dfa46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243770617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2243770617
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1716563682
Short name T913
Test name
Test status
Simulation time 1340333702 ps
CPU time 11.08 seconds
Started May 05 01:16:23 PM PDT 24
Finished May 05 01:16:34 PM PDT 24
Peak memory 228456 kb
Host smart-d66ebd3d-216b-4248-b90b-4713e62154d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716563682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1716563682
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.401904977
Short name T532
Test name
Test status
Simulation time 503760422 ps
CPU time 2.64 seconds
Started May 05 01:16:24 PM PDT 24
Finished May 05 01:16:28 PM PDT 24
Peak memory 203840 kb
Host smart-cef65134-a68f-46c4-8fe5-c1c2507b5459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401904977 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.401904977
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2762763354
Short name T379
Test name
Test status
Simulation time 11091247815 ps
CPU time 5.27 seconds
Started May 05 01:16:23 PM PDT 24
Finished May 05 01:16:29 PM PDT 24
Peak memory 220140 kb
Host smart-65573016-769e-4d5f-bd30-524534858999
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762763354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2762763354
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.234852951
Short name T478
Test name
Test status
Simulation time 10061743062 ps
CPU time 30.65 seconds
Started May 05 01:16:28 PM PDT 24
Finished May 05 01:16:59 PM PDT 24
Peak memory 324468 kb
Host smart-606fccd4-04ab-45e2-b799-fcc5c605daab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234852951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.234852951
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3685515166
Short name T1051
Test name
Test status
Simulation time 2170689442 ps
CPU time 2.76 seconds
Started May 05 01:16:24 PM PDT 24
Finished May 05 01:16:28 PM PDT 24
Peak memory 203908 kb
Host smart-a9a47f0c-648d-4330-b158-3ab789aa2188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685515166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3685515166
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.608148129
Short name T367
Test name
Test status
Simulation time 8764416944 ps
CPU time 5.43 seconds
Started May 05 01:16:23 PM PDT 24
Finished May 05 01:16:28 PM PDT 24
Peak memory 213888 kb
Host smart-f98f7563-7460-48d5-8244-4a2a26081fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608148129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.608148129
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1508149159
Short name T400
Test name
Test status
Simulation time 19081257493 ps
CPU time 361.64 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:22:28 PM PDT 24
Peak memory 4499228 kb
Host smart-448dc1e3-a857-4a0b-a732-68635eb4a2ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508149159 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1508149159
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2797631330
Short name T1061
Test name
Test status
Simulation time 5639284847 ps
CPU time 17.13 seconds
Started May 05 01:16:20 PM PDT 24
Finished May 05 01:16:38 PM PDT 24
Peak memory 203716 kb
Host smart-534b1afc-360d-4e73-a168-86524cdd6bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797631330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2797631330
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.182709227
Short name T474
Test name
Test status
Simulation time 345750285 ps
CPU time 5.53 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:32 PM PDT 24
Peak memory 203888 kb
Host smart-b0e0e18b-2782-4f0e-8f39-305cd38b7bb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182709227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.182709227
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.797115137
Short name T1142
Test name
Test status
Simulation time 52240399580 ps
CPU time 477.49 seconds
Started May 05 01:16:16 PM PDT 24
Finished May 05 01:24:14 PM PDT 24
Peak memory 4133044 kb
Host smart-c8646591-367b-49e6-809d-0f850319dca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797115137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.797115137
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2845863145
Short name T339
Test name
Test status
Simulation time 40710061294 ps
CPU time 2878.03 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 02:04:24 PM PDT 24
Peak memory 9757076 kb
Host smart-be2ffd0d-1610-4bcb-9f77-9d4a1d72e544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845863145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2845863145
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3788755619
Short name T243
Test name
Test status
Simulation time 1236750646 ps
CPU time 6.32 seconds
Started May 05 01:16:23 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 203876 kb
Host smart-d45bd181-643b-4370-b205-0fe4b648819e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788755619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3788755619
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3441149797
Short name T742
Test name
Test status
Simulation time 17971132 ps
CPU time 0.6 seconds
Started May 05 01:16:40 PM PDT 24
Finished May 05 01:16:41 PM PDT 24
Peak memory 203728 kb
Host smart-08ae5bd1-c15c-4633-bf3d-064baa96f595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441149797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3441149797
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1400315178
Short name T599
Test name
Test status
Simulation time 286202999 ps
CPU time 1.47 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:27 PM PDT 24
Peak memory 212224 kb
Host smart-2e6f4b09-aa42-4cae-82f3-8d177af39aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400315178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1400315178
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2936250279
Short name T807
Test name
Test status
Simulation time 354664918 ps
CPU time 7.47 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:16:34 PM PDT 24
Peak memory 271604 kb
Host smart-b19d346e-bbd1-42dc-b40b-d8388c4fff2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936250279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2936250279
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.710096721
Short name T1275
Test name
Test status
Simulation time 3585996803 ps
CPU time 76.82 seconds
Started May 05 01:16:27 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 720628 kb
Host smart-b3038078-ead6-406a-861a-9774c2727c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710096721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.710096721
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.957785176
Short name T899
Test name
Test status
Simulation time 6168508251 ps
CPU time 52.12 seconds
Started May 05 01:16:24 PM PDT 24
Finished May 05 01:17:16 PM PDT 24
Peak memory 588992 kb
Host smart-d649c87c-dd47-4879-8b80-224c3a60958f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957785176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.957785176
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2479710878
Short name T867
Test name
Test status
Simulation time 126458122 ps
CPU time 0.88 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:26 PM PDT 24
Peak memory 203724 kb
Host smart-e49645c8-3fed-4eb6-9bda-e29254e3482a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479710878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2479710878
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.499885207
Short name T1183
Test name
Test status
Simulation time 134578682 ps
CPU time 6.42 seconds
Started May 05 01:16:32 PM PDT 24
Finished May 05 01:16:39 PM PDT 24
Peak memory 220980 kb
Host smart-23802087-a2b2-402f-aee5-17a53d5cbeda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499885207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
499885207
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.608625345
Short name T270
Test name
Test status
Simulation time 4802255756 ps
CPU time 315.49 seconds
Started May 05 01:16:27 PM PDT 24
Finished May 05 01:21:44 PM PDT 24
Peak memory 1205304 kb
Host smart-6d8306a7-e788-41b2-9af2-1adebacb7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608625345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.608625345
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.4257791503
Short name T1336
Test name
Test status
Simulation time 881083255 ps
CPU time 6.64 seconds
Started May 05 01:16:32 PM PDT 24
Finished May 05 01:16:39 PM PDT 24
Peak memory 203836 kb
Host smart-37acc274-6343-4960-ad88-560bf28dd8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257791503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.4257791503
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.957572249
Short name T1018
Test name
Test status
Simulation time 6790071886 ps
CPU time 31.61 seconds
Started May 05 01:16:33 PM PDT 24
Finished May 05 01:17:05 PM PDT 24
Peak memory 317552 kb
Host smart-6d015e30-fa92-458e-bf03-6c90cb3ec514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957572249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.957572249
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1604825484
Short name T932
Test name
Test status
Simulation time 39543638 ps
CPU time 0.63 seconds
Started May 05 01:16:24 PM PDT 24
Finished May 05 01:16:26 PM PDT 24
Peak memory 203664 kb
Host smart-442e216a-e108-4f85-bcc6-6b15c128cb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604825484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1604825484
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.303962957
Short name T63
Test name
Test status
Simulation time 2903869956 ps
CPU time 16.3 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 212348 kb
Host smart-92b503c0-81bc-4874-8b38-b4743adb66a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303962957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.303962957
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3964013801
Short name T858
Test name
Test status
Simulation time 4454306380 ps
CPU time 16.77 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:16:43 PM PDT 24
Peak memory 280988 kb
Host smart-4ac83d87-0154-4631-848d-33f3c3171bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964013801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3964013801
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2910861843
Short name T1255
Test name
Test status
Simulation time 34872872681 ps
CPU time 330.95 seconds
Started May 05 01:16:26 PM PDT 24
Finished May 05 01:21:57 PM PDT 24
Peak memory 1834996 kb
Host smart-c5462fe9-9155-4206-8007-1eaeb5cfb35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910861843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2910861843
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.445041980
Short name T814
Test name
Test status
Simulation time 1027814759 ps
CPU time 20.9 seconds
Started May 05 01:16:27 PM PDT 24
Finished May 05 01:16:49 PM PDT 24
Peak memory 212000 kb
Host smart-f0bcd6f4-c978-48fb-863b-7b97a48c767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445041980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.445041980
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.745131663
Short name T1154
Test name
Test status
Simulation time 1329727552 ps
CPU time 3.54 seconds
Started May 05 01:16:38 PM PDT 24
Finished May 05 01:16:43 PM PDT 24
Peak memory 203856 kb
Host smart-c53e3a2b-31b1-4c2a-a04e-3f31f1f193cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745131663 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.745131663
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3679334067
Short name T566
Test name
Test status
Simulation time 10204429793 ps
CPU time 13.35 seconds
Started May 05 01:16:30 PM PDT 24
Finished May 05 01:16:44 PM PDT 24
Peak memory 260672 kb
Host smart-7663eb29-db5e-4ed3-9db5-1974d7e68a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679334067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3679334067
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3849711027
Short name T679
Test name
Test status
Simulation time 10024929341 ps
CPU time 79.45 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:17:49 PM PDT 24
Peak memory 557224 kb
Host smart-1ac5b99a-6022-4815-a282-a12d21c2828c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849711027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3849711027
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2832524250
Short name T1016
Test name
Test status
Simulation time 589675603 ps
CPU time 3.12 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 203800 kb
Host smart-02aa4130-7994-4f84-a48d-502e1e2e53cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832524250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2832524250
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1649697391
Short name T933
Test name
Test status
Simulation time 4382634181 ps
CPU time 4.02 seconds
Started May 05 01:16:27 PM PDT 24
Finished May 05 01:16:31 PM PDT 24
Peak memory 204172 kb
Host smart-5ff61854-8d81-426a-922b-b663ae2eeb55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649697391 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1649697391
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1037841859
Short name T5
Test name
Test status
Simulation time 11775797976 ps
CPU time 23.72 seconds
Started May 05 01:16:30 PM PDT 24
Finished May 05 01:16:55 PM PDT 24
Peak memory 740760 kb
Host smart-ba384ecd-ef08-41b5-bddd-85f6ef0e8eb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037841859 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1037841859
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3258607829
Short name T413
Test name
Test status
Simulation time 4564448447 ps
CPU time 18.4 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:16:44 PM PDT 24
Peak memory 203800 kb
Host smart-9d4bfb67-0172-43f3-b5db-ef56a085902a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258607829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3258607829
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2036113151
Short name T1310
Test name
Test status
Simulation time 695613921 ps
CPU time 10.75 seconds
Started May 05 01:16:32 PM PDT 24
Finished May 05 01:16:43 PM PDT 24
Peak memory 211448 kb
Host smart-a652e322-7c0d-4b8a-94a3-4d394da7d540
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036113151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2036113151
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2983399669
Short name T1315
Test name
Test status
Simulation time 34971174858 ps
CPU time 143.18 seconds
Started May 05 01:16:31 PM PDT 24
Finished May 05 01:18:55 PM PDT 24
Peak memory 1982028 kb
Host smart-992588cf-fa18-46ec-b7b6-199d147a1f33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983399669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2983399669
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.701677060
Short name T600
Test name
Test status
Simulation time 8328734843 ps
CPU time 294.75 seconds
Started May 05 01:16:25 PM PDT 24
Finished May 05 01:21:21 PM PDT 24
Peak memory 2159152 kb
Host smart-e2be446b-d6cd-4683-9e18-10d3dbac4759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701677060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.701677060
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3787117007
Short name T500
Test name
Test status
Simulation time 1633571641 ps
CPU time 7.74 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:16:38 PM PDT 24
Peak memory 216412 kb
Host smart-e976492c-6f3f-46db-9ac4-8bfb46efc7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787117007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3787117007
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.3209795721
Short name T221
Test name
Test status
Simulation time 4052352821 ps
CPU time 5.76 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:16:36 PM PDT 24
Peak memory 207420 kb
Host smart-c7cabc97-1874-4d76-9185-3ff576a36b2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209795721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.3209795721
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3014518721
Short name T665
Test name
Test status
Simulation time 15499679 ps
CPU time 0.6 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:40 PM PDT 24
Peak memory 203728 kb
Host smart-9c7f0e3f-b964-4005-9388-e98f0da6fd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014518721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3014518721
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2356886267
Short name T462
Test name
Test status
Simulation time 89967582 ps
CPU time 1.22 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:16:37 PM PDT 24
Peak memory 212160 kb
Host smart-ce17c423-bd10-4022-a0e7-7058120e1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356886267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2356886267
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.472805051
Short name T757
Test name
Test status
Simulation time 257427511 ps
CPU time 13.17 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:52 PM PDT 24
Peak memory 257776 kb
Host smart-53fa812b-366d-462e-aac1-6d11008841f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472805051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.472805051
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3813628785
Short name T66
Test name
Test status
Simulation time 10716981558 ps
CPU time 74.55 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 713424 kb
Host smart-53f56e61-dc86-42ec-adeb-97500965de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813628785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3813628785
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3558600071
Short name T625
Test name
Test status
Simulation time 6010367761 ps
CPU time 45.25 seconds
Started May 05 01:16:30 PM PDT 24
Finished May 05 01:17:16 PM PDT 24
Peak memory 590840 kb
Host smart-1f5678e9-76a1-4d3f-a308-ba5a454a3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558600071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3558600071
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3597794382
Short name T515
Test name
Test status
Simulation time 264725773 ps
CPU time 1.08 seconds
Started May 05 01:16:30 PM PDT 24
Finished May 05 01:16:32 PM PDT 24
Peak memory 203760 kb
Host smart-66fc2abb-39f2-462f-8c90-4b4e448771ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597794382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3597794382
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3362841913
Short name T935
Test name
Test status
Simulation time 125956418 ps
CPU time 6.83 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:16:36 PM PDT 24
Peak memory 224068 kb
Host smart-708ee999-909d-4b86-ae07-d9912766145a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362841913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3362841913
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1648761803
Short name T181
Test name
Test status
Simulation time 2525157023 ps
CPU time 54.88 seconds
Started May 05 01:16:32 PM PDT 24
Finished May 05 01:17:27 PM PDT 24
Peak memory 831020 kb
Host smart-4391e4cc-dce2-4e8d-89c1-4b2481422ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648761803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1648761803
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1659787168
Short name T1327
Test name
Test status
Simulation time 1028360092 ps
CPU time 7.82 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:47 PM PDT 24
Peak memory 203884 kb
Host smart-cd3261be-1916-48ac-9b5a-dc45f8cbb62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659787168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1659787168
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.4161272603
Short name T33
Test name
Test status
Simulation time 16232892512 ps
CPU time 34.1 seconds
Started May 05 01:16:41 PM PDT 24
Finished May 05 01:17:16 PM PDT 24
Peak memory 375808 kb
Host smart-80390a17-45d7-49d1-a04a-5310b1236839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161272603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4161272603
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.4178502202
Short name T45
Test name
Test status
Simulation time 40369340 ps
CPU time 0.61 seconds
Started May 05 01:16:29 PM PDT 24
Finished May 05 01:16:30 PM PDT 24
Peak memory 203636 kb
Host smart-268d8a3d-7b69-46d2-baa8-4f847709fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178502202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4178502202
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.4204831888
Short name T942
Test name
Test status
Simulation time 7319892599 ps
CPU time 56.72 seconds
Started May 05 01:16:34 PM PDT 24
Finished May 05 01:17:31 PM PDT 24
Peak memory 226768 kb
Host smart-faa8cf2f-9252-416f-8a9c-774f36268dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204831888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4204831888
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1127736567
Short name T790
Test name
Test status
Simulation time 6300938408 ps
CPU time 17.93 seconds
Started May 05 01:16:28 PM PDT 24
Finished May 05 01:16:47 PM PDT 24
Peak memory 312836 kb
Host smart-a31fad81-5db5-419f-9022-c79101953cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127736567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1127736567
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.276645616
Short name T583
Test name
Test status
Simulation time 107432476758 ps
CPU time 1724.56 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:45:20 PM PDT 24
Peak memory 1678292 kb
Host smart-1994c9a4-0837-4f9f-af94-2fddffb7817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276645616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.276645616
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3865138366
Short name T708
Test name
Test status
Simulation time 2287511815 ps
CPU time 14.65 seconds
Started May 05 01:16:36 PM PDT 24
Finished May 05 01:16:51 PM PDT 24
Peak memory 212104 kb
Host smart-579afb4e-0e45-4e5c-9803-76755054cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865138366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3865138366
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.168104887
Short name T446
Test name
Test status
Simulation time 1652962991 ps
CPU time 3.85 seconds
Started May 05 01:16:37 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 203816 kb
Host smart-dd16b5db-8442-452c-96d6-f214123b334f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168104887 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.168104887
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1232138753
Short name T595
Test name
Test status
Simulation time 10282595196 ps
CPU time 14.04 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:53 PM PDT 24
Peak memory 280984 kb
Host smart-e2cc9987-6e26-4a3f-bea3-618145efd99b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232138753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1232138753
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3831343274
Short name T496
Test name
Test status
Simulation time 10209026223 ps
CPU time 13.01 seconds
Started May 05 01:16:41 PM PDT 24
Finished May 05 01:16:54 PM PDT 24
Peak memory 259388 kb
Host smart-de9ceb34-e245-4418-81fd-2fb8d8bf46f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831343274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3831343274
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2530450678
Short name T218
Test name
Test status
Simulation time 487640028 ps
CPU time 2.62 seconds
Started May 05 01:16:38 PM PDT 24
Finished May 05 01:16:41 PM PDT 24
Peak memory 203784 kb
Host smart-5dec9315-3899-4795-98e5-634c5d965df3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530450678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2530450678
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3985029798
Short name T1116
Test name
Test status
Simulation time 976832715 ps
CPU time 5.27 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:16:41 PM PDT 24
Peak memory 203812 kb
Host smart-560fc4dd-31c2-479d-a476-16b5b331ac75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985029798 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3985029798
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2467818145
Short name T360
Test name
Test status
Simulation time 14357973589 ps
CPU time 35.15 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:17:11 PM PDT 24
Peak memory 941168 kb
Host smart-84bdbc3c-dd0c-4e2f-a972-f0187a3a84de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467818145 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2467818145
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2327787377
Short name T970
Test name
Test status
Simulation time 9724736897 ps
CPU time 15.29 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:16:51 PM PDT 24
Peak memory 203872 kb
Host smart-b219cf45-aaef-4a44-a164-4880ce36cbd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327787377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2327787377
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1893995789
Short name T301
Test name
Test status
Simulation time 2592500691 ps
CPU time 16.46 seconds
Started May 05 01:16:34 PM PDT 24
Finished May 05 01:16:51 PM PDT 24
Peak memory 219232 kb
Host smart-f1afca6a-2bba-493d-a281-f0cfc02e2567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893995789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1893995789
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3256278135
Short name T616
Test name
Test status
Simulation time 26055097360 ps
CPU time 118.61 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:18:34 PM PDT 24
Peak memory 1688816 kb
Host smart-328442a8-3a64-4b9d-813b-3f179795e168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256278135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3256278135
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.366684985
Short name T433
Test name
Test status
Simulation time 10815715254 ps
CPU time 1236.46 seconds
Started May 05 01:16:35 PM PDT 24
Finished May 05 01:37:12 PM PDT 24
Peak memory 2722332 kb
Host smart-01f8d754-542a-4ac1-b581-a8cac2d3ff5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366684985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.366684985
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3056329776
Short name T497
Test name
Test status
Simulation time 2090142047 ps
CPU time 6.14 seconds
Started May 05 01:16:36 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 203864 kb
Host smart-dc8ba497-f089-409c-91ca-dd9378514db1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056329776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3056329776
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.852708486
Short name T1024
Test name
Test status
Simulation time 1113227930 ps
CPU time 5.62 seconds
Started May 05 01:16:36 PM PDT 24
Finished May 05 01:16:42 PM PDT 24
Peak memory 209236 kb
Host smart-4f94dabe-531c-47bb-9d16-22bfe1e3c44d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852708486 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_unexp_stop.852708486
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2034986021
Short name T845
Test name
Test status
Simulation time 21279855 ps
CPU time 0.59 seconds
Started May 05 01:16:57 PM PDT 24
Finished May 05 01:16:58 PM PDT 24
Peak memory 203748 kb
Host smart-f44f0758-ce6e-429e-8342-f22270012442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034986021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2034986021
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3640453563
Short name T309
Test name
Test status
Simulation time 144193375 ps
CPU time 1.62 seconds
Started May 05 01:16:44 PM PDT 24
Finished May 05 01:16:46 PM PDT 24
Peak memory 212176 kb
Host smart-c69d8464-211c-4f4f-b8bd-3605c6420b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640453563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3640453563
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2057881007
Short name T1048
Test name
Test status
Simulation time 176312124 ps
CPU time 9.12 seconds
Started May 05 01:16:45 PM PDT 24
Finished May 05 01:16:55 PM PDT 24
Peak memory 237076 kb
Host smart-04194388-68d2-4108-8907-863da06bdeab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057881007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2057881007
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3839249426
Short name T1091
Test name
Test status
Simulation time 1976541882 ps
CPU time 65.23 seconds
Started May 05 01:16:42 PM PDT 24
Finished May 05 01:17:48 PM PDT 24
Peak memory 673876 kb
Host smart-5a2886c8-28d4-461f-a2a4-37c0ccbab1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839249426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3839249426
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2669168725
Short name T505
Test name
Test status
Simulation time 8455652795 ps
CPU time 71.67 seconds
Started May 05 01:16:41 PM PDT 24
Finished May 05 01:17:53 PM PDT 24
Peak memory 710980 kb
Host smart-96edd735-1218-4db2-8403-a021363ab8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669168725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2669168725
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3213397184
Short name T124
Test name
Test status
Simulation time 84088429 ps
CPU time 0.82 seconds
Started May 05 01:16:43 PM PDT 24
Finished May 05 01:16:44 PM PDT 24
Peak memory 203600 kb
Host smart-df933c34-127b-4a66-99a3-eb33057b5b9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213397184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3213397184
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1603293803
Short name T576
Test name
Test status
Simulation time 425237978 ps
CPU time 2.91 seconds
Started May 05 01:16:44 PM PDT 24
Finished May 05 01:16:47 PM PDT 24
Peak memory 203856 kb
Host smart-6755da4a-8bef-4321-b7d7-4e53ae11b297
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603293803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1603293803
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.616003811
Short name T1294
Test name
Test status
Simulation time 5313428434 ps
CPU time 155.01 seconds
Started May 05 01:16:41 PM PDT 24
Finished May 05 01:19:17 PM PDT 24
Peak memory 723432 kb
Host smart-0485e80b-219e-4104-8d40-233a7a47d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616003811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.616003811
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3186146670
Short name T591
Test name
Test status
Simulation time 317452273 ps
CPU time 12.5 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:17:06 PM PDT 24
Peak memory 203832 kb
Host smart-8d30fdbc-7c8b-4f82-9b14-127a4c9d3cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186146670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3186146670
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1519716133
Short name T449
Test name
Test status
Simulation time 5178766575 ps
CPU time 55.83 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:17:50 PM PDT 24
Peak memory 251084 kb
Host smart-4df32585-cf42-49f3-9301-cdea1bbcecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519716133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1519716133
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3052772344
Short name T1082
Test name
Test status
Simulation time 43003629 ps
CPU time 0.63 seconds
Started May 05 01:16:39 PM PDT 24
Finished May 05 01:16:40 PM PDT 24
Peak memory 203636 kb
Host smart-8a59be5f-bd44-4edc-8f71-9223ef0a8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052772344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3052772344
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3179779582
Short name T328
Test name
Test status
Simulation time 2752461855 ps
CPU time 32.14 seconds
Started May 05 01:16:45 PM PDT 24
Finished May 05 01:17:18 PM PDT 24
Peak memory 509592 kb
Host smart-80cb24fb-eece-4e7e-aedf-97668b215ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179779582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3179779582
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2929845337
Short name T353
Test name
Test status
Simulation time 1455498943 ps
CPU time 72.55 seconds
Started May 05 01:16:41 PM PDT 24
Finished May 05 01:17:54 PM PDT 24
Peak memory 352988 kb
Host smart-a2765e46-0b9e-4272-81f9-40ab4580d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929845337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2929845337
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1369007584
Short name T650
Test name
Test status
Simulation time 33652230893 ps
CPU time 358.11 seconds
Started May 05 01:16:46 PM PDT 24
Finished May 05 01:22:45 PM PDT 24
Peak memory 1729940 kb
Host smart-57f88877-b1c8-466b-9102-1e06764ba8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369007584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1369007584
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2086986982
Short name T1200
Test name
Test status
Simulation time 551598513 ps
CPU time 10.05 seconds
Started May 05 01:16:46 PM PDT 24
Finished May 05 01:16:56 PM PDT 24
Peak memory 212072 kb
Host smart-a71844ff-5d21-4a52-bd5c-20e652069e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086986982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2086986982
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1589310754
Short name T268
Test name
Test status
Simulation time 1352231576 ps
CPU time 3.55 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:16:58 PM PDT 24
Peak memory 203824 kb
Host smart-11c49fde-178b-4fd2-84a8-98776fb71078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589310754 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1589310754
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.114703790
Short name T1316
Test name
Test status
Simulation time 10085914745 ps
CPU time 57.89 seconds
Started May 05 01:16:50 PM PDT 24
Finished May 05 01:17:48 PM PDT 24
Peak memory 419192 kb
Host smart-1565f908-ea7f-432d-b3c9-adfae129291a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114703790 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.114703790
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1635197617
Short name T640
Test name
Test status
Simulation time 10318152279 ps
CPU time 9.3 seconds
Started May 05 01:16:49 PM PDT 24
Finished May 05 01:16:59 PM PDT 24
Peak memory 251964 kb
Host smart-61346efb-56f3-49eb-b63a-9b91a66d87e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635197617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1635197617
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3917645639
Short name T660
Test name
Test status
Simulation time 462804719 ps
CPU time 2.71 seconds
Started May 05 01:16:47 PM PDT 24
Finished May 05 01:16:51 PM PDT 24
Peak memory 203804 kb
Host smart-65873799-04fd-457a-9931-7bf2311b910c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917645639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3917645639
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2060545951
Short name T815
Test name
Test status
Simulation time 5461979500 ps
CPU time 4.92 seconds
Started May 05 01:16:45 PM PDT 24
Finished May 05 01:16:50 PM PDT 24
Peak memory 204396 kb
Host smart-b619c54f-cb48-4a06-9393-b9911bc5c27c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060545951 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2060545951
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3918901469
Short name T372
Test name
Test status
Simulation time 15375127304 ps
CPU time 146.73 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:19:20 PM PDT 24
Peak memory 1993336 kb
Host smart-c26daec4-b4e7-4bb2-bd96-e10d3f488896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918901469 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3918901469
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.256344222
Short name T1013
Test name
Test status
Simulation time 2345025241 ps
CPU time 23.12 seconds
Started May 05 01:16:43 PM PDT 24
Finished May 05 01:17:07 PM PDT 24
Peak memory 203816 kb
Host smart-2d786c4b-f06d-4244-b499-4ce5ad874582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256344222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.256344222
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1173526364
Short name T1348
Test name
Test status
Simulation time 4711520863 ps
CPU time 18.17 seconds
Started May 05 01:16:44 PM PDT 24
Finished May 05 01:17:03 PM PDT 24
Peak memory 222316 kb
Host smart-be96afa3-8760-4535-ba77-2daa442dc288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173526364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1173526364
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.673374407
Short name T864
Test name
Test status
Simulation time 45952470179 ps
CPU time 15.54 seconds
Started May 05 01:16:45 PM PDT 24
Finished May 05 01:17:00 PM PDT 24
Peak memory 443676 kb
Host smart-514974ad-8419-4717-932d-3646e42ae635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673374407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.673374407
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3972293538
Short name T30
Test name
Test status
Simulation time 8790754668 ps
CPU time 690.34 seconds
Started May 05 01:16:45 PM PDT 24
Finished May 05 01:28:16 PM PDT 24
Peak memory 2079876 kb
Host smart-e9ee0aea-cd02-4f63-8856-19ae01f01d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972293538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3972293538
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3904651916
Short name T1168
Test name
Test status
Simulation time 3224226475 ps
CPU time 7.58 seconds
Started May 05 01:16:49 PM PDT 24
Finished May 05 01:16:57 PM PDT 24
Peak memory 214612 kb
Host smart-bcaf9911-9826-4bb3-9921-06aac0971915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904651916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3904651916
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.4191688209
Short name T853
Test name
Test status
Simulation time 35103394 ps
CPU time 0.61 seconds
Started May 05 01:17:01 PM PDT 24
Finished May 05 01:17:02 PM PDT 24
Peak memory 203748 kb
Host smart-1885e7e7-011c-49d9-a8b3-1ac55cb7aebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191688209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.4191688209
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3242275871
Short name T1250
Test name
Test status
Simulation time 758913232 ps
CPU time 1.53 seconds
Started May 05 01:16:55 PM PDT 24
Finished May 05 01:16:57 PM PDT 24
Peak memory 212176 kb
Host smart-2410e94b-853d-404c-bf99-c794f25c4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242275871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3242275871
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3701647024
Short name T1132
Test name
Test status
Simulation time 285169446 ps
CPU time 5.87 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:16:59 PM PDT 24
Peak memory 253296 kb
Host smart-73246e5b-dafa-4fd4-9190-972372bf6aaa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701647024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3701647024
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2726989640
Short name T809
Test name
Test status
Simulation time 4978827259 ps
CPU time 45.48 seconds
Started May 05 01:16:54 PM PDT 24
Finished May 05 01:17:40 PM PDT 24
Peak memory 586984 kb
Host smart-b52fa158-9d5f-4e58-9319-532f2ef9bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726989640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2726989640
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3086029974
Short name T1023
Test name
Test status
Simulation time 1125494988 ps
CPU time 73.09 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:18:07 PM PDT 24
Peak memory 480120 kb
Host smart-f3f19075-c7c8-4bf1-bd13-bfce7a8ac80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086029974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3086029974
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3610427952
Short name T580
Test name
Test status
Simulation time 731023847 ps
CPU time 0.93 seconds
Started May 05 01:16:51 PM PDT 24
Finished May 05 01:16:53 PM PDT 24
Peak memory 203720 kb
Host smart-c0b40fd3-11fc-4c39-8687-e543ea231716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610427952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3610427952
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.399784953
Short name T654
Test name
Test status
Simulation time 135615700 ps
CPU time 3.99 seconds
Started May 05 01:16:55 PM PDT 24
Finished May 05 01:16:59 PM PDT 24
Peak memory 225288 kb
Host smart-ae85ba04-38b2-4acb-a918-80478e9696f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399784953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
399784953
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2092383106
Short name T1358
Test name
Test status
Simulation time 53249087138 ps
CPU time 105.39 seconds
Started May 05 01:16:55 PM PDT 24
Finished May 05 01:18:41 PM PDT 24
Peak memory 1028164 kb
Host smart-8015dce5-7606-4f8c-8b9f-f99a8d64ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092383106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2092383106
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.4228526212
Short name T442
Test name
Test status
Simulation time 1882059865 ps
CPU time 7.51 seconds
Started May 05 01:17:01 PM PDT 24
Finished May 05 01:17:09 PM PDT 24
Peak memory 203880 kb
Host smart-7d35ed7b-fd4a-4b45-a034-26698d3858b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228526212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.4228526212
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3797502431
Short name T560
Test name
Test status
Simulation time 3912546283 ps
CPU time 44.54 seconds
Started May 05 01:16:59 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 311656 kb
Host smart-5ff7252c-b48f-4b93-ba3f-468c8892b196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797502431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3797502431
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3524107361
Short name T1268
Test name
Test status
Simulation time 44328226 ps
CPU time 0.65 seconds
Started May 05 01:16:54 PM PDT 24
Finished May 05 01:16:55 PM PDT 24
Peak memory 203664 kb
Host smart-139ef662-28d3-448c-b08a-b908a6ef9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524107361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3524107361
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.589682886
Short name T984
Test name
Test status
Simulation time 6303429322 ps
CPU time 205.36 seconds
Started May 05 01:16:55 PM PDT 24
Finished May 05 01:20:21 PM PDT 24
Peak memory 822284 kb
Host smart-42184fc1-281a-4b9a-ad44-3cdade08fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589682886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.589682886
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1407420029
Short name T1106
Test name
Test status
Simulation time 5765209588 ps
CPU time 63.69 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:17:58 PM PDT 24
Peak memory 317200 kb
Host smart-afdbb6c6-41f9-4780-9637-e3e79581feb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407420029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1407420029
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1719083018
Short name T250
Test name
Test status
Simulation time 17928480400 ps
CPU time 247.75 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:21:02 PM PDT 24
Peak memory 615068 kb
Host smart-e3ccd9ba-4434-4304-808a-1780a7a42918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719083018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1719083018
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4194323735
Short name T232
Test name
Test status
Simulation time 2840990373 ps
CPU time 31.49 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:17:26 PM PDT 24
Peak memory 212124 kb
Host smart-e82f2503-accc-4a7b-bb89-92b95ab3f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194323735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4194323735
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1662172233
Short name T523
Test name
Test status
Simulation time 1418649011 ps
CPU time 3.92 seconds
Started May 05 01:16:59 PM PDT 24
Finished May 05 01:17:03 PM PDT 24
Peak memory 203800 kb
Host smart-81947b4f-2d2f-4bb6-8fbb-971928e2c89b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662172233 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1662172233
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2501185641
Short name T54
Test name
Test status
Simulation time 10096892005 ps
CPU time 69.87 seconds
Started May 05 01:16:58 PM PDT 24
Finished May 05 01:18:09 PM PDT 24
Peak memory 511060 kb
Host smart-1d023812-f2ef-4f1f-99b3-4eb0b7cd6b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501185641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2501185641
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1114013046
Short name T88
Test name
Test status
Simulation time 10158247155 ps
CPU time 85.49 seconds
Started May 05 01:16:58 PM PDT 24
Finished May 05 01:18:24 PM PDT 24
Peak memory 594412 kb
Host smart-dc330e00-c8e8-4903-8768-7884315aadd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114013046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1114013046
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.505479524
Short name T582
Test name
Test status
Simulation time 370112157 ps
CPU time 2.46 seconds
Started May 05 01:17:06 PM PDT 24
Finished May 05 01:17:09 PM PDT 24
Peak memory 203824 kb
Host smart-29daf233-b7f4-4912-88d2-e9ecb890f74e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505479524 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.505479524
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.4026371692
Short name T1055
Test name
Test status
Simulation time 687381015 ps
CPU time 3.99 seconds
Started May 05 01:16:59 PM PDT 24
Finished May 05 01:17:03 PM PDT 24
Peak memory 203828 kb
Host smart-ca9bd400-c738-4c8e-adf0-9368af5343b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026371692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.4026371692
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.859701224
Short name T1360
Test name
Test status
Simulation time 26056332316 ps
CPU time 543.37 seconds
Started May 05 01:16:59 PM PDT 24
Finished May 05 01:26:03 PM PDT 24
Peak memory 6349008 kb
Host smart-cea0c4f3-e9a9-459e-94c4-5505fc140862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859701224 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.859701224
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2461792588
Short name T507
Test name
Test status
Simulation time 3309353316 ps
CPU time 18.53 seconds
Started May 05 01:16:58 PM PDT 24
Finished May 05 01:17:17 PM PDT 24
Peak memory 203952 kb
Host smart-14aaf329-6ff2-4a8a-af14-9390475f1dc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461792588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2461792588
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.4227153592
Short name T868
Test name
Test status
Simulation time 746342210 ps
CPU time 14.24 seconds
Started May 05 01:16:57 PM PDT 24
Finished May 05 01:17:11 PM PDT 24
Peak memory 203876 kb
Host smart-036aee8a-dd62-45f2-a592-2d54c797ff3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227153592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.4227153592
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3935289611
Short name T633
Test name
Test status
Simulation time 35097901376 ps
CPU time 458.87 seconds
Started May 05 01:16:53 PM PDT 24
Finished May 05 01:24:33 PM PDT 24
Peak memory 3907312 kb
Host smart-07e8aa48-8d17-4e9f-b4aa-2b5b50548631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935289611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3935289611
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3079432740
Short name T800
Test name
Test status
Simulation time 3196324741 ps
CPU time 7.49 seconds
Started May 05 01:17:06 PM PDT 24
Finished May 05 01:17:14 PM PDT 24
Peak memory 214380 kb
Host smart-c2783938-4117-4b2f-ac81-073fee6c8cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079432740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3079432740
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.3456776057
Short name T217
Test name
Test status
Simulation time 1069840468 ps
CPU time 6.97 seconds
Started May 05 01:16:58 PM PDT 24
Finished May 05 01:17:06 PM PDT 24
Peak memory 203780 kb
Host smart-e1810322-fee1-4cbf-9879-f2307a6afa5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456776057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.3456776057
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.4214960559
Short name T1104
Test name
Test status
Simulation time 16569665 ps
CPU time 0.62 seconds
Started May 05 01:17:08 PM PDT 24
Finished May 05 01:17:09 PM PDT 24
Peak memory 203736 kb
Host smart-022a85f2-5975-40c5-9423-0b8f837067ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214960559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.4214960559
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1140534880
Short name T1340
Test name
Test status
Simulation time 79588608 ps
CPU time 1.37 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:17:05 PM PDT 24
Peak memory 212136 kb
Host smart-fbedb9c8-f16b-4836-9ff6-baf162f05deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140534880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1140534880
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1108487534
Short name T1066
Test name
Test status
Simulation time 394630683 ps
CPU time 9.62 seconds
Started May 05 01:17:03 PM PDT 24
Finished May 05 01:17:13 PM PDT 24
Peak memory 227504 kb
Host smart-1c208aa1-c29a-4629-a900-3c3595ed2ada
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108487534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1108487534
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3594753079
Short name T354
Test name
Test status
Simulation time 11572116327 ps
CPU time 75.04 seconds
Started May 05 01:17:03 PM PDT 24
Finished May 05 01:18:18 PM PDT 24
Peak memory 696856 kb
Host smart-440f24cd-e7a6-4988-b6ad-d9e9d7de480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594753079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3594753079
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3701435347
Short name T1157
Test name
Test status
Simulation time 1697842778 ps
CPU time 125.64 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:19:10 PM PDT 24
Peak memory 622820 kb
Host smart-8db5eec1-a227-4b27-a275-949d18e1df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701435347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3701435347
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3468518386
Short name T459
Test name
Test status
Simulation time 773205261 ps
CPU time 10.43 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:17:15 PM PDT 24
Peak memory 239756 kb
Host smart-846933d1-1303-4588-bbfa-3c76c219e198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468518386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3468518386
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3829174075
Short name T1036
Test name
Test status
Simulation time 9438708766 ps
CPU time 107.86 seconds
Started May 05 01:17:05 PM PDT 24
Finished May 05 01:18:53 PM PDT 24
Peak memory 1194016 kb
Host smart-391e9a00-1f15-4402-89b0-cdd137a334a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829174075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3829174075
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2352209769
Short name T225
Test name
Test status
Simulation time 167516210 ps
CPU time 5.93 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:16 PM PDT 24
Peak memory 203640 kb
Host smart-eb27db11-0db1-4c82-bdcf-3e61180c6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352209769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2352209769
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1016701280
Short name T4
Test name
Test status
Simulation time 7141629012 ps
CPU time 63.53 seconds
Started May 05 01:17:08 PM PDT 24
Finished May 05 01:18:12 PM PDT 24
Peak memory 341984 kb
Host smart-95df8000-c88d-4aa8-b7d2-7cdbc866c755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016701280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1016701280
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3638650777
Short name T298
Test name
Test status
Simulation time 188639413 ps
CPU time 0.66 seconds
Started May 05 01:17:03 PM PDT 24
Finished May 05 01:17:05 PM PDT 24
Peak memory 203624 kb
Host smart-7d308a63-20bf-48d9-b00a-6542f9c6e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638650777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3638650777
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1956331775
Short name T907
Test name
Test status
Simulation time 47585336173 ps
CPU time 116.77 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:19:01 PM PDT 24
Peak memory 203908 kb
Host smart-4cbc6921-0e2b-4cd9-b8a0-76ca13949cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956331775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1956331775
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1504373557
Short name T427
Test name
Test status
Simulation time 4609651397 ps
CPU time 59.11 seconds
Started May 05 01:17:03 PM PDT 24
Finished May 05 01:18:02 PM PDT 24
Peak memory 344944 kb
Host smart-7eaf2131-090b-4183-a7a4-3c84f8dc2dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504373557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1504373557
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3582394574
Short name T1029
Test name
Test status
Simulation time 1024770782 ps
CPU time 22.67 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:17:27 PM PDT 24
Peak memory 211984 kb
Host smart-734bd285-8755-4981-b75e-20d271c202c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582394574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3582394574
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1951886263
Short name T23
Test name
Test status
Simulation time 1017572931 ps
CPU time 3.4 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:13 PM PDT 24
Peak memory 211908 kb
Host smart-9db9168a-1972-4758-8764-1de9c1fe6dbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951886263 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1951886263
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1136476292
Short name T707
Test name
Test status
Simulation time 10224726387 ps
CPU time 11.59 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:21 PM PDT 24
Peak memory 271608 kb
Host smart-678b156a-c023-4448-a216-f4cd43267dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136476292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1136476292
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2720556734
Short name T387
Test name
Test status
Simulation time 10255829664 ps
CPU time 24.47 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:34 PM PDT 24
Peak memory 335196 kb
Host smart-48b9ea1d-49ec-49e2-bf72-a1adc575f7f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720556734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2720556734
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1585338012
Short name T397
Test name
Test status
Simulation time 790313621 ps
CPU time 2.66 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:12 PM PDT 24
Peak memory 203872 kb
Host smart-74736e25-a334-4493-8e26-97edb0621504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585338012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1585338012
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3701260893
Short name T1031
Test name
Test status
Simulation time 1087810795 ps
CPU time 6.09 seconds
Started May 05 01:17:03 PM PDT 24
Finished May 05 01:17:10 PM PDT 24
Peak memory 220108 kb
Host smart-9bb8a8b6-1293-42d5-9369-d3ee1652f8ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701260893 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3701260893
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2967325692
Short name T346
Test name
Test status
Simulation time 19022625045 ps
CPU time 4.77 seconds
Started May 05 01:17:08 PM PDT 24
Finished May 05 01:17:13 PM PDT 24
Peak memory 203936 kb
Host smart-7625809d-8268-4d05-9f8a-df847fe3d4e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967325692 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2967325692
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.515139383
Short name T306
Test name
Test status
Simulation time 7478274512 ps
CPU time 17.71 seconds
Started May 05 01:17:07 PM PDT 24
Finished May 05 01:17:25 PM PDT 24
Peak memory 203888 kb
Host smart-31b4a404-2208-4e37-9a79-56e8bf0260cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515139383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.515139383
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2806522049
Short name T549
Test name
Test status
Simulation time 2425137223 ps
CPU time 21.17 seconds
Started May 05 01:17:07 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 232548 kb
Host smart-425cbbff-c806-4b3b-989d-a543f05f25c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806522049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2806522049
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1221040357
Short name T468
Test name
Test status
Simulation time 53695249023 ps
CPU time 1393.98 seconds
Started May 05 01:17:04 PM PDT 24
Finished May 05 01:40:19 PM PDT 24
Peak memory 8666444 kb
Host smart-c0c771c4-c496-4584-8858-8eea24113707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221040357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1221040357
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2129937818
Short name T228
Test name
Test status
Simulation time 11118877490 ps
CPU time 1380.55 seconds
Started May 05 01:17:05 PM PDT 24
Finished May 05 01:40:06 PM PDT 24
Peak memory 2670280 kb
Host smart-94792f8c-54e0-44d9-baaf-12439c55a959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129937818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2129937818
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.4064105789
Short name T940
Test name
Test status
Simulation time 1486649733 ps
CPU time 7.3 seconds
Started May 05 01:17:08 PM PDT 24
Finished May 05 01:17:15 PM PDT 24
Peak memory 210016 kb
Host smart-585411b3-24b5-4863-a56f-3ecb87cdb04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064105789 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.4064105789
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.564853415
Short name T696
Test name
Test status
Simulation time 39029799 ps
CPU time 0.58 seconds
Started May 05 01:17:17 PM PDT 24
Finished May 05 01:17:18 PM PDT 24
Peak memory 203692 kb
Host smart-f821bb94-579d-430d-bc32-642a4bf7b742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564853415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.564853415
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1693003982
Short name T1284
Test name
Test status
Simulation time 790837044 ps
CPU time 1.69 seconds
Started May 05 01:17:14 PM PDT 24
Finished May 05 01:17:16 PM PDT 24
Peak memory 212076 kb
Host smart-554bf216-8410-4cf4-bee0-e52d5a8f4282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693003982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1693003982
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3295975712
Short name T490
Test name
Test status
Simulation time 560832281 ps
CPU time 5.46 seconds
Started May 05 01:17:14 PM PDT 24
Finished May 05 01:17:20 PM PDT 24
Peak memory 234312 kb
Host smart-d86784e8-df7d-436c-bb5e-d8f111b5ee39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295975712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3295975712
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1777730749
Short name T663
Test name
Test status
Simulation time 2215186641 ps
CPU time 51.75 seconds
Started May 05 01:17:20 PM PDT 24
Finished May 05 01:18:12 PM PDT 24
Peak memory 407996 kb
Host smart-4d6c7ab5-cc1f-44d5-b8e5-ab5b81064df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777730749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1777730749
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2383877969
Short name T824
Test name
Test status
Simulation time 3228792933 ps
CPU time 103.5 seconds
Started May 05 01:17:16 PM PDT 24
Finished May 05 01:19:00 PM PDT 24
Peak memory 580060 kb
Host smart-280b3a0b-0fdd-4362-9d4d-c9e34f770ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383877969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2383877969
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3381005407
Short name T1068
Test name
Test status
Simulation time 139145691 ps
CPU time 1.01 seconds
Started May 05 01:17:13 PM PDT 24
Finished May 05 01:17:15 PM PDT 24
Peak memory 203692 kb
Host smart-1b7f9318-fc6b-40fd-b1ff-366fb527e7d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381005407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3381005407
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2303761708
Short name T293
Test name
Test status
Simulation time 623411832 ps
CPU time 8.38 seconds
Started May 05 01:17:13 PM PDT 24
Finished May 05 01:17:22 PM PDT 24
Peak memory 203768 kb
Host smart-8df9befb-e92a-4a9c-b443-b0c5076723ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303761708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2303761708
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.4178828507
Short name T178
Test name
Test status
Simulation time 3053553947 ps
CPU time 63.83 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:18:19 PM PDT 24
Peak memory 861120 kb
Host smart-bdfd9163-f5c5-41c6-a576-50b173df2aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178828507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.4178828507
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.866834977
Short name T784
Test name
Test status
Simulation time 868191364 ps
CPU time 6.67 seconds
Started May 05 01:17:19 PM PDT 24
Finished May 05 01:17:26 PM PDT 24
Peak memory 203780 kb
Host smart-b5558fbb-95a5-4d9e-bdbf-a1e62b493451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866834977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.866834977
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.1290655121
Short name T64
Test name
Test status
Simulation time 1139181839 ps
CPU time 16.75 seconds
Started May 05 01:17:17 PM PDT 24
Finished May 05 01:17:35 PM PDT 24
Peak memory 309524 kb
Host smart-31874e3f-b731-4a88-886a-cba960377236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290655121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.1290655121
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3517353425
Short name T299
Test name
Test status
Simulation time 50865529 ps
CPU time 0.64 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:10 PM PDT 24
Peak memory 203616 kb
Host smart-79b84371-03a3-483a-9ce6-413beef31b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517353425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3517353425
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2273815431
Short name T927
Test name
Test status
Simulation time 30111147397 ps
CPU time 71.71 seconds
Started May 05 01:17:16 PM PDT 24
Finished May 05 01:18:28 PM PDT 24
Peak memory 413944 kb
Host smart-1f5cab27-cf63-4e4f-bc5b-fb096cfd3eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273815431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2273815431
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3948493867
Short name T793
Test name
Test status
Simulation time 1201243201 ps
CPU time 19.61 seconds
Started May 05 01:17:09 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 315904 kb
Host smart-3fbbf6e5-acfc-47d3-82d5-5d59a6a29898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948493867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3948493867
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.712809592
Short name T1002
Test name
Test status
Simulation time 1072214642 ps
CPU time 22.1 seconds
Started May 05 01:17:13 PM PDT 24
Finished May 05 01:17:36 PM PDT 24
Peak memory 212000 kb
Host smart-879f9b58-4558-4eb9-b18f-62ba8af37e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712809592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.712809592
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.693108256
Short name T1096
Test name
Test status
Simulation time 2007120904 ps
CPU time 2.96 seconds
Started May 05 01:17:20 PM PDT 24
Finished May 05 01:17:23 PM PDT 24
Peak memory 203816 kb
Host smart-a4314451-6bec-4d5b-9409-fe4d7d8ac897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693108256 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.693108256
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.288833577
Short name T895
Test name
Test status
Simulation time 10665593609 ps
CPU time 11.97 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:17:28 PM PDT 24
Peak memory 239444 kb
Host smart-64f008cb-55d3-428e-931c-2be7757686e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288833577 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.288833577
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.785666695
Short name T396
Test name
Test status
Simulation time 10168079061 ps
CPU time 14.51 seconds
Started May 05 01:17:14 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 298840 kb
Host smart-f9186c10-518f-4095-aef8-5a128aeaedee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785666695 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.785666695
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2660875414
Short name T312
Test name
Test status
Simulation time 1892179331 ps
CPU time 2.49 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:17:18 PM PDT 24
Peak memory 203848 kb
Host smart-ad496562-895d-40d7-8999-7277ab847e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660875414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2660875414
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1555757319
Short name T334
Test name
Test status
Simulation time 11088009300 ps
CPU time 3.98 seconds
Started May 05 01:17:13 PM PDT 24
Finished May 05 01:17:17 PM PDT 24
Peak memory 206772 kb
Host smart-bcd98147-7ec8-4985-8fb1-8cb13f5fb305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555757319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1555757319
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2485816229
Short name T385
Test name
Test status
Simulation time 4594823242 ps
CPU time 8.8 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:17:24 PM PDT 24
Peak memory 203924 kb
Host smart-51c30e9a-a705-46b6-b34c-3996d244c3ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485816229 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2485816229
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3264282881
Short name T390
Test name
Test status
Simulation time 3526065785 ps
CPU time 30.75 seconds
Started May 05 01:17:14 PM PDT 24
Finished May 05 01:17:45 PM PDT 24
Peak memory 203900 kb
Host smart-efa14d31-dd4c-432b-9fd4-13c5994b85e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264282881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3264282881
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1449998392
Short name T1227
Test name
Test status
Simulation time 879504454 ps
CPU time 36.88 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:17:52 PM PDT 24
Peak memory 203824 kb
Host smart-c733b32a-6a01-451e-b1bf-dea82252c541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449998392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1449998392
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1783907000
Short name T827
Test name
Test status
Simulation time 38862566218 ps
CPU time 75.52 seconds
Started May 05 01:17:16 PM PDT 24
Finished May 05 01:18:32 PM PDT 24
Peak memory 1254812 kb
Host smart-deb32d05-5482-4857-a77f-9d98618ac748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783907000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1783907000
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2584579504
Short name T1028
Test name
Test status
Simulation time 32666060057 ps
CPU time 597.26 seconds
Started May 05 01:17:16 PM PDT 24
Finished May 05 01:27:14 PM PDT 24
Peak memory 3798940 kb
Host smart-4daae9cc-ef85-45d6-b4bc-228152e08cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584579504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2584579504
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.561223647
Short name T841
Test name
Test status
Simulation time 5016911358 ps
CPU time 6.4 seconds
Started May 05 01:17:15 PM PDT 24
Finished May 05 01:17:22 PM PDT 24
Peak memory 203944 kb
Host smart-ff97ae63-e2b4-47d5-80f5-b72a00743227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561223647 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.561223647
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.15997988
Short name T535
Test name
Test status
Simulation time 39969893 ps
CPU time 0.64 seconds
Started May 05 01:17:29 PM PDT 24
Finished May 05 01:17:30 PM PDT 24
Peak memory 203732 kb
Host smart-0cf4faec-ad86-4642-abce-9e457fa1c4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.15997988
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2256900895
Short name T974
Test name
Test status
Simulation time 68501287 ps
CPU time 1.35 seconds
Started May 05 01:17:28 PM PDT 24
Finished May 05 01:17:30 PM PDT 24
Peak memory 212080 kb
Host smart-366d52b3-8098-45ad-ac21-5df61c596306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256900895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2256900895
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3423711574
Short name T1257
Test name
Test status
Simulation time 1110081187 ps
CPU time 9.77 seconds
Started May 05 01:17:18 PM PDT 24
Finished May 05 01:17:28 PM PDT 24
Peak memory 306680 kb
Host smart-cac75965-14f1-4f11-8262-1cf41afcb9d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423711574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3423711574
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1448190734
Short name T1001
Test name
Test status
Simulation time 4449826085 ps
CPU time 27.69 seconds
Started May 05 01:17:21 PM PDT 24
Finished May 05 01:17:48 PM PDT 24
Peak memory 445636 kb
Host smart-dd7224e5-c003-442c-9ca7-40e68515689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448190734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1448190734
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1185808077
Short name T469
Test name
Test status
Simulation time 1581334465 ps
CPU time 49.19 seconds
Started May 05 01:17:17 PM PDT 24
Finished May 05 01:18:07 PM PDT 24
Peak memory 567848 kb
Host smart-b5cf10d7-4461-47d7-b72e-4afd5923d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185808077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1185808077
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3150936562
Short name T213
Test name
Test status
Simulation time 500094570 ps
CPU time 1.05 seconds
Started May 05 01:17:20 PM PDT 24
Finished May 05 01:17:21 PM PDT 24
Peak memory 203812 kb
Host smart-b8c58c0b-828c-4f28-9128-63cf1d9dc86e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150936562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3150936562
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1219961236
Short name T1196
Test name
Test status
Simulation time 177350893 ps
CPU time 4.89 seconds
Started May 05 01:17:20 PM PDT 24
Finished May 05 01:17:25 PM PDT 24
Peak memory 203864 kb
Host smart-08309261-ac17-42e6-bf00-9aa293e7231f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219961236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1219961236
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2771657626
Short name T589
Test name
Test status
Simulation time 2861140407 ps
CPU time 80.05 seconds
Started May 05 01:17:19 PM PDT 24
Finished May 05 01:18:39 PM PDT 24
Peak memory 888092 kb
Host smart-a2b03a7e-aadf-44f0-a629-1e5989035350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771657626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2771657626
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.559460895
Short name T886
Test name
Test status
Simulation time 2040331893 ps
CPU time 2.91 seconds
Started May 05 01:17:30 PM PDT 24
Finished May 05 01:17:33 PM PDT 24
Peak memory 203848 kb
Host smart-2e1c7398-3d3c-4b33-9585-b6e337f99e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559460895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.559460895
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.705676290
Short name T716
Test name
Test status
Simulation time 2095690545 ps
CPU time 21.37 seconds
Started May 05 01:17:33 PM PDT 24
Finished May 05 01:17:55 PM PDT 24
Peak memory 294492 kb
Host smart-0486d3a6-6d29-4cef-9ab4-24892d2e2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705676290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.705676290
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.171728224
Short name T100
Test name
Test status
Simulation time 44864352 ps
CPU time 0.64 seconds
Started May 05 01:17:19 PM PDT 24
Finished May 05 01:17:20 PM PDT 24
Peak memory 203664 kb
Host smart-175fa1f4-685b-4b1a-84ce-a9d40bc55da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171728224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.171728224
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2186508293
Short name T36
Test name
Test status
Simulation time 52632647920 ps
CPU time 92.62 seconds
Started May 05 01:17:21 PM PDT 24
Finished May 05 01:18:54 PM PDT 24
Peak memory 264520 kb
Host smart-53bf66d9-a3f9-4278-8220-4dbf97b4968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186508293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2186508293
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.4002029866
Short name T872
Test name
Test status
Simulation time 5347131523 ps
CPU time 27.59 seconds
Started May 05 01:17:16 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 339888 kb
Host smart-8277ccd7-eb4d-4d61-bcc5-c579ec3d329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002029866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.4002029866
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3471266072
Short name T472
Test name
Test status
Simulation time 515186278 ps
CPU time 7.53 seconds
Started May 05 01:17:25 PM PDT 24
Finished May 05 01:17:33 PM PDT 24
Peak memory 215280 kb
Host smart-5a21fc2d-3a76-408d-8dbb-3b901520c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471266072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3471266072
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.919505739
Short name T1304
Test name
Test status
Simulation time 822023076 ps
CPU time 2.34 seconds
Started May 05 01:17:28 PM PDT 24
Finished May 05 01:17:31 PM PDT 24
Peak memory 203832 kb
Host smart-e5f222c3-2cf2-4aea-a4ad-33b0b4cdbb7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919505739 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.919505739
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2273619873
Short name T62
Test name
Test status
Simulation time 10062312371 ps
CPU time 32.53 seconds
Started May 05 01:17:24 PM PDT 24
Finished May 05 01:17:57 PM PDT 24
Peak memory 308820 kb
Host smart-3de04be8-6827-4d69-9f64-c320047c67fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273619873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2273619873
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.246403812
Short name T412
Test name
Test status
Simulation time 10553734461 ps
CPU time 13.41 seconds
Started May 05 01:17:24 PM PDT 24
Finished May 05 01:17:38 PM PDT 24
Peak memory 270156 kb
Host smart-3f064a74-2ce1-43ea-bf1c-4d1d8b59aef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246403812 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_tx.246403812
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.296172595
Short name T219
Test name
Test status
Simulation time 1397205737 ps
CPU time 2.22 seconds
Started May 05 01:17:29 PM PDT 24
Finished May 05 01:17:32 PM PDT 24
Peak memory 203812 kb
Host smart-8b6063b0-8933-46fc-bdca-d2242c122d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296172595 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.296172595
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2029875762
Short name T806
Test name
Test status
Simulation time 4627723893 ps
CPU time 6.01 seconds
Started May 05 01:17:27 PM PDT 24
Finished May 05 01:17:34 PM PDT 24
Peak memory 217180 kb
Host smart-583cac66-3fef-4de5-a8fb-40c82f531f7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029875762 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2029875762
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2380242663
Short name T623
Test name
Test status
Simulation time 5083359240 ps
CPU time 8.77 seconds
Started May 05 01:17:23 PM PDT 24
Finished May 05 01:17:32 PM PDT 24
Peak memory 431756 kb
Host smart-974b4a39-8dfd-466d-a22f-5359b449344c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380242663 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2380242663
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.317291585
Short name T1195
Test name
Test status
Simulation time 3751042391 ps
CPU time 21.71 seconds
Started May 05 01:17:24 PM PDT 24
Finished May 05 01:17:46 PM PDT 24
Peak memory 203940 kb
Host smart-8b50c865-6268-48fa-aad4-87622cc30b49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317291585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.317291585
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2128813390
Short name T380
Test name
Test status
Simulation time 2245945187 ps
CPU time 26.67 seconds
Started May 05 01:17:25 PM PDT 24
Finished May 05 01:17:52 PM PDT 24
Peak memory 203792 kb
Host smart-2064b07d-8e9b-4eb6-b3a3-dd95647cc787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128813390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2128813390
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.4019420488
Short name T333
Test name
Test status
Simulation time 25145864817 ps
CPU time 38.44 seconds
Started May 05 01:17:23 PM PDT 24
Finished May 05 01:18:02 PM PDT 24
Peak memory 696468 kb
Host smart-741c636b-16b4-4ce5-a03a-293042592d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019420488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.4019420488
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1904307500
Short name T277
Test name
Test status
Simulation time 33379399206 ps
CPU time 3098.87 seconds
Started May 05 01:17:25 PM PDT 24
Finished May 05 02:09:04 PM PDT 24
Peak memory 8077476 kb
Host smart-d0198914-466b-4cc0-acc9-fdafa274f6ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904307500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1904307500
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1433991513
Short name T526
Test name
Test status
Simulation time 5603910054 ps
CPU time 6.99 seconds
Started May 05 01:17:25 PM PDT 24
Finished May 05 01:17:32 PM PDT 24
Peak memory 212124 kb
Host smart-4dc84079-97cd-4b52-b74f-a68354d61f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433991513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1433991513
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.4117519529
Short name T1079
Test name
Test status
Simulation time 898697112 ps
CPU time 4.95 seconds
Started May 05 01:17:24 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 203780 kb
Host smart-918ba6ba-0363-461b-9d91-7b9c27f3ed10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117519529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.4117519529
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2927515632
Short name T689
Test name
Test status
Simulation time 56910351 ps
CPU time 0.64 seconds
Started May 05 01:17:39 PM PDT 24
Finished May 05 01:17:40 PM PDT 24
Peak memory 203724 kb
Host smart-f7119e45-a2a3-492b-b4a9-87c8af00ecac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927515632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2927515632
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.484183048
Short name T278
Test name
Test status
Simulation time 155687580 ps
CPU time 1.45 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:17:35 PM PDT 24
Peak memory 212044 kb
Host smart-90172170-eb9f-4217-9de3-eee2a2bb10f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484183048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.484183048
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3751584926
Short name T551
Test name
Test status
Simulation time 1446365764 ps
CPU time 7.9 seconds
Started May 05 01:17:29 PM PDT 24
Finished May 05 01:17:37 PM PDT 24
Peak memory 279256 kb
Host smart-6222f67e-52b6-422d-b6a2-58b5e855ba4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751584926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3751584926
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.4047823169
Short name T574
Test name
Test status
Simulation time 1790882346 ps
CPU time 123.64 seconds
Started May 05 01:17:29 PM PDT 24
Finished May 05 01:19:34 PM PDT 24
Peak memory 628252 kb
Host smart-602d855d-bf85-4af0-9961-3ef495d02cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047823169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.4047823169
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.4245374862
Short name T330
Test name
Test status
Simulation time 441991385 ps
CPU time 0.95 seconds
Started May 05 01:17:28 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 203712 kb
Host smart-8d6c5ece-caca-490b-81bb-b403f8a9350b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245374862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.4245374862
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3153527377
Short name T880
Test name
Test status
Simulation time 352454214 ps
CPU time 6.25 seconds
Started May 05 01:17:30 PM PDT 24
Finished May 05 01:17:37 PM PDT 24
Peak memory 203784 kb
Host smart-92940add-7813-4592-8fd0-ca6d8a06cda3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153527377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3153527377
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1546656724
Short name T110
Test name
Test status
Simulation time 4451979312 ps
CPU time 363.92 seconds
Started May 05 01:17:32 PM PDT 24
Finished May 05 01:23:37 PM PDT 24
Peak memory 1300964 kb
Host smart-ba005b44-99b5-466d-b150-9c7eaed766d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546656724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1546656724
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.605100972
Short name T678
Test name
Test status
Simulation time 2222498294 ps
CPU time 9.01 seconds
Started May 05 01:17:41 PM PDT 24
Finished May 05 01:17:50 PM PDT 24
Peak memory 203844 kb
Host smart-32c99493-2a8d-44ba-b43f-f5ec1ac5ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605100972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.605100972
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3656398936
Short name T1241
Test name
Test status
Simulation time 1884402399 ps
CPU time 32.31 seconds
Started May 05 01:17:39 PM PDT 24
Finished May 05 01:18:12 PM PDT 24
Peak memory 385336 kb
Host smart-08adaafe-9747-4ab7-94d9-0021ef8b0cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656398936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3656398936
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1246095835
Short name T44
Test name
Test status
Simulation time 19568662 ps
CPU time 0.62 seconds
Started May 05 01:17:28 PM PDT 24
Finished May 05 01:17:29 PM PDT 24
Peak memory 203584 kb
Host smart-fb7c78b7-59a8-4fec-8eb0-019492e936f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246095835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1246095835
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.4279443751
Short name T1150
Test name
Test status
Simulation time 6746310179 ps
CPU time 263.31 seconds
Started May 05 01:17:33 PM PDT 24
Finished May 05 01:21:56 PM PDT 24
Peak memory 1670680 kb
Host smart-20f12067-d5d5-49eb-a77f-2ee8e91dcb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279443751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4279443751
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.419339777
Short name T321
Test name
Test status
Simulation time 3590868248 ps
CPU time 40.72 seconds
Started May 05 01:17:30 PM PDT 24
Finished May 05 01:18:11 PM PDT 24
Peak memory 263756 kb
Host smart-7bd4dcb6-57c9-4609-abc3-4e8f891ccb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419339777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.419339777
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.4106853786
Short name T1298
Test name
Test status
Simulation time 40206045000 ps
CPU time 1451.62 seconds
Started May 05 01:17:37 PM PDT 24
Finished May 05 01:41:49 PM PDT 24
Peak memory 4733920 kb
Host smart-9a45ec8f-47d0-45e6-bde0-90b9c94be792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106853786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.4106853786
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.830481368
Short name T810
Test name
Test status
Simulation time 3513526413 ps
CPU time 5.31 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:17:39 PM PDT 24
Peak memory 213160 kb
Host smart-1e695727-10cf-40c4-a532-99a955376f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830481368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.830481368
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2118964972
Short name T751
Test name
Test status
Simulation time 4091861471 ps
CPU time 5 seconds
Started May 05 01:17:39 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 214300 kb
Host smart-4e0b3133-ca8d-418c-aabf-a97c9f10039f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118964972 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2118964972
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1754313846
Short name T86
Test name
Test status
Simulation time 10496138823 ps
CPU time 15.74 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:17:50 PM PDT 24
Peak memory 262132 kb
Host smart-aa885704-a7fe-45f5-b00f-d6d309a8a07b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754313846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1754313846
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3869242778
Short name T934
Test name
Test status
Simulation time 10082116810 ps
CPU time 73.48 seconds
Started May 05 01:17:37 PM PDT 24
Finished May 05 01:18:51 PM PDT 24
Peak memory 594936 kb
Host smart-9cc50c80-40a2-4eed-a559-fe0be79f8987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869242778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3869242778
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.3633562800
Short name T1344
Test name
Test status
Simulation time 855241425 ps
CPU time 2.66 seconds
Started May 05 01:17:41 PM PDT 24
Finished May 05 01:17:44 PM PDT 24
Peak memory 203844 kb
Host smart-bcbca336-20e1-4d8d-aa2e-079b15a4df28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633562800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.3633562800
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1360267908
Short name T501
Test name
Test status
Simulation time 1104464215 ps
CPU time 5.57 seconds
Started May 05 01:17:36 PM PDT 24
Finished May 05 01:17:42 PM PDT 24
Peak memory 203904 kb
Host smart-3ae9fd38-b8fd-4e8a-8c0a-38d9c151f6db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360267908 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1360267908
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2612298159
Short name T997
Test name
Test status
Simulation time 17483814504 ps
CPU time 354.29 seconds
Started May 05 01:17:36 PM PDT 24
Finished May 05 01:23:31 PM PDT 24
Peak memory 4198652 kb
Host smart-169a034d-2d21-4e30-b521-026baf3eea34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612298159 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2612298159
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.379330966
Short name T1089
Test name
Test status
Simulation time 1095600814 ps
CPU time 13.59 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:17:48 PM PDT 24
Peak memory 203760 kb
Host smart-4132f779-bc15-46e2-98ba-451076f07877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379330966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.379330966
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3717423380
Short name T1236
Test name
Test status
Simulation time 4018842428 ps
CPU time 43.13 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:18:17 PM PDT 24
Peak memory 203920 kb
Host smart-ae64fcd9-c449-4129-8720-bfddcd9a983d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717423380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3717423380
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2385302222
Short name T762
Test name
Test status
Simulation time 50334754094 ps
CPU time 1062.47 seconds
Started May 05 01:17:34 PM PDT 24
Finished May 05 01:35:17 PM PDT 24
Peak memory 7671368 kb
Host smart-532b16fb-ec96-4a9b-8ba0-7b85dfeedfae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385302222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2385302222
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1947943260
Short name T661
Test name
Test status
Simulation time 4885577216 ps
CPU time 21.33 seconds
Started May 05 01:17:35 PM PDT 24
Finished May 05 01:17:57 PM PDT 24
Peak memory 428300 kb
Host smart-2611cca6-8743-455c-8746-8dc546525abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947943260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1947943260
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3268663069
Short name T40
Test name
Test status
Simulation time 5689434434 ps
CPU time 7.34 seconds
Started May 05 01:17:35 PM PDT 24
Finished May 05 01:17:43 PM PDT 24
Peak memory 220212 kb
Host smart-27e49a68-eae6-4171-8ca7-1a78ef75734b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268663069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3268663069
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.522960278
Short name T438
Test name
Test status
Simulation time 18168412 ps
CPU time 0.6 seconds
Started May 05 01:10:18 PM PDT 24
Finished May 05 01:10:19 PM PDT 24
Peak memory 203660 kb
Host smart-80eb8382-b258-45a4-9174-b1f5202f9c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522960278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.522960278
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2353597835
Short name T527
Test name
Test status
Simulation time 98630746 ps
CPU time 1.47 seconds
Started May 05 01:10:09 PM PDT 24
Finished May 05 01:10:11 PM PDT 24
Peak memory 212116 kb
Host smart-3d3d90b4-6650-49e5-84f3-417516eed7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353597835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2353597835
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2263297411
Short name T537
Test name
Test status
Simulation time 1228793740 ps
CPU time 6.22 seconds
Started May 05 01:10:09 PM PDT 24
Finished May 05 01:10:16 PM PDT 24
Peak memory 271552 kb
Host smart-d9eef3a2-a7af-4477-97b4-c320e8a4ebc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263297411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2263297411
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.101809848
Short name T1352
Test name
Test status
Simulation time 1495985032 ps
CPU time 51.55 seconds
Started May 05 01:10:14 PM PDT 24
Finished May 05 01:11:06 PM PDT 24
Peak memory 575780 kb
Host smart-dca46b09-9a18-43f7-9b98-c0a9385016c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101809848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.101809848
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3384289625
Short name T956
Test name
Test status
Simulation time 2136968426 ps
CPU time 83.64 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:11:28 PM PDT 24
Peak memory 735556 kb
Host smart-1d971dd8-aac2-4063-a6f9-658aa999201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384289625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3384289625
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2757030503
Short name T539
Test name
Test status
Simulation time 899062267 ps
CPU time 1.13 seconds
Started May 05 01:10:08 PM PDT 24
Finished May 05 01:10:10 PM PDT 24
Peak memory 203792 kb
Host smart-6019fe53-72bc-420b-ada7-1586def0f83a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757030503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2757030503
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3190773503
Short name T1319
Test name
Test status
Simulation time 102194294 ps
CPU time 2.76 seconds
Started May 05 01:10:07 PM PDT 24
Finished May 05 01:10:10 PM PDT 24
Peak memory 214760 kb
Host smart-8fe59c6f-d684-4b50-b5b2-3bee65f0d7f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190773503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3190773503
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2497322175
Short name T737
Test name
Test status
Simulation time 18467751455 ps
CPU time 124.04 seconds
Started May 05 01:10:03 PM PDT 24
Finished May 05 01:12:08 PM PDT 24
Peak memory 1354828 kb
Host smart-5f051968-6cb8-43bf-8254-d07c5ad9bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497322175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2497322175
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1777413550
Short name T634
Test name
Test status
Simulation time 1373505126 ps
CPU time 5.68 seconds
Started May 05 01:10:13 PM PDT 24
Finished May 05 01:10:19 PM PDT 24
Peak memory 203908 kb
Host smart-b8c022e0-cb56-4414-981f-a49622fb1c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777413550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1777413550
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.563655468
Short name T399
Test name
Test status
Simulation time 2266774925 ps
CPU time 48.21 seconds
Started May 05 01:10:18 PM PDT 24
Finished May 05 01:11:07 PM PDT 24
Peak memory 277008 kb
Host smart-61ff323a-a275-472b-a074-47507ea386a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563655468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.563655468
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3522629565
Short name T361
Test name
Test status
Simulation time 76827100 ps
CPU time 0.68 seconds
Started May 05 01:10:03 PM PDT 24
Finished May 05 01:10:04 PM PDT 24
Peak memory 203648 kb
Host smart-02b22700-441c-4d8d-ab94-4ca7d826c943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522629565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3522629565
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1947867361
Short name T206
Test name
Test status
Simulation time 916468393 ps
CPU time 2.81 seconds
Started May 05 01:10:08 PM PDT 24
Finished May 05 01:10:11 PM PDT 24
Peak memory 228396 kb
Host smart-2531b567-b7fd-47fb-9d09-0631c457bd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947867361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1947867361
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2871875643
Short name T1039
Test name
Test status
Simulation time 2025228171 ps
CPU time 47.56 seconds
Started May 05 01:10:04 PM PDT 24
Finished May 05 01:10:52 PM PDT 24
Peak memory 301456 kb
Host smart-6e9607f6-ea1c-41f0-bde2-860f8911fc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871875643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2871875643
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.1356554718
Short name T1181
Test name
Test status
Simulation time 23513186870 ps
CPU time 1472.96 seconds
Started May 05 01:10:14 PM PDT 24
Finished May 05 01:34:48 PM PDT 24
Peak memory 2150504 kb
Host smart-52185dd6-0e5a-43bd-9f3d-fc02b4ecbe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356554718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1356554718
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.227503216
Short name T437
Test name
Test status
Simulation time 4691867222 ps
CPU time 34.32 seconds
Started May 05 01:10:13 PM PDT 24
Finished May 05 01:10:48 PM PDT 24
Peak memory 220084 kb
Host smart-0f523c54-e5d6-4e92-9868-8f5447e549f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227503216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.227503216
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.579051698
Short name T289
Test name
Test status
Simulation time 2747973933 ps
CPU time 3.67 seconds
Started May 05 01:10:15 PM PDT 24
Finished May 05 01:10:19 PM PDT 24
Peak memory 203916 kb
Host smart-8dd45d1f-7a06-4db4-9135-104e23e04af2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579051698 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.579051698
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3044928858
Short name T1153
Test name
Test status
Simulation time 10305808415 ps
CPU time 13.81 seconds
Started May 05 01:10:08 PM PDT 24
Finished May 05 01:10:23 PM PDT 24
Peak memory 279000 kb
Host smart-30bb7406-b3a3-4f18-9898-f6ed0415e385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044928858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3044928858
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1910539786
Short name T686
Test name
Test status
Simulation time 10188560731 ps
CPU time 13.5 seconds
Started May 05 01:10:18 PM PDT 24
Finished May 05 01:10:32 PM PDT 24
Peak memory 307544 kb
Host smart-43f37677-3612-42ee-8a9f-37ba3f592404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910539786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1910539786
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.4080055903
Short name T220
Test name
Test status
Simulation time 1214547272 ps
CPU time 2.09 seconds
Started May 05 01:10:13 PM PDT 24
Finished May 05 01:10:16 PM PDT 24
Peak memory 203824 kb
Host smart-de6194b0-41b3-4e3f-8295-1fa80fd38a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080055903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.4080055903
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2237297057
Short name T1225
Test name
Test status
Simulation time 2663051144 ps
CPU time 3.87 seconds
Started May 05 01:10:08 PM PDT 24
Finished May 05 01:10:12 PM PDT 24
Peak memory 204832 kb
Host smart-fd352752-c624-4c63-97c2-b0366a705baf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237297057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2237297057
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2739665825
Short name T99
Test name
Test status
Simulation time 18646945838 ps
CPU time 9.72 seconds
Started May 05 01:10:09 PM PDT 24
Finished May 05 01:10:19 PM PDT 24
Peak memory 276672 kb
Host smart-8cb3155c-5c03-45ef-aa10-92ff5db6a8b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739665825 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2739665825
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.4266650569
Short name T276
Test name
Test status
Simulation time 1712585975 ps
CPU time 14.18 seconds
Started May 05 01:10:10 PM PDT 24
Finished May 05 01:10:24 PM PDT 24
Peak memory 203832 kb
Host smart-97cc0333-f314-4f7f-b6c9-07b2f01c925b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266650569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.4266650569
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.4286738486
Short name T227
Test name
Test status
Simulation time 2224275989 ps
CPU time 8.29 seconds
Started May 05 01:10:07 PM PDT 24
Finished May 05 01:10:16 PM PDT 24
Peak memory 208904 kb
Host smart-a33e9db6-d567-4d83-9f30-ea89d7ee9936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286738486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.4286738486
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2053359021
Short name T376
Test name
Test status
Simulation time 64000003402 ps
CPU time 210.72 seconds
Started May 05 01:10:10 PM PDT 24
Finished May 05 01:13:41 PM PDT 24
Peak memory 2066900 kb
Host smart-776be343-5624-4758-b030-5aa175155fe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053359021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2053359021
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2382901394
Short name T573
Test name
Test status
Simulation time 34345771492 ps
CPU time 999.28 seconds
Started May 05 01:10:11 PM PDT 24
Finished May 05 01:26:51 PM PDT 24
Peak memory 4125676 kb
Host smart-ab5f11d3-9cca-4af6-8dec-a3a62a80403c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382901394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2382901394
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3430821892
Short name T884
Test name
Test status
Simulation time 6613288113 ps
CPU time 7.44 seconds
Started May 05 01:10:11 PM PDT 24
Finished May 05 01:10:19 PM PDT 24
Peak memory 218052 kb
Host smart-dc34ec46-24e7-43ad-b46c-11c4c84d8ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430821892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3430821892
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3724578425
Short name T1303
Test name
Test status
Simulation time 14646794 ps
CPU time 0.59 seconds
Started May 05 01:10:30 PM PDT 24
Finished May 05 01:10:31 PM PDT 24
Peak memory 203660 kb
Host smart-0d4b26a0-de5c-4319-a319-7debda99e4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724578425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3724578425
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3002552793
Short name T562
Test name
Test status
Simulation time 256095405 ps
CPU time 1.37 seconds
Started May 05 01:10:22 PM PDT 24
Finished May 05 01:10:23 PM PDT 24
Peak memory 212132 kb
Host smart-8202865a-ce3e-471a-aa53-67839510e6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002552793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3002552793
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.99737513
Short name T666
Test name
Test status
Simulation time 3405632293 ps
CPU time 11.01 seconds
Started May 05 01:10:20 PM PDT 24
Finished May 05 01:10:32 PM PDT 24
Peak memory 245332 kb
Host smart-032ed741-db56-444e-be77-4e4378313d2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99737513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.99737513
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3573261592
Short name T61
Test name
Test status
Simulation time 2419173400 ps
CPU time 79.69 seconds
Started May 05 01:10:23 PM PDT 24
Finished May 05 01:11:43 PM PDT 24
Peak memory 505440 kb
Host smart-246c419a-45b4-4c69-a5e0-c85e61822217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573261592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3573261592
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.4168302983
Short name T1147
Test name
Test status
Simulation time 1224793090 ps
CPU time 35.47 seconds
Started May 05 01:10:14 PM PDT 24
Finished May 05 01:10:50 PM PDT 24
Peak memory 449052 kb
Host smart-284a5616-19e8-432b-9d5b-90cdda7ccf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168302983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.4168302983
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.41540914
Short name T953
Test name
Test status
Simulation time 159388493 ps
CPU time 1.01 seconds
Started May 05 01:10:19 PM PDT 24
Finished May 05 01:10:21 PM PDT 24
Peak memory 203684 kb
Host smart-71735ca3-2995-4729-9dee-a3730726e638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.41540914
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3142680976
Short name T1353
Test name
Test status
Simulation time 193100830 ps
CPU time 10.07 seconds
Started May 05 01:10:20 PM PDT 24
Finished May 05 01:10:31 PM PDT 24
Peak memory 238368 kb
Host smart-1911a004-ad70-4426-a7ba-92120a3c2919
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142680976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3142680976
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1310253822
Short name T774
Test name
Test status
Simulation time 3679126112 ps
CPU time 90.03 seconds
Started May 05 01:10:14 PM PDT 24
Finished May 05 01:11:45 PM PDT 24
Peak memory 1116424 kb
Host smart-47d9f57b-dfc0-43ff-8c65-d5622edda086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310253822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1310253822
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1985317055
Short name T748
Test name
Test status
Simulation time 327188840 ps
CPU time 2.67 seconds
Started May 05 01:10:25 PM PDT 24
Finished May 05 01:10:28 PM PDT 24
Peak memory 203824 kb
Host smart-38d515ec-7ed5-4825-a271-ea9958ae830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985317055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1985317055
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3458688392
Short name T1081
Test name
Test status
Simulation time 1627824769 ps
CPU time 30.1 seconds
Started May 05 01:10:29 PM PDT 24
Finished May 05 01:11:00 PM PDT 24
Peak memory 397676 kb
Host smart-91b823f0-96db-43af-975a-dd815d0a5f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458688392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3458688392
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.4094671439
Short name T493
Test name
Test status
Simulation time 25616210 ps
CPU time 0.65 seconds
Started May 05 01:10:14 PM PDT 24
Finished May 05 01:10:15 PM PDT 24
Peak memory 203576 kb
Host smart-fe3c9dd6-efe4-4ba7-8f6f-8fa8eddb88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094671439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.4094671439
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3646255994
Short name T937
Test name
Test status
Simulation time 656885186 ps
CPU time 31.17 seconds
Started May 05 01:10:19 PM PDT 24
Finished May 05 01:10:51 PM PDT 24
Peak memory 311200 kb
Host smart-a8dfd2f1-cac3-4ad6-a61c-44b3d22d807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646255994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3646255994
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1790546279
Short name T429
Test name
Test status
Simulation time 1641835977 ps
CPU time 74.09 seconds
Started May 05 01:10:13 PM PDT 24
Finished May 05 01:11:28 PM PDT 24
Peak memory 300696 kb
Host smart-60f74652-16b0-4264-a12d-3384c55208b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790546279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1790546279
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1735626545
Short name T237
Test name
Test status
Simulation time 12918637048 ps
CPU time 134.09 seconds
Started May 05 01:10:18 PM PDT 24
Finished May 05 01:12:33 PM PDT 24
Peak memory 507780 kb
Host smart-d3bffc09-923d-4631-9c72-c72c07b2259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735626545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1735626545
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1429412843
Short name T1192
Test name
Test status
Simulation time 1446821098 ps
CPU time 13.5 seconds
Started May 05 01:10:19 PM PDT 24
Finished May 05 01:10:32 PM PDT 24
Peak memory 220052 kb
Host smart-c3fa06b4-cfbe-449b-9eed-845655d20620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429412843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1429412843
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2803895800
Short name T340
Test name
Test status
Simulation time 2357970487 ps
CPU time 3.27 seconds
Started May 05 01:10:26 PM PDT 24
Finished May 05 01:10:30 PM PDT 24
Peak memory 203980 kb
Host smart-0a9c56d3-0fdd-4595-9f96-943f08c46b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803895800 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2803895800
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.28947998
Short name T453
Test name
Test status
Simulation time 10187470714 ps
CPU time 22.71 seconds
Started May 05 01:10:24 PM PDT 24
Finished May 05 01:10:47 PM PDT 24
Peak memory 272260 kb
Host smart-b1a973af-a4c0-414e-814f-8c5e9234cfe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947998 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_acq.28947998
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2736177343
Short name T836
Test name
Test status
Simulation time 10448665643 ps
CPU time 13.09 seconds
Started May 05 01:10:28 PM PDT 24
Finished May 05 01:10:41 PM PDT 24
Peak memory 292436 kb
Host smart-510793df-2720-4d8f-b0ff-0b0289b9a0ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736177343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2736177343
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3613739288
Short name T458
Test name
Test status
Simulation time 495057353 ps
CPU time 3.06 seconds
Started May 05 01:10:26 PM PDT 24
Finished May 05 01:10:30 PM PDT 24
Peak memory 203776 kb
Host smart-317a1938-076b-4f5f-9ae2-3e1a334b1dc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613739288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3613739288
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3530361012
Short name T597
Test name
Test status
Simulation time 3861838464 ps
CPU time 6.92 seconds
Started May 05 01:10:19 PM PDT 24
Finished May 05 01:10:27 PM PDT 24
Peak memory 212104 kb
Host smart-65eef036-2eed-4bbb-8509-e7210888cdb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530361012 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3530361012
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1487490455
Short name T874
Test name
Test status
Simulation time 18835177486 ps
CPU time 7.63 seconds
Started May 05 01:10:19 PM PDT 24
Finished May 05 01:10:27 PM PDT 24
Peak memory 203904 kb
Host smart-bc72846c-3f32-457b-9055-d1b985d0ec44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487490455 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1487490455
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.230601765
Short name T543
Test name
Test status
Simulation time 1941061042 ps
CPU time 14 seconds
Started May 05 01:10:18 PM PDT 24
Finished May 05 01:10:32 PM PDT 24
Peak memory 203804 kb
Host smart-b0b981e7-7421-45db-b987-4abbc09f3452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230601765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.230601765
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1699935793
Short name T1050
Test name
Test status
Simulation time 2235696171 ps
CPU time 11.07 seconds
Started May 05 01:10:21 PM PDT 24
Finished May 05 01:10:33 PM PDT 24
Peak memory 209448 kb
Host smart-2858ed9f-8cdc-4c52-bc56-8a00579403ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699935793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1699935793
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2457757378
Short name T384
Test name
Test status
Simulation time 37805660192 ps
CPU time 70.1 seconds
Started May 05 01:10:20 PM PDT 24
Finished May 05 01:11:30 PM PDT 24
Peak memory 1146700 kb
Host smart-75453975-21f9-4731-8e17-a4d20e974786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457757378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2457757378
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2011319783
Short name T792
Test name
Test status
Simulation time 42900872182 ps
CPU time 108.16 seconds
Started May 05 01:10:23 PM PDT 24
Finished May 05 01:12:11 PM PDT 24
Peak memory 1241796 kb
Host smart-521bb5d6-44a8-4728-8605-e72d0fff757a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011319783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2011319783
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.409736292
Short name T528
Test name
Test status
Simulation time 11999773095 ps
CPU time 6.35 seconds
Started May 05 01:10:20 PM PDT 24
Finished May 05 01:10:26 PM PDT 24
Peak memory 220140 kb
Host smart-a31b6da4-0011-403e-ba46-624ceeda4f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409736292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.409736292
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1029574157
Short name T559
Test name
Test status
Simulation time 19534566 ps
CPU time 0.62 seconds
Started May 05 01:10:37 PM PDT 24
Finished May 05 01:10:38 PM PDT 24
Peak memory 203736 kb
Host smart-b2be82ef-216e-42a5-90a9-517aee79a888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029574157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1029574157
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3636573827
Short name T667
Test name
Test status
Simulation time 120843521 ps
CPU time 1.31 seconds
Started May 05 01:10:30 PM PDT 24
Finished May 05 01:10:32 PM PDT 24
Peak memory 212132 kb
Host smart-470248b3-20bc-45b8-9906-8f1e2ac65694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636573827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3636573827
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3669178233
Short name T362
Test name
Test status
Simulation time 464016591 ps
CPU time 4.77 seconds
Started May 05 01:10:30 PM PDT 24
Finished May 05 01:10:36 PM PDT 24
Peak memory 251260 kb
Host smart-a89de194-3c4f-4024-8cf9-cc3d9d87b599
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669178233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3669178233
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.876152903
Short name T759
Test name
Test status
Simulation time 7253325256 ps
CPU time 49.9 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 621012 kb
Host smart-437a5be4-56d1-4bdb-8e4e-20758bed568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876152903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.876152903
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1426924020
Short name T700
Test name
Test status
Simulation time 8216902779 ps
CPU time 54.5 seconds
Started May 05 01:10:32 PM PDT 24
Finished May 05 01:11:27 PM PDT 24
Peak memory 584972 kb
Host smart-ee7941dc-f392-4936-a455-64aa0fb11e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426924020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1426924020
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3017612246
Short name T831
Test name
Test status
Simulation time 1078843476 ps
CPU time 0.91 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:10:33 PM PDT 24
Peak memory 203684 kb
Host smart-a8154db1-212f-4357-8a43-779ccce1fb2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017612246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3017612246
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.463016125
Short name T1232
Test name
Test status
Simulation time 103285258 ps
CPU time 5.75 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:10:37 PM PDT 24
Peak memory 203828 kb
Host smart-3eeadbba-718f-45be-a6aa-e13541b2fcbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463016125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.463016125
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.81337722
Short name T234
Test name
Test status
Simulation time 2573361903 ps
CPU time 73.82 seconds
Started May 05 01:10:29 PM PDT 24
Finished May 05 01:11:43 PM PDT 24
Peak memory 834684 kb
Host smart-6225a55a-8ff8-4939-8a62-bb728a15f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81337722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.81337722
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3483100627
Short name T910
Test name
Test status
Simulation time 2040254712 ps
CPU time 18.01 seconds
Started May 05 01:10:37 PM PDT 24
Finished May 05 01:10:56 PM PDT 24
Peak memory 203860 kb
Host smart-4d9c0d9d-7b55-41d7-924c-fd9b0b5859bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483100627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3483100627
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2430493007
Short name T569
Test name
Test status
Simulation time 1923759386 ps
CPU time 33.68 seconds
Started May 05 01:10:36 PM PDT 24
Finished May 05 01:11:10 PM PDT 24
Peak memory 413552 kb
Host smart-872ce9d8-443f-46ac-9d26-754b2c0ece45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430493007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2430493007
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.841093178
Short name T1355
Test name
Test status
Simulation time 20017736 ps
CPU time 0.66 seconds
Started May 05 01:10:25 PM PDT 24
Finished May 05 01:10:27 PM PDT 24
Peak memory 203880 kb
Host smart-d3eac761-294c-4f05-a32a-770bbc76d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841093178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.841093178
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1215569729
Short name T1337
Test name
Test status
Simulation time 5282173612 ps
CPU time 41.85 seconds
Started May 05 01:10:32 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 239836 kb
Host smart-e212d5e9-c522-4405-bb64-b6a1bb870ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215569729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1215569729
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2256007936
Short name T850
Test name
Test status
Simulation time 2230396268 ps
CPU time 54.21 seconds
Started May 05 01:10:25 PM PDT 24
Finished May 05 01:11:20 PM PDT 24
Peak memory 294712 kb
Host smart-a2a8e81b-4670-415e-9e49-797de0e4544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256007936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2256007936
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2225965708
Short name T1071
Test name
Test status
Simulation time 10485302826 ps
CPU time 1307.05 seconds
Started May 05 01:10:34 PM PDT 24
Finished May 05 01:32:22 PM PDT 24
Peak memory 2524016 kb
Host smart-6cf58bfe-c5c8-4b30-ac4c-ec4baf341e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225965708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2225965708
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1950605799
Short name T454
Test name
Test status
Simulation time 1786837393 ps
CPU time 9.8 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:10:42 PM PDT 24
Peak memory 215328 kb
Host smart-3bb0b616-fb57-4898-976d-255805128d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950605799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1950605799
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1256547722
Short name T1343
Test name
Test status
Simulation time 1639917617 ps
CPU time 3.9 seconds
Started May 05 01:10:35 PM PDT 24
Finished May 05 01:10:39 PM PDT 24
Peak memory 212060 kb
Host smart-41dddaac-b5be-403b-920f-68ca6b975b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256547722 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1256547722
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.66828625
Short name T1260
Test name
Test status
Simulation time 10365979643 ps
CPU time 4.63 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:10:36 PM PDT 24
Peak memory 212256 kb
Host smart-601ada7c-828a-4b16-94d5-6e6053e361bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66828625 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_acq.66828625
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.4278562137
Short name T966
Test name
Test status
Simulation time 10151589746 ps
CPU time 73.99 seconds
Started May 05 01:10:33 PM PDT 24
Finished May 05 01:11:47 PM PDT 24
Peak memory 491256 kb
Host smart-d84b279e-15b9-4553-ab38-0fda2ee64eab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278562137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.4278562137
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1207666726
Short name T13
Test name
Test status
Simulation time 1788264302 ps
CPU time 2.83 seconds
Started May 05 01:10:37 PM PDT 24
Finished May 05 01:10:40 PM PDT 24
Peak memory 203816 kb
Host smart-e8f43013-726a-4e5b-976a-083680e85c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207666726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1207666726
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.612629572
Short name T1146
Test name
Test status
Simulation time 3991870047 ps
CPU time 5.17 seconds
Started May 05 01:10:32 PM PDT 24
Finished May 05 01:10:38 PM PDT 24
Peak memory 204368 kb
Host smart-e25f1109-fa1d-4f90-80b2-8eeb8d65c3f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612629572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.612629572
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2065207113
Short name T522
Test name
Test status
Simulation time 21497722937 ps
CPU time 412.88 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:17:24 PM PDT 24
Peak memory 3828584 kb
Host smart-3b069508-6f74-4b69-b441-6bcbdf676f8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065207113 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2065207113
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2475717144
Short name T264
Test name
Test status
Simulation time 5291060710 ps
CPU time 8.38 seconds
Started May 05 01:10:32 PM PDT 24
Finished May 05 01:10:41 PM PDT 24
Peak memory 203824 kb
Host smart-24e2ed4c-d9b9-46e1-a0e6-d9a2b1c0e742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475717144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2475717144
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3466670960
Short name T1293
Test name
Test status
Simulation time 1626401611 ps
CPU time 12.47 seconds
Started May 05 01:10:32 PM PDT 24
Finished May 05 01:10:45 PM PDT 24
Peak memory 203792 kb
Host smart-73a6e068-bcf4-45e5-8acf-a8c877deea5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466670960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3466670960
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1825697374
Short name T1205
Test name
Test status
Simulation time 29223009479 ps
CPU time 11.33 seconds
Started May 05 01:10:33 PM PDT 24
Finished May 05 01:10:44 PM PDT 24
Peak memory 303512 kb
Host smart-212f0e82-6ac2-448e-a64d-95d3c1197ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825697374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1825697374
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3526276615
Short name T287
Test name
Test status
Simulation time 13761046050 ps
CPU time 616.35 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:20:47 PM PDT 24
Peak memory 1716028 kb
Host smart-53c9e334-be73-4351-b806-4df0056ddd30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526276615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3526276615
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.4245527014
Short name T963
Test name
Test status
Simulation time 5595923149 ps
CPU time 7.14 seconds
Started May 05 01:10:31 PM PDT 24
Finished May 05 01:10:39 PM PDT 24
Peak memory 203888 kb
Host smart-ac114ede-84a3-4aa2-85f8-6cb9a81dcb9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245527014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.4245527014
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2413525324
Short name T1325
Test name
Test status
Simulation time 19032662 ps
CPU time 0.62 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:10:48 PM PDT 24
Peak memory 203672 kb
Host smart-94d3d8e4-6da9-422d-8979-82040f9bdaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413525324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2413525324
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1109763659
Short name T977
Test name
Test status
Simulation time 475144420 ps
CPU time 2.09 seconds
Started May 05 01:10:43 PM PDT 24
Finished May 05 01:10:45 PM PDT 24
Peak memory 212056 kb
Host smart-e84b9852-8b9b-4780-a5f2-ce661704dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109763659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1109763659
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2160814042
Short name T122
Test name
Test status
Simulation time 1633744195 ps
CPU time 3.46 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:10:45 PM PDT 24
Peak memory 230084 kb
Host smart-bf41ef15-b149-43f4-8c93-1cb4f40f3015
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160814042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2160814042
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3786021825
Short name T936
Test name
Test status
Simulation time 5287067307 ps
CPU time 29.43 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:11:11 PM PDT 24
Peak memory 314940 kb
Host smart-38745cdd-40e2-4a71-b4ba-972c37314f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786021825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3786021825
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2647214945
Short name T791
Test name
Test status
Simulation time 2579759925 ps
CPU time 154.02 seconds
Started May 05 01:10:35 PM PDT 24
Finished May 05 01:13:10 PM PDT 24
Peak memory 711336 kb
Host smart-2aa6829d-b493-42d9-a655-25939034e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647214945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2647214945
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.634994115
Short name T434
Test name
Test status
Simulation time 102057987 ps
CPU time 0.78 seconds
Started May 05 01:10:37 PM PDT 24
Finished May 05 01:10:38 PM PDT 24
Peak memory 203684 kb
Host smart-4ce16ca1-5cbc-48f4-9157-1d3605730c5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634994115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.634994115
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2614143442
Short name T930
Test name
Test status
Simulation time 142615427 ps
CPU time 5.89 seconds
Started May 05 01:10:40 PM PDT 24
Finished May 05 01:10:46 PM PDT 24
Peak memory 203760 kb
Host smart-e12bcaea-3b7d-4944-89a5-ae471ced8302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614143442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2614143442
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2381401240
Short name T658
Test name
Test status
Simulation time 5727899876 ps
CPU time 83.64 seconds
Started May 05 01:10:36 PM PDT 24
Finished May 05 01:12:00 PM PDT 24
Peak memory 886388 kb
Host smart-e68d84e7-c802-47e8-9152-a5190b45f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381401240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2381401240
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2626050482
Short name T338
Test name
Test status
Simulation time 893402832 ps
CPU time 7.43 seconds
Started May 05 01:10:47 PM PDT 24
Finished May 05 01:10:55 PM PDT 24
Peak memory 203828 kb
Host smart-81b7ad4d-6d83-4225-83b6-4725f6514319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626050482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2626050482
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3653691132
Short name T546
Test name
Test status
Simulation time 5834393376 ps
CPU time 77.27 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:12:04 PM PDT 24
Peak memory 387160 kb
Host smart-8f7fad3e-8922-4542-9671-54efab48d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653691132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3653691132
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3521200979
Short name T42
Test name
Test status
Simulation time 24396077 ps
CPU time 0.66 seconds
Started May 05 01:10:36 PM PDT 24
Finished May 05 01:10:37 PM PDT 24
Peak memory 203648 kb
Host smart-ffe67e2f-6398-4ad8-8708-44a2b578a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521200979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3521200979
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2590399471
Short name T75
Test name
Test status
Simulation time 6530555799 ps
CPU time 131.09 seconds
Started May 05 01:10:40 PM PDT 24
Finished May 05 01:12:51 PM PDT 24
Peak memory 215956 kb
Host smart-83c102e2-ccd2-43ae-bfcd-0c2f44bc6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590399471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2590399471
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1281399899
Short name T697
Test name
Test status
Simulation time 2044539802 ps
CPU time 19.3 seconds
Started May 05 01:10:36 PM PDT 24
Finished May 05 01:10:56 PM PDT 24
Peak memory 286984 kb
Host smart-6299488c-e7cf-410a-bf66-0b2096c2c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281399899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1281399899
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.350780594
Short name T1244
Test name
Test status
Simulation time 4308748126 ps
CPU time 9.66 seconds
Started May 05 01:10:42 PM PDT 24
Finished May 05 01:10:52 PM PDT 24
Peak memory 220000 kb
Host smart-ede15fc3-b544-4730-a8c3-f52b2bfc146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350780594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.350780594
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3802100691
Short name T771
Test name
Test status
Simulation time 3312049113 ps
CPU time 3.97 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:10:54 PM PDT 24
Peak memory 211964 kb
Host smart-c299857f-d364-4f0d-a284-4d1b09735e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802100691 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3802100691
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2959789572
Short name T985
Test name
Test status
Simulation time 10098652082 ps
CPU time 34.16 seconds
Started May 05 01:10:45 PM PDT 24
Finished May 05 01:11:20 PM PDT 24
Peak memory 380828 kb
Host smart-18a2090b-3554-4643-9863-d3c4e47b25f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959789572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2959789572
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3769099793
Short name T738
Test name
Test status
Simulation time 480592411 ps
CPU time 2.6 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:10:53 PM PDT 24
Peak memory 203724 kb
Host smart-48473be3-0f91-47c4-b80a-f505e03ac266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769099793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3769099793
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3509516920
Short name T491
Test name
Test status
Simulation time 1437514983 ps
CPU time 5.68 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:10:47 PM PDT 24
Peak memory 216968 kb
Host smart-f909d195-ae88-4167-831d-6591bc84ce5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509516920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3509516920
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1832836824
Short name T356
Test name
Test status
Simulation time 16785883378 ps
CPU time 39.08 seconds
Started May 05 01:10:42 PM PDT 24
Finished May 05 01:11:22 PM PDT 24
Peak memory 976444 kb
Host smart-348457d4-9760-490c-8d91-235dc0c0af07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832836824 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1832836824
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2786269316
Short name T1097
Test name
Test status
Simulation time 4466506667 ps
CPU time 41.99 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:11:28 PM PDT 24
Peak memory 203776 kb
Host smart-69fab611-59a5-48d5-a705-ef14ec89c205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786269316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2786269316
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1893785068
Short name T375
Test name
Test status
Simulation time 1460024982 ps
CPU time 21 seconds
Started May 05 01:10:40 PM PDT 24
Finished May 05 01:11:01 PM PDT 24
Peak memory 228840 kb
Host smart-43b8c092-449f-482d-9ec7-6610180958cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893785068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1893785068
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2695056523
Short name T722
Test name
Test status
Simulation time 15711195037 ps
CPU time 8.5 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:10:49 PM PDT 24
Peak memory 203968 kb
Host smart-f9fa2bfe-29d8-4ef1-91af-e433aa71022e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695056523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2695056523
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3577837517
Short name T520
Test name
Test status
Simulation time 34905488254 ps
CPU time 596.06 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:20:38 PM PDT 24
Peak memory 1747424 kb
Host smart-cc6e908d-8848-45bb-8fa2-8cc76191d2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577837517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3577837517
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.952956178
Short name T1191
Test name
Test status
Simulation time 1189610506 ps
CPU time 6.8 seconds
Started May 05 01:10:41 PM PDT 24
Finished May 05 01:10:49 PM PDT 24
Peak memory 212844 kb
Host smart-2550d8f8-16dc-4d66-81fd-fde401c7e148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952956178 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.952956178
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1168048358
Short name T594
Test name
Test status
Simulation time 18168471 ps
CPU time 0.63 seconds
Started May 05 01:10:56 PM PDT 24
Finished May 05 01:10:57 PM PDT 24
Peak memory 203688 kb
Host smart-3ee40430-8751-442d-a06c-2112a04255e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168048358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1168048358
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2195861491
Short name T693
Test name
Test status
Simulation time 460307849 ps
CPU time 1.55 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:10:54 PM PDT 24
Peak memory 212140 kb
Host smart-d71e4440-7f54-4f9c-8ae6-3258c8e6a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195861491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2195861491
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.971369382
Short name T408
Test name
Test status
Simulation time 894807638 ps
CPU time 4.36 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:10:55 PM PDT 24
Peak memory 243088 kb
Host smart-816334c1-ecee-471a-8c7d-a77a61b85f7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971369382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.971369382
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2084782686
Short name T931
Test name
Test status
Simulation time 2985241667 ps
CPU time 41.38 seconds
Started May 05 01:10:47 PM PDT 24
Finished May 05 01:11:29 PM PDT 24
Peak memory 561444 kb
Host smart-de91fbfb-c7d5-46d6-b972-92b47c4c1ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084782686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2084782686
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.24935426
Short name T1350
Test name
Test status
Simulation time 2200290671 ps
CPU time 64.23 seconds
Started May 05 01:10:47 PM PDT 24
Finished May 05 01:11:52 PM PDT 24
Peak memory 691164 kb
Host smart-25e424e8-c135-40ea-80db-c3d674fc9339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24935426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.24935426
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.61825874
Short name T519
Test name
Test status
Simulation time 94572978 ps
CPU time 0.94 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:10:48 PM PDT 24
Peak memory 203696 kb
Host smart-d45cfb1a-d3a9-42bf-a627-6058a6b48f11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61825874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.61825874
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.11283203
Short name T92
Test name
Test status
Simulation time 159570278 ps
CPU time 3.34 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:10:50 PM PDT 24
Peak memory 203788 kb
Host smart-f93fad83-e0ae-4d97-a954-107ceb8ce444
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11283203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.11283203
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.169035863
Short name T1074
Test name
Test status
Simulation time 3675494331 ps
CPU time 86.36 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:12:13 PM PDT 24
Peak memory 1096440 kb
Host smart-b3d7e699-0888-4ff5-9552-1d90c037f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169035863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.169035863
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2077282849
Short name T860
Test name
Test status
Simulation time 1192982149 ps
CPU time 9.04 seconds
Started May 05 01:10:56 PM PDT 24
Finished May 05 01:11:05 PM PDT 24
Peak memory 203880 kb
Host smart-6f2d38ca-41f8-4394-9c8e-4ae9edb5fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077282849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2077282849
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.678764469
Short name T65
Test name
Test status
Simulation time 5416889751 ps
CPU time 18.46 seconds
Started May 05 01:10:55 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 327796 kb
Host smart-8bb2fedf-8cec-48c3-b76c-c9d44db4f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678764469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.678764469
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2893690430
Short name T952
Test name
Test status
Simulation time 88553362 ps
CPU time 0.65 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:10:47 PM PDT 24
Peak memory 203656 kb
Host smart-094b11c2-172c-48fb-b382-97be1f4997bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893690430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2893690430
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3797352554
Short name T719
Test name
Test status
Simulation time 25439266774 ps
CPU time 184.22 seconds
Started May 05 01:10:45 PM PDT 24
Finished May 05 01:13:50 PM PDT 24
Peak memory 203948 kb
Host smart-dcaf1848-21df-437d-a388-5ea59cec30e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797352554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3797352554
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2493156846
Short name T1296
Test name
Test status
Simulation time 3205283812 ps
CPU time 75.26 seconds
Started May 05 01:10:46 PM PDT 24
Finished May 05 01:12:01 PM PDT 24
Peak memory 331804 kb
Host smart-a6fa0a48-2304-4f27-a3b7-2b9479aa9c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493156846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2493156846
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2394360130
Short name T843
Test name
Test status
Simulation time 575523746 ps
CPU time 26.3 seconds
Started May 05 01:10:47 PM PDT 24
Finished May 05 01:11:14 PM PDT 24
Peak memory 212104 kb
Host smart-0a617f31-8693-44e4-a9c1-55d13043b137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394360130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2394360130
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.828211749
Short name T772
Test name
Test status
Simulation time 972011106 ps
CPU time 4.36 seconds
Started May 05 01:10:57 PM PDT 24
Finished May 05 01:11:02 PM PDT 24
Peak memory 212056 kb
Host smart-dd6e3511-84bd-4a5d-8418-fe3b9cb7ba14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828211749 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.828211749
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.52341434
Short name T31
Test name
Test status
Simulation time 10283381056 ps
CPU time 13.91 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:11:06 PM PDT 24
Peak memory 258480 kb
Host smart-c891b322-c5f4-4acb-b2e4-7750a2f65374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52341434 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_acq.52341434
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1171822858
Short name T958
Test name
Test status
Simulation time 10221305788 ps
CPU time 14.97 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:11:06 PM PDT 24
Peak memory 307904 kb
Host smart-abff623c-201d-4a3a-8320-e0141331a337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171822858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1171822858
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.988587077
Short name T659
Test name
Test status
Simulation time 2423901399 ps
CPU time 2.71 seconds
Started May 05 01:10:55 PM PDT 24
Finished May 05 01:10:58 PM PDT 24
Peak memory 203860 kb
Host smart-f43427ea-eb85-40c2-a17f-bf626250214e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988587077 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.988587077
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.157978983
Short name T254
Test name
Test status
Simulation time 1258999553 ps
CPU time 4.69 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:10:55 PM PDT 24
Peak memory 207556 kb
Host smart-b8478de8-34bf-44df-b8b3-5ae078f03b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157978983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.157978983
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.161789276
Short name T327
Test name
Test status
Simulation time 9435682376 ps
CPU time 6.73 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:10:58 PM PDT 24
Peak memory 204060 kb
Host smart-45856b70-141f-494e-a96b-94b1a2c719e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161789276 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.161789276
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.22332520
Short name T1159
Test name
Test status
Simulation time 2497490287 ps
CPU time 47.72 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:11:39 PM PDT 24
Peak memory 203864 kb
Host smart-c5605b41-a4e5-4947-be73-755fd6223ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targe
t_smoke.22332520
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1281519204
Short name T585
Test name
Test status
Simulation time 314422866 ps
CPU time 5.67 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:10:58 PM PDT 24
Peak memory 203784 kb
Host smart-22cecf57-5672-4c6d-abb3-816b8591453b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281519204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1281519204
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2415906934
Short name T720
Test name
Test status
Simulation time 38029760739 ps
CPU time 178.29 seconds
Started May 05 01:10:51 PM PDT 24
Finished May 05 01:13:50 PM PDT 24
Peak memory 2303212 kb
Host smart-dc4ce188-43db-4edb-94b6-88da74202096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415906934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2415906934
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2376720115
Short name T530
Test name
Test status
Simulation time 21486413910 ps
CPU time 152.58 seconds
Started May 05 01:10:50 PM PDT 24
Finished May 05 01:13:24 PM PDT 24
Peak memory 1317428 kb
Host smart-086b495c-3179-4425-9abc-96279d3d9696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376720115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2376720115
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3887864562
Short name T1339
Test name
Test status
Simulation time 1137600636 ps
CPU time 6.92 seconds
Started May 05 01:10:49 PM PDT 24
Finished May 05 01:10:57 PM PDT 24
Peak memory 220076 kb
Host smart-d49aadf3-879a-48e5-8755-941d26b9491b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887864562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3887864562
Directory /workspace/9.i2c_target_timeout/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%