Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

171176

1

T2

44

T5

51

T6

230

ack

15056

1

T2

2

T5

5

T6

40

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	712	1			T5	1		T6	2		T7	1
high	38093	1			T2	8		T5	13		T6	62
med	69294	1			T2	15		T5	17		T6	98
sml	77382	1			T2	23		T5	25		T6	105
all_zero	751	1			T6	3		T7	1		T39	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92506

1

T2

20

T5

25

T6

115

auto[1]

93726

1

T2

26

T5

31

T6

155

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127723

1

T2

28

T5

38

T6

212

auto[1]

58509

1

T2

18

T5

18

T6

58

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178134

1

T2

35

T5

47

T6

254

auto[1]

8098

1

T2

11

T5

9

T6

16

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175928

1

T2

41

T5

48

T6

237

auto[1]

10304

1

T2

5

T5

8

T6

33

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176805

1

T2

42

T5

50

T6

238

auto[1]

9427

1

T2

4

T5

6

T6

32

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92506

1

T2

20

T5

25

T6

115

auto[1]

93726

1

T2

26

T5

31

T6

155

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127723

1

T2

28

T5

38

T6

212

auto[1]

58509

1

T2

18

T5

18

T6

58

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178134

1

T2

35

T5

47

T6

254

auto[1]

8098

1

T2

11

T5

9

T6

16

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175928

1

T2

41

T5

48

T6

237

auto[1]

10304

1

T2

5

T5

8

T6

33

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

176805

1

T2

42

T5

50

T6

238

auto[1]

9427

1

T2

4

T5

6

T6

32

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

6

1

T5

1

T238

1

T239

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T240

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T241

1

T242

1

T243

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

345

1

T2

1

T5

1

T6

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

175

1

T6

2

T62

2

T43

3

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

157

1

T6

1

T62

2

T43

6

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

585

1

T6

7

T39

1

T60

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

276

1

T6

1

T62

3

T43

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

284

1

T6

1

T61

3

T62

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

581

1

T6

5

T78

1

T61

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

296

1

T6

1

T61

1

T62

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

290

1

T5

1

T6

2

T39

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T62

1

T95

1

T244

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

7

1

T43

1

T64

1

T245

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T246

1

T247

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	54026	1			T2	8		T5	12		T6	63
write_address_byte	10304	1			T2	5		T5	8		T6	33
read_with_ack	2356	1			T2	7		T5	5		T39	1
read_with_nack	5742	1			T2	4		T5	4		T6	16
stop_byte	9427	1			T2	4		T5	6		T6	32
write_address_byte_nak	5314	1			T2	4		T5	8		T6	26
data_byte_nack	171176	1			T2	44		T5	51		T6	230
stop_byte_nack	5691	1			T2	4		T5	6		T6	24
nakok_byte_nack	86179	1			T2	24		T5	28		T6	127
nakok_addr_byte_nack	2672	1			T2	1		T5	5		T6	13