Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42212380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10464101

1

T1

73

T2

1215

T3

242

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51734556	1			T1	135		T2	4285		T3	697
values[0x0]	470853	1			T1	40		T2	106		T3	90
values[0x1]	471072	1			T1	43		T2	136		T3	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30201231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22475250

1

T1

110

T2

2158

T3

421

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	245775	1			T2	3		T5	37		T6	953
valid_sources[0x01]	199429	1			T2	3		T5	25		T7	9
valid_sources[0x02]	182163	1			T2	214		T5	14		T7	22
valid_sources[0x03]	179538	1			T2	1		T5	30		T6	568
valid_sources[0x04]	293246	1			T1	1		T2	1		T5	18
valid_sources[0x05]	190986	1			T5	26		T6	34		T7	12
valid_sources[0x06]	189407	1			T1	26		T5	5		T7	827
valid_sources[0x07]	247863	1			T5	26		T7	19		T8	8
valid_sources[0x08]	178370	1			T5	13		T7	30		T8	14
valid_sources[0x09]	191097	1			T2	105		T5	17		T7	6
valid_sources[0x0a]	181823	1			T2	2		T5	25		T7	16
valid_sources[0x0b]	182999	1			T1	6		T2	5		T3	1
valid_sources[0x0c]	193860	1			T5	12		T6	143		T7	123
valid_sources[0x0d]	186196	1			T5	7		T7	23		T8	5
valid_sources[0x0e]	200396	1			T2	2		T5	11		T6	78
valid_sources[0x0f]	202559	1			T2	1		T5	9		T7	1505
valid_sources[0x10]	519972	1			T5	15		T7	18		T8	6
valid_sources[0x11]	195328	1			T5	48		T7	1		T8	5
valid_sources[0x12]	201743	1			T2	3		T5	11		T7	850
valid_sources[0x13]	200350	1			T5	29		T6	93		T7	2
valid_sources[0x14]	195350	1			T2	2		T5	28		T7	12
valid_sources[0x15]	194610	1			T2	3		T5	16		T7	13
valid_sources[0x16]	202891	1			T2	2		T5	4		T7	243
valid_sources[0x17]	196329	1			T5	20		T7	23		T8	7
valid_sources[0x18]	200370	1			T2	2		T5	17		T7	258
valid_sources[0x19]	195648	1			T2	1		T5	4		T7	131
valid_sources[0x1a]	178304	1			T2	1		T3	1		T5	11
valid_sources[0x1b]	191837	1			T2	1		T5	21		T6	31
valid_sources[0x1c]	237886	1			T2	6		T5	20		T6	84
valid_sources[0x1d]	316754	1			T5	12		T7	11		T8	4
valid_sources[0x1e]	233359	1			T2	1		T5	23		T7	5
valid_sources[0x1f]	213603	1			T3	103		T5	21		T7	21
valid_sources[0x20]	257544	1			T2	1		T5	17		T7	697
valid_sources[0x21]	182445	1			T4	111		T5	17		T6	78
valid_sources[0x22]	204678	1			T5	28		T7	23		T8	4
valid_sources[0x23]	210023	1			T2	1		T4	104		T5	8
valid_sources[0x24]	189745	1			T2	8		T5	13		T7	133
valid_sources[0x25]	188058	1			T2	1		T5	30		T7	1855
valid_sources[0x26]	192186	1			T2	1		T5	25		T7	20
valid_sources[0x27]	213121	1			T3	120		T5	13		T7	1924
valid_sources[0x28]	220363	1			T2	4		T5	13		T6	46
valid_sources[0x29]	196562	1			T2	2		T3	1		T5	4
valid_sources[0x2a]	184901	1			T5	19		T7	12		T8	3
valid_sources[0x2b]	287428	1			T2	1		T5	41		T6	54
valid_sources[0x2c]	259039	1			T5	9		T7	19		T8	9
valid_sources[0x2d]	177923	1			T2	1		T5	4		T7	15
valid_sources[0x2e]	198971	1			T2	1		T5	5		T6	70
valid_sources[0x2f]	307827	1			T2	1		T5	16		T6	20
valid_sources[0x30]	208637	1			T5	25		T7	1162		T8	10
valid_sources[0x31]	190010	1			T1	7		T2	1		T5	17
valid_sources[0x32]	194294	1			T2	8		T3	1		T5	12
valid_sources[0x33]	181609	1			T2	1		T5	12		T7	15
valid_sources[0x34]	202932	1			T5	16		T7	5		T8	7
valid_sources[0x35]	199034	1			T3	96		T5	34		T7	13
valid_sources[0x36]	191464	1			T5	21		T7	13		T8	7
valid_sources[0x37]	255917	1			T2	1		T4	2		T5	33
valid_sources[0x38]	188932	1			T2	1		T5	31		T7	11
valid_sources[0x39]	189588	1			T5	20		T8	4		T10	4
valid_sources[0x3a]	195666	1			T2	1		T5	16		T6	202
valid_sources[0x3b]	209026	1			T2	2		T5	46		T7	9
valid_sources[0x3c]	212606	1			T2	2		T5	26		T7	2
valid_sources[0x3d]	205145	1			T2	102		T5	9		T7	29
valid_sources[0x3e]	197440	1			T2	1		T5	28		T6	72
valid_sources[0x3f]	209021	1			T5	6		T7	55		T8	12
valid_sources[0x40]	199345	1			T2	1		T5	19		T7	8
valid_sources[0x41]	206615	1			T2	3		T5	35		T6	408
valid_sources[0x42]	190323	1			T2	1		T3	1		T5	13
valid_sources[0x43]	213825	1			T2	5		T5	15		T7	8
valid_sources[0x44]	194103	1			T1	9		T2	2		T5	28
valid_sources[0x45]	394007	1			T2	2		T5	50		T6	41
valid_sources[0x46]	200497	1			T2	3		T3	106		T5	20
valid_sources[0x47]	188407	1			T2	1		T5	20		T7	1810
valid_sources[0x48]	218177	1			T2	1		T5	10		T7	8
valid_sources[0x49]	190651	1			T5	11		T7	125		T8	4
valid_sources[0x4a]	192338	1			T5	26		T7	3		T8	11
valid_sources[0x4b]	178564	1			T1	1		T2	1		T5	15
valid_sources[0x4c]	182198	1			T5	10		T7	12		T8	5
valid_sources[0x4d]	217064	1			T2	1		T3	2		T5	4
valid_sources[0x4e]	191870	1			T2	2		T5	54		T7	1603
valid_sources[0x4f]	184311	1			T2	2		T3	60		T5	23
valid_sources[0x50]	209578	1			T2	9		T5	14		T7	4
valid_sources[0x51]	213077	1			T1	1		T3	1		T5	18
valid_sources[0x52]	192173	1			T1	5		T2	1		T5	20
valid_sources[0x53]	197255	1			T2	2		T5	30		T7	4
valid_sources[0x54]	185283	1			T5	9		T7	1162		T8	2
valid_sources[0x55]	182549	1			T1	1		T2	294		T5	27
valid_sources[0x56]	190822	1			T2	1		T5	31		T7	4
valid_sources[0x57]	202160	1			T2	3		T5	13		T7	10
valid_sources[0x58]	189294	1			T2	7		T5	21		T7	13
valid_sources[0x59]	298687	1			T5	14		T6	172		T7	1
valid_sources[0x5a]	200637	1			T2	1		T5	20		T7	1857
valid_sources[0x5b]	188669	1			T2	1		T3	1		T5	17
valid_sources[0x5c]	193918	1			T2	1		T5	29		T7	12
valid_sources[0x5d]	209794	1			T2	1		T4	141		T5	28
valid_sources[0x5e]	186124	1			T5	40		T6	165		T7	960
valid_sources[0x5f]	184870	1			T5	39		T7	9		T8	15
valid_sources[0x60]	184233	1			T2	1		T5	7		T7	273
valid_sources[0x61]	207610	1			T3	1		T5	38		T7	242
valid_sources[0x62]	193965	1			T5	17		T7	8		T8	2
valid_sources[0x63]	174906	1			T2	2		T3	1		T5	2
valid_sources[0x64]	257606	1			T2	2		T5	1		T6	39
valid_sources[0x65]	195097	1			T2	1		T5	18		T7	15
valid_sources[0x66]	207583	1			T2	1		T5	21		T7	3233
valid_sources[0x67]	182366	1			T1	1		T5	8		T7	6
valid_sources[0x68]	226353	1			T5	23		T7	2		T8	1
valid_sources[0x69]	187597	1			T2	1		T5	29		T7	8
valid_sources[0x6a]	203899	1			T2	1		T5	12		T6	81
valid_sources[0x6b]	210275	1			T2	1		T5	32		T7	1571
valid_sources[0x6c]	184667	1			T5	14		T7	23		T8	6
valid_sources[0x6d]	200988	1			T3	1		T5	29		T7	24
valid_sources[0x6e]	197306	1			T2	5		T5	34		T7	143
valid_sources[0x6f]	187272	1			T4	76		T5	15		T6	70
valid_sources[0x70]	193719	1			T2	1		T5	20		T7	4
valid_sources[0x71]	205582	1			T3	1		T5	17		T6	222
valid_sources[0x72]	206813	1			T1	4		T2	1		T5	16
valid_sources[0x73]	200816	1			T3	1		T5	22		T7	13
valid_sources[0x74]	207227	1			T5	7		T7	373		T8	8
valid_sources[0x75]	217738	1			T3	35		T5	8		T7	14
valid_sources[0x76]	195174	1			T2	9		T3	1		T5	23
valid_sources[0x77]	196779	1			T2	1		T5	20		T7	484
valid_sources[0x78]	324439	1			T7	16		T8	8		T10	3
valid_sources[0x79]	183490	1			T5	19		T6	37		T7	31
valid_sources[0x7a]	196847	1			T5	22		T7	1030		T8	4
valid_sources[0x7b]	193404	1			T5	5		T7	3		T8	3
valid_sources[0x7c]	189712	1			T1	1		T2	1		T5	39
valid_sources[0x7d]	199421	1			T2	1		T5	22		T7	10
valid_sources[0x7e]	206554	1			T5	15		T7	10		T8	7
valid_sources[0x7f]	195941	1			T2	4		T5	14		T7	8
valid_sources[0x80]	200015	1			T1	16		T2	4		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10048218

1

T1

12

T2

1084

T3

127

values[0x0]

all_enables

biggest_size

245368

1

T1

32

T2

66

T3

63

values[0x1]

all_enables

biggest_size

170515

1

T1

29

T2

65

T3

52