Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	100.00						100.00

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	411095370	6006	0	0
ctrl_rd_A	411095370	2779	0	0
host_fifo_config_rd_A	411095370	5882	0	0
host_nack_handler_timeout_rd_A	411095370	1722	0	0
host_timeout_ctrl_rd_A	411095370	1578	0	0
intr_enable_rd_A	411095370	4583	0	0
ovrd_rd_A	411095370	2522	0	0
target_fifo_config_rd_A	411095370	2019	0	0
target_id_rd_A	411095370	2215	0	0
target_timeout_ctrl_rd_A	411095370	1805	0	0
timeout_ctrl_rd_A	411095370	1990	0	0
timing0_rd_A	411095370	1771	0	0
timing1_rd_A	411095370	1819	0	0
timing2_rd_A	411095370	1771	0	0
timing3_rd_A	411095370	1720	0	0
timing4_rd_A	411095370	1780	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	6006	0	0
T92	2233	4	0	0
T122	3089	277	0	0
T123	5094	151	0	0
T135	14084	1	0	0
T136	6649	179	0	0
T137	13542	1	0	0
T140	3121	33	0	0
T141	1618	67	0	0
T158	2834	8	0	0
T159	2347	10	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	2779	0	0
T92	2233	15	0	0
T134	7919	231	0	0
T135	14084	300	0	0
T137	13542	153	0	0
T158	2834	6	0	0
T159	2347	3	0	0
T162	1958	1	0	0
T174	3367	3	0	0
T175	6092	28	0	0
T182	6664	44	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	5882	0	0
T43	413638	359	0	0
T51	135968	0	0	0
T71	114976	0	0	0
T72	955342	0	0	0
T94	0	112	0	0
T96	0	339	0	0
T99	497207	0	0	0
T102	108575	0	0	0
T119	1037	0	0	0
T183	0	196	0	0
T184	0	247	0	0
T185	0	421	0	0
T186	0	104	0	0
T187	0	165	0	0
T188	0	186	0	0
T189	0	84	0	0
T190	101958	0	0	0
T191	32579	0	0	0
T192	38924	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1722	0	0
T92	2233	4	0	0
T134	7919	55	0	0
T135	14084	90	0	0
T137	13542	68	0	0
T158	2834	10	0	0
T159	2347	8	0	0
T162	1958	3	0	0
T174	3367	13	0	0
T175	6092	15	0	0
T182	6664	79	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1578	0	0
T92	2233	7	0	0
T134	7919	50	0	0
T135	14084	80	0	0
T137	13542	50	0	0
T158	2834	19	0	0
T159	2347	17	0	0
T162	1958	3	0	0
T174	3367	24	0	0
T175	6092	19	0	0
T182	6664	66	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	4583	0	0
T32	93450	0	0	0
T92	0	9	0	0
T94	983730	9	0	0
T96	0	36	0	0
T104	267034	0	0	0
T120	626	0	0	0
T134	0	223	0	0
T135	0	525	0	0
T174	0	54	0	0
T185	0	11	0	0
T193	0	22	0	0
T194	0	11	0	0
T195	0	31	0	0
T196	73470	0	0	0
T197	129285	0	0	0
T198	11917	0	0	0
T199	158914	0	0	0
T200	233745	0	0	0
T201	51061	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	2522	0	0
T24	53524	0	0	0
T43	413638	0	0	0
T52	2462	48	0	0
T53	0	38	0	0
T55	0	50	0	0
T56	1307	0	0	0
T58	185754	0	0	0
T59	108528	0	0	0
T62	390019	0	0	0
T71	114976	0	0	0
T100	493814	0	0	0
T202	0	43	0	0
T203	0	25	0	0
T204	0	49	0	0
T205	0	46	0	0
T206	0	55	0	0
T207	0	77	0	0
T208	0	62	0	0
T209	30344	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	2019	0	0
T92	2233	5	0	0
T134	7919	102	0	0
T135	14084	152	0	0
T137	13542	69	0	0
T158	2834	22	0	0
T159	2347	5	0	0
T164	1444	18	0	0
T174	3367	15	0	0
T175	6092	62	0	0
T182	6664	53	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	2215	0	0
T92	2233	2	0	0
T134	7919	101	0	0
T135	14084	151	0	0
T137	13542	98	0	0
T158	2834	5	0	0
T159	2347	7	0	0
T162	1958	4	0	0
T174	3367	10	0	0
T175	6092	16	0	0
T182	6664	80	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1805	0	0
T92	2233	3	0	0
T134	7919	36	0	0
T135	14084	97	0	0
T137	13542	73	0	0
T158	2834	22	0	0
T159	2347	7	0	0
T162	1958	1	0	0
T174	3367	46	0	0
T175	6092	39	0	0
T182	6664	46	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1990	0	0
T92	2233	14	0	0
T134	7919	74	0	0
T135	14084	141	0	0
T137	13542	79	0	0
T158	2834	19	0	0
T159	2347	24	0	0
T162	1958	10	0	0
T174	3367	11	0	0
T175	6092	75	0	0
T182	6664	52	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1771	0	0
T92	2233	6	0	0
T134	7919	57	0	0
T135	14084	126	0	0
T137	13542	66	0	0
T158	2834	20	0	0
T159	2347	10	0	0
T162	1958	8	0	0
T174	3367	19	0	0
T175	6092	9	0	0
T182	6664	63	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1819	0	0
T134	7919	46	0	0
T135	14084	117	0	0
T137	13542	45	0	0
T158	2834	10	0	0
T159	2347	10	0	0
T162	1958	7	0	0
T164	1444	9	0	0
T174	3367	14	0	0
T175	6092	42	0	0
T182	6664	44	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1771	0	0
T134	7919	75	0	0
T135	14084	128	0	0
T137	13542	65	0	0
T158	2834	14	0	0
T159	2347	15	0	0
T164	1444	9	0	0
T165	10327	74	0	0
T174	3367	46	0	0
T175	6092	49	0	0
T182	6664	63	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1720	0	0
T92	2233	1	0	0
T134	7919	54	0	0
T135	14084	107	0	0
T137	13542	59	0	0
T158	2834	8	0	0
T159	2347	10	0	0
T162	1958	17	0	0
T174	3367	8	0	0
T175	6092	34	0	0
T182	6664	51	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411095370	1780	0	0
T92	2233	7	0	0
T134	7919	45	0	0
T135	14084	145	0	0
T137	13542	89	0	0
T158	2834	7	0	0
T159	2347	9	0	0
T162	1958	2	0	0
T174	3367	9	0	0
T175	6092	51	0	0
T182	6664	41	0	0