Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.59	92.59	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	92.59	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	4	23	85.19

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	4	23	85.19	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

189483

1

T2

1478

T37

6

T50

354

ack

15373

1

T2

141

T10

15

T47

44

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	706	1			T2	6		T50	1		T85	4
high	42184	1			T2	357		T10	3		T47	3
med	76382	1			T2	579		T10	2		T47	7
sml	84795	1			T2	671		T10	10		T47	34
all_zero	789	1			T2	6		T50	1		T86	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102299

1

T2

808

T10

5

T47

20

auto[1]

102557

1

T2

811

T10

10

T47

24

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140649

1

T2

1156

T10

15

T47

26

auto[1]

64207

1

T2

463

T47

18

T37

3

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196769

1

T2

1555

T10

8

T47

13

auto[1]

8087

1

T2

64

T10

7

T47

31

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193942

1

T2

1504

T10

7

T47

31

auto[1]

10914

1

T2

115

T10

8

T47

13

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194846

1

T2

1509

T10

8

T47

31

auto[1]

10010

1

T2

110

T10

7

T47

13

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102299

1

T2

808

T10

5

T47

20

auto[1]

102557

1

T2

811

T10

10

T47

24

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140649

1

T2

1156

T10

15

T47

26

auto[1]

64207

1

T2

463

T47

18

T37

3

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196769

1

T2

1555

T10

8

T47

13

auto[1]

8087

1

T2

64

T10

7

T47

31

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193942

1

T2

1504

T10

7

T47

31

auto[1]

10914

1

T2

115

T10

8

T47

13

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194846

1

T2

1509

T10

8

T47

31

auto[1]

10010

1

T2

110

T10

7

T47

13

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	4	23	85.19	2
Automatically Generated Cross Bins	15	2	13	86.67	2
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

cp_fbyte	start	stop	read	rcont	nakok	cp_ack	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[ack]	0	1	1
[all_zero]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[ack]	0	1	1

Covered bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

3

1

T220

1

T221

1

T222

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T106

1

T223

1

T224

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

327

1

T2

3

T50

1

T51

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

180

1

T2

3

T50

1

T85

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

187

1

T2

2

T51

1

T85

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

658

1

T2

9

T85

1

T97

3

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

330

1

T2

4

T85

1

T97

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

325

1

T2

5

T85

2

T98

5

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

617

1

T2

6

T37

1

T85

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

321

1

T2

4

T85

2

T97

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

335

1

T2

3

T37

1

T85

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

20

1

T2

1

T52

1

T225

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

5

1

T226

1

T227

1

T110

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	60450	1			T2	471		T37	1		T50	114
write_address_byte	10914	1			T2	115		T10	8		T47	13
read_with_ack	2175	1			T47	18		T50	5		T51	2
read_with_nack	5912	1			T2	64		T10	7		T47	13
stop_byte	10010	1			T2	110		T10	7		T47	13
write_address_byte_nak	5977	1			T2	72		T37	2		T50	7
data_byte_nack	189483	1			T2	1478		T37	6		T50	354
stop_byte_nack	6327	1			T2	72		T50	7		T51	4
nakok_byte_nack	94846	1			T2	748		T37	4		T50	176
nakok_addr_byte_nack	2998	1			T2	37		T37	1		T50	4