Unified Coverage Report :: Group :: i2c_env_pkg::i2c_status_cg

Group : i2c_env_pkg::i2c_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.status_cg	100.00	1	100	1	64	64

---

Group Instance : i2c_env_pkg.status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group Instance i2c_env_pkg.status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acqempty	2	0	2	100.00	100	1	1	2
cp_acqfull	2	0	2	100.00	100	1	1	2
cp_fmtempty	2	0	2	100.00	100	1	1	2
cp_fmtfull	2	0	2	100.00	100	1	1	2
cp_hostidle	2	0	2	100.00	100	1	1	2
cp_rxempty	2	0	2	100.00	100	1	1	2
cp_rxfull	2	0	2	100.00	100	1	1	2
cp_targetidle	2	0	2	100.00	100	1	1	2
cp_txempty	2	0	2	100.00	100	1	1	2
cp_txfull	2	0	2	100.00	100	1	1	2

Summary for Variable cp_acqempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11044504

1

T1

446

T3

407

T4

386

auto[1]

39375802

1

T1

23

T2

683910

T3

40

---

Summary for Variable cp_acqfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50404268

1

T1

469

T2

683910

T3

447

auto[1]

16038

1

T4

112

T17

358

T18

181

---

Summary for Variable cp_fmtempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37789788

1

T2

678764

T10

14623

T47

14458

auto[1]

12630518

1

T1

469

T2

5146

T3

447

---

Summary for Variable cp_fmtfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46255200

1

T1

469

T2

476632

T3

447

auto[1]

4165106

1

T2

207278

T50

545

T51

10417

---

Summary for Variable cp_hostidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_hostidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37787415

1

T2

678734

T10

14623

T47

14458

auto[1]

12632891

1

T1

469

T2

5176

T3

447

---

Summary for Variable cp_rxempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8859854

1

T2

254981

T10

15162

T47

2562

auto[1]

41560452

1

T1

469

T2

428929

T3

447

---

Summary for Variable cp_rxfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50355869

1

T1

469

T2

680831

T3

447

auto[1]

64437

1

T2

3079

T10

265

T50

4

---

Summary for Variable cp_targetidle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_targetidle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12165717

1

T1

428

T3

427

T4

120

auto[1]

38254589

1

T1

41

T2

683910

T3

20

---

Summary for Variable cp_txempty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txempty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12083104

1

T1

281

T3

302

T6

241

auto[1]

38337202

1

T1

188

T2

683910

T3

145

---

Summary for Variable cp_txfull

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txfull

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49981408

1

T1

469

T2

683910

T3

447

auto[1]

438898

1

T6

25

T29

5026

T49

47