Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445298415	0	0	0
ctrl_rd_A	445298415	2568	0	0
host_fifo_config_rd_A	445298415	7591	0	0
host_nack_handler_timeout_rd_A	445298415	1998	0	0
host_timeout_ctrl_rd_A	445298415	1996	0	0
intr_enable_rd_A	445298415	4154	0	0
ovrd_rd_A	445298415	2768	0	0
target_fifo_config_rd_A	445298415	1958	0	0
target_id_rd_A	445298415	2345	0	0
target_timeout_ctrl_rd_A	445298415	1922	0	0
timeout_ctrl_rd_A	445298415	2140	0	0
timing0_rd_A	445298415	2040	0	0
timing1_rd_A	445298415	1841	0	0
timing2_rd_A	445298415	1861	0	0
timing3_rd_A	445298415	1904	0	0
timing4_rd_A	445298415	1914	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	2568	0	0
T87	7651	99	0	0
T88	3134	24	0	0
T89	2355	31	0	0
T90	7815	14	0	0
T91	3922	66	0	0
T92	8412	146	0	0
T93	3053	30	0	0
T94	15751	289	0	0
T95	12898	22	0	0
T96	1518	7	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	7591	0	0
T18	117969	0	0	0
T24	29940	0	0	0
T30	42923	0	0	0
T31	889559	0	0	0
T32	131567	0	0	0
T43	2000	0	0	0
T46	13073	0	0	0
T63	0	155	0	0
T82	0	157	0	0
T85	315109	110	0	0
T97	0	80	0	0
T98	0	208	0	0
T99	0	52	0	0
T100	0	116	0	0
T101	0	222	0	0
T102	0	174	0	0
T103	0	171	0	0
T104	112017	0	0	0
T105	1227	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1998	0	0
T87	7651	66	0	0
T88	3134	23	0	0
T89	2355	13	0	0
T90	7815	2	0	0
T91	3922	22	0	0
T92	8412	43	0	0
T93	3053	5	0	0
T94	15751	124	0	0
T95	12898	58	0	0
T96	1518	10	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1996	0	0
T87	7651	41	0	0
T88	3134	7	0	0
T89	2355	7	0	0
T90	7815	18	0	0
T91	3922	12	0	0
T92	8412	34	0	0
T93	3053	10	0	0
T94	15751	89	0	0
T95	12898	59	0	0
T96	1518	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	4154	0	0
T39	161627	0	0	0
T63	114862	11	0	0
T73	71931	0	0	0
T82	0	20	0	0
T99	0	12	0	0
T101	0	37	0	0
T106	0	14	0	0
T107	0	18	0	0
T108	0	62	0	0
T109	0	26	0	0
T110	0	24	0	0
T111	0	14	0	0
T112	133053	0	0	0
T113	159877	0	0	0
T114	1874	0	0	0
T115	865	0	0	0
T116	1964	0	0	0
T117	38963	0	0	0
T118	112480	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	2768	0	0
T39	161627	0	0	0
T99	660033	0	0	0
T116	1964	36	0	0
T117	38963	0	0	0
T118	112480	0	0	0
T119	0	49	0	0
T120	0	70	0	0
T121	0	20	0	0
T122	0	58	0	0
T123	0	35	0	0
T124	0	28	0	0
T125	0	30	0	0
T126	0	28	0	0
T127	0	39	0	0
T128	49867	0	0	0
T129	330878	0	0	0
T130	156042	0	0	0
T131	74933	0	0	0
T132	33112	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1958	0	0
T87	7651	56	0	0
T88	3134	13	0	0
T89	2355	3	0	0
T90	7815	15	0	0
T91	3922	8	0	0
T92	8412	43	0	0
T93	3053	16	0	0
T94	15751	106	0	0
T95	12898	66	0	0
T96	1518	6	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	2345	0	0
T87	7651	86	0	0
T88	3134	10	0	0
T89	2355	2	0	0
T90	7815	15	0	0
T91	3922	28	0	0
T92	8412	128	0	0
T93	3053	9	0	0
T94	15751	216	0	0
T95	12898	34	0	0
T96	1518	23	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1922	0	0
T87	7651	62	0	0
T88	3134	22	0	0
T89	2355	15	0	0
T90	7815	18	0	0
T91	3922	28	0	0
T92	8412	50	0	0
T93	3053	8	0	0
T94	15751	118	0	0
T95	12898	16	0	0
T96	1518	15	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	2140	0	0
T87	7651	54	0	0
T88	3134	33	0	0
T90	7815	27	0	0
T91	3922	18	0	0
T92	8412	66	0	0
T93	3053	5	0	0
T94	15751	153	0	0
T95	12898	20	0	0
T96	1518	3	0	0
T133	6444	49	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	2040	0	0
T87	7651	62	0	0
T88	3134	26	0	0
T90	7815	6	0	0
T91	3922	18	0	0
T92	8412	91	0	0
T93	3053	9	0	0
T94	15751	114	0	0
T95	12898	38	0	0
T96	1518	10	0	0
T133	6444	26	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1841	0	0
T87	7651	79	0	0
T88	3134	26	0	0
T89	2355	3	0	0
T91	3922	10	0	0
T92	8412	44	0	0
T93	3053	8	0	0
T94	15751	132	0	0
T95	12898	27	0	0
T96	1518	4	0	0
T133	6444	35	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1861	0	0
T87	7651	67	0	0
T88	3134	17	0	0
T89	2355	4	0	0
T90	7815	5	0	0
T91	3922	27	0	0
T92	8412	57	0	0
T93	3053	13	0	0
T94	15751	92	0	0
T95	12898	19	0	0
T96	1518	6	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1904	0	0
T87	7651	62	0	0
T88	3134	20	0	0
T89	2355	1	0	0
T90	7815	14	0	0
T91	3922	20	0	0
T92	8412	51	0	0
T93	3053	18	0	0
T94	15751	111	0	0
T95	12898	40	0	0
T96	1518	3	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445298415	1914	0	0
T87	7651	64	0	0
T88	3134	12	0	0
T89	2355	12	0	0
T90	7815	4	0	0
T91	3922	18	0	0
T92	8412	39	0	0
T93	3053	7	0	0
T94	15751	106	0	0
T95	12898	50	0	0
T96	1518	8	0	0