Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

163519

1

T2

727

T3

1280

T8

8

ack

14714

1

T2

13

T3

40

T8

4

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	655	1			T2	2		T3	5		T58	2
high	36427	1			T2	127		T3	257		T8	2
med	65964	1			T2	301		T3	521		T8	3
sml	74485	1			T2	308		T3	533		T8	7
all_zero	702	1			T2	2		T3	4		T79	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88693

1

T2

375

T3

658

T8

8

auto[1]

89540

1

T2

365

T3

662

T8

4

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122219

1

T2

485

T3

891

T8

10

auto[1]

56014

1

T2

255

T3

429

T8

2

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170393

1

T2

731

T3

1301

T8

9

auto[1]

7840

1

T2

9

T3

19

T8

3

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168227

1

T2

727

T3

1281

T8

7

auto[1]

10006

1

T2

13

T3

39

T8

5

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169089

1

T2

732

T3

1282

T8

9

auto[1]

9144

1

T2

8

T3

38

T8

3

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88693

1

T2

375

T3

658

T8

8

auto[1]

89540

1

T2

365

T3

662

T8

4

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122219

1

T2

485

T3

891

T8

10

auto[1]

56014

1

T2

255

T3

429

T8

2

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170393

1

T2

731

T3

1301

T8

9

auto[1]

7840

1

T2

9

T3

19

T8

3

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168227

1

T2

727

T3

1281

T8

7

auto[1]

10006

1

T2

13

T3

39

T8

5

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169089

1

T2

732

T3

1282

T8

9

auto[1]

9144

1

T2

8

T3

38

T8

3

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T82

1

T186

2

T256

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T119

1

T257

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T258

1

T259

1

T260

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

285

1

T3

3

T58

2

T87

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

132

1

T3

3

T169

2

T261

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

143

1

T2

1

T3

2

T87

2

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

527

1

T2

1

T3

4

T58

4

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

258

1

T3

2

T58

3

T87

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

270

1

T2

1

T3

3

T58

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

528

1

T2

1

T3

4

T58

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

279

1

T2

2

T3

2

T87

3

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

277

1

T3

2

T58

3

T87

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T262

1

T103

1

T263

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

1

1

T264

1

-

-

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T256

1

T265

1

T266

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51775	1			T2	228		T3	402		T8	1
write_address_byte	10006	1			T2	13		T3	39		T8	5
read_with_ack	2264	1			T2	4		T8	1		T76	6
read_with_nack	5576	1			T2	5		T3	19		T8	2
stop_byte	9144	1			T2	8		T3	38		T8	3
write_address_byte_nak	5006	1			T2	9		T3	36		T8	4
data_byte_nack	163519	1			T2	727		T3	1280		T8	8
stop_byte_nack	5386	1			T2	7		T3	35		T8	1
nakok_byte_nack	82125	1			T2	359		T3	641		T8	4
nakok_addr_byte_nack	2483	1			T3	17		T8	2		T57	3