SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.interrupts_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 45 | 0 | 45 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_acq_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_acq_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_cmd_complete_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_fmt_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_host_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_nak_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_overflow_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_scl_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_interference_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_sda_unstable_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_stretch_timeout_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_stretch_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_tx_threshold_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_unexp_stop_test | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 402250 | 1 | T1 | 3 | T2 | 3 | T3 | 1 | ||||
auto[1] | 401936 | 1 | T1 | 1 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 279 | 1 | T38 | 3 | T147 | 5 | T118 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403010 | 1 | T1 | 4 | T2 | 2 | T3 | 2 | ||||
auto[1] | 401087 | 1 | T2 | 2 | T3 | 2 | T6 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 306 | 1 | T38 | 4 | T39 | 4 | T147 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403127 | 1 | T1 | 3 | T2 | 2 | T3 | 2 | ||||
auto[1] | 401038 | 1 | T1 | 1 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 316 | 1 | T38 | 2 | T39 | 2 | T147 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 400795 | 1 | T1 | 2 | T2 | 4 | T3 | 1 | ||||
auto[1] | 399535 | 1 | T1 | 2 | T3 | 3 | T5 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 286 | 1 | T38 | 4 | T39 | 2 | T147 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403233 | 1 | T1 | 2 | T2 | 4 | T3 | 3 | ||||
auto[1] | 400805 | 1 | T1 | 2 | T3 | 1 | T6 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 306 | 1 | T38 | 2 | T39 | 3 | T147 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 402725 | 1 | T1 | 2 | T2 | 2 | T3 | 3 | ||||
auto[1] | 401371 | 1 | T1 | 2 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 302 | 1 | T38 | 3 | T39 | 2 | T147 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403548 | 1 | T1 | 3 | T2 | 4 | T3 | 3 | ||||
auto[1] | 400609 | 1 | T1 | 1 | T3 | 1 | T5 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 337 | 1 | T38 | 3 | T39 | 4 | T147 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403353 | 1 | T1 | 4 | T2 | 3 | T3 | 3 | ||||
auto[1] | 400775 | 1 | T2 | 1 | T3 | 1 | T6 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 294 | 1 | T38 | 1 | T39 | 2 | T147 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401001 | 1 | T1 | 2 | T2 | 3 | T3 | 1 | ||||
auto[1] | 399307 | 1 | T1 | 2 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 306 | 1 | T38 | 1 | T39 | 1 | T147 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401471 | 1 | T1 | 2 | T2 | 1 | T3 | 1 | ||||
auto[1] | 398914 | 1 | T1 | 2 | T2 | 3 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 324 | 1 | T38 | 4 | T39 | 3 | T147 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401357 | 1 | T1 | 2 | T2 | 3 | T3 | 2 | ||||
auto[1] | 398929 | 1 | T1 | 2 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 316 | 1 | T39 | 4 | T147 | 5 | T118 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401271 | 1 | T1 | 1 | T2 | 1 | T3 | 4 | ||||
auto[1] | 399060 | 1 | T1 | 3 | T2 | 3 | T5 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 317 | 1 | T38 | 3 | T147 | 6 | T118 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 403208 | 1 | T1 | 2 | T2 | 3 | T3 | 1 | ||||
auto[1] | 400930 | 1 | T1 | 2 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 291 | 1 | T38 | 2 | T39 | 4 | T147 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401502 | 1 | T1 | 1 | T2 | 3 | T3 | 2 | ||||
auto[1] | 398832 | 1 | T1 | 3 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 335 | 1 | T38 | 1 | T39 | 1 | T147 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 402611 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | ||||
auto[1] | 401471 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
dis | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 300 | 1 | T38 | 4 | T39 | 1 | T147 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |