Group : i2c_env_pkg::i2c_fifo_level_cg
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Group : i2c_env_pkg::i2c_fifo_level_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
82.35 61.76 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
i2c_env_pkg.rx_fifo_level_cg 41.18 1 100 1 64 64
i2c_env_pkg.fmt_fifo_level_cg 82.35 1 100 1 64 64




Group Instance : i2c_env_pkg.rx_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
41.18 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.rx_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 3 6 66.67
Crosses 8 7 1 12.50


Variables for Group Instance i2c_env_pkg.rx_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_fifolvl 5 3 2 40.00 100 1 1 0
cp_irq 2 0 2 100.00 100 1 1 2
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.rx_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_fifo_threshold_cross 8 7 1 12.50 100 1 1 0



Group Instance : i2c_env_pkg.fmt_fifo_level_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
82.35 1 100 1 64 64




Summary for Group Instance i2c_env_pkg.fmt_fifo_level_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 8 3 5 62.50


Variables for Group Instance i2c_env_pkg.fmt_fifo_level_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_fifolvl 5 0 5 100.00 100 1 1 0
cp_irq 2 0 2 100.00 100 1 1 2
cp_rst 2 0 2 100.00 100 1 1 2


Crosses for Group Instance i2c_env_pkg.fmt_fifo_level_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_fifo_threshold_cross 8 3 5 62.50 100 1 1 0


Summary for Variable cp_fifolvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 3 2 40.00


User Defined Bins for cp_fifolvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
lvl[1] 0 1 1
lvl[4] 0 1 1
lvl[16] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others 3667 1 T1 1 T2 1 T3 1
lvl[8] 2 1 T86 1 T233 1 - -



Summary for Variable cp_irq

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_irq

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3644 1 T1 1 T2 1 T3 1
auto[1] 25 1 T144 1 T232 1 T113 1



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1267 1 T31 5 T43 12 T33 5
auto[1] 2402 1 T1 1 T2 1 T3 1



Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 7 1 12.50 7
Automatically Generated Cross Bins 8 7 1 12.50 7
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_fifo_threshold_cross

Element holes
cp_fifolvlcp_irqCOUNTAT LEASTNUMBERSTATUS
[lvl[1] , lvl[4]] * -- -- 4
[lvl[16]] * -- -- 2


Uncovered bins
cp_fifolvlcp_irqCOUNTAT LEASTNUMBERSTATUS
[lvl[8]] [auto[1]] 0 1 1


Covered bins
cp_fifolvlcp_irqCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
lvl[8] auto[0] 2 1 T86 1 T233 1


User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
reserved_values 0 Excluded


Summary for Variable cp_fifolvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_fifolvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others 3343 1 T1 1 T2 1 T3 1
lvl[1] 206 1 T43 2 T45 2 T81 4
lvl[4] 54 1 T43 6 T45 4 T234 4
lvl[8] 60 1 T45 2 T81 2 T234 2
lvl[16] 6 1 T235 2 T236 2 T237 2



Summary for Variable cp_irq

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_irq

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3015 1 T1 1 T2 1 T3 1
auto[1] 654 1 T31 5 T33 5 T34 5



Summary for Variable cp_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_rst

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 921 1 T31 5 T43 6 T33 5
auto[1] 2748 1 T1 1 T2 1 T3 1



Summary for Cross cp_fifo_threshold_cross

Samples crossed: cp_fifolvl cp_irq
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 3 5 62.50 3
Automatically Generated Cross Bins 8 3 5 62.50 3
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_fifo_threshold_cross

Uncovered bins
cp_fifolvlcp_irqCOUNTAT LEASTNUMBERSTATUS
[lvl[4] , lvl[8] , lvl[16]] [auto[1]] -- -- 3


Covered bins
cp_fifolvlcp_irqCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lvl[1] auto[0] 182 1 T43 2 T45 2 T81 4
lvl[1] auto[1] 24 1 T173 1 T82 1 T238 2
lvl[4] auto[0] 54 1 T43 6 T45 4 T234 4
lvl[8] auto[0] 60 1 T45 2 T81 2 T234 2
lvl[16] auto[0] 6 1 T235 2 T236 2 T237 2


User Defined Cross Bins for cp_fifo_threshold_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
reserved_values 0 Excluded

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