Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Line Coverage for Module :
i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Module :
i2c_fifo_sync_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T54,T55,T56 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T64,T65 |
1 | 1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T34,T68,T70 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T34,T68,T70 |
1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T68,T70 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T31 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T31 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T31 |
Branch Coverage for Module :
i2c_fifo_sync_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T2,T3 |
1 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
i2c_fifo_sync_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5248 |
5248 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5248 |
5248 |
0 |
0 |
T1 |
4 |
4 |
0 |
0 |
T2 |
4 |
4 |
0 |
0 |
T3 |
4 |
4 |
0 |
0 |
T4 |
4 |
4 |
0 |
0 |
T5 |
4 |
4 |
0 |
0 |
T6 |
4 |
4 |
0 |
0 |
T7 |
4 |
4 |
0 |
0 |
T8 |
4 |
4 |
0 |
0 |
T9 |
4 |
4 |
0 |
0 |
T10 |
4 |
4 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1617263192 |
1616551772 |
0 |
0 |
T1 |
163584 |
163332 |
0 |
0 |
T2 |
849056 |
848668 |
0 |
0 |
T3 |
1834336 |
1834116 |
0 |
0 |
T4 |
3868 |
3604 |
0 |
0 |
T5 |
786692 |
786316 |
0 |
0 |
T6 |
1088920 |
1088648 |
0 |
0 |
T7 |
328588 |
328244 |
0 |
0 |
T8 |
91600 |
91272 |
0 |
0 |
T9 |
5372 |
5068 |
0 |
0 |
T10 |
6412 |
6116 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1617263192 |
1278428362 |
0 |
0 |
T1 |
163584 |
155295 |
0 |
0 |
T2 |
849056 |
687691 |
0 |
0 |
T3 |
1834336 |
1403620 |
0 |
0 |
T4 |
3868 |
3604 |
0 |
0 |
T5 |
786692 |
614260 |
0 |
0 |
T6 |
1088920 |
802058 |
0 |
0 |
T7 |
328588 |
261526 |
0 |
0 |
T8 |
91600 |
88594 |
0 |
0 |
T9 |
5372 |
5068 |
0 |
0 |
T10 |
6412 |
6116 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1617263192 |
20088798 |
0 |
0 |
T2 |
424528 |
44321 |
0 |
0 |
T3 |
917168 |
697 |
0 |
0 |
T4 |
1934 |
0 |
0 |
0 |
T5 |
393346 |
0 |
0 |
0 |
T6 |
544460 |
0 |
0 |
0 |
T7 |
164294 |
0 |
0 |
0 |
T8 |
45800 |
0 |
0 |
0 |
T9 |
2686 |
0 |
0 |
0 |
T10 |
3206 |
0 |
0 |
0 |
T22 |
197402 |
13 |
0 |
0 |
T23 |
0 |
20 |
0 |
0 |
T31 |
117904 |
1774 |
0 |
0 |
T38 |
0 |
14747 |
0 |
0 |
T39 |
0 |
28899 |
0 |
0 |
T54 |
0 |
2986 |
0 |
0 |
T55 |
0 |
3309 |
0 |
0 |
T57 |
40510 |
0 |
0 |
0 |
T58 |
0 |
457 |
0 |
0 |
T69 |
0 |
23131 |
0 |
0 |
T72 |
0 |
40012 |
0 |
0 |
T73 |
0 |
256055 |
0 |
0 |
T80 |
0 |
103 |
0 |
0 |
T87 |
0 |
697 |
0 |
0 |
T142 |
0 |
148 |
0 |
0 |
T144 |
0 |
8 |
0 |
0 |
T148 |
0 |
12856 |
0 |
0 |
T149 |
0 |
32838 |
0 |
0 |
T154 |
0 |
9292 |
0 |
0 |
T155 |
0 |
59931 |
0 |
0 |
T156 |
95600 |
0 |
0 |
0 |
T157 |
15390 |
0 |
0 |
0 |
T158 |
80712 |
0 |
0 |
0 |
T159 |
341826 |
0 |
0 |
0 |
T160 |
1669 |
0 |
0 |
0 |
T161 |
180395 |
0 |
0 |
0 |
T162 |
96794 |
0 |
0 |
0 |
T163 |
165518 |
0 |
0 |
0 |
T164 |
22278 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1617263192 |
716132 |
0 |
0 |
T1 |
40896 |
0 |
0 |
0 |
T2 |
636792 |
793 |
0 |
0 |
T3 |
1375752 |
2500 |
0 |
0 |
T4 |
2901 |
0 |
0 |
0 |
T5 |
786692 |
96 |
0 |
0 |
T6 |
1088920 |
126 |
0 |
0 |
T7 |
328588 |
331 |
0 |
0 |
T8 |
91600 |
8 |
0 |
0 |
T9 |
5372 |
0 |
0 |
0 |
T10 |
6412 |
0 |
0 |
0 |
T11 |
150595 |
550 |
0 |
0 |
T12 |
0 |
89 |
0 |
0 |
T19 |
0 |
689 |
0 |
0 |
T31 |
117904 |
232 |
0 |
0 |
T32 |
0 |
162 |
0 |
0 |
T33 |
0 |
281 |
0 |
0 |
T34 |
0 |
427 |
0 |
0 |
T54 |
0 |
1116 |
0 |
0 |
T57 |
60765 |
24 |
0 |
0 |
T58 |
0 |
1500 |
0 |
0 |
T76 |
0 |
10 |
0 |
0 |
T79 |
22418 |
86 |
0 |
0 |
T80 |
0 |
1250 |
0 |
0 |
T87 |
0 |
2375 |
0 |
0 |
T165 |
0 |
135 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1617263192 |
716132 |
0 |
0 |
T1 |
40896 |
0 |
0 |
0 |
T2 |
636792 |
793 |
0 |
0 |
T3 |
1375752 |
2500 |
0 |
0 |
T4 |
2901 |
0 |
0 |
0 |
T5 |
786692 |
96 |
0 |
0 |
T6 |
1088920 |
126 |
0 |
0 |
T7 |
328588 |
331 |
0 |
0 |
T8 |
91600 |
8 |
0 |
0 |
T9 |
5372 |
0 |
0 |
0 |
T10 |
6412 |
0 |
0 |
0 |
T11 |
150595 |
550 |
0 |
0 |
T12 |
0 |
89 |
0 |
0 |
T19 |
0 |
689 |
0 |
0 |
T31 |
117904 |
232 |
0 |
0 |
T32 |
0 |
162 |
0 |
0 |
T33 |
0 |
281 |
0 |
0 |
T34 |
0 |
427 |
0 |
0 |
T54 |
0 |
1116 |
0 |
0 |
T57 |
60765 |
24 |
0 |
0 |
T58 |
0 |
1500 |
0 |
0 |
T76 |
0 |
10 |
0 |
0 |
T79 |
22418 |
86 |
0 |
0 |
T80 |
0 |
1250 |
0 |
0 |
T87 |
0 |
2375 |
0 |
0 |
T165 |
0 |
135 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 39 | 76.47 |
Logical | 51 | 39 | 76.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T5,T6 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T64,T65,T66 |
1 | 1 | Covered | T1,T5,T6 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T5,T6 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T5,T6 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T5,T6 |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Not Covered | |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T5,T6 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Covered | T1,T6,T7 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T6,T7 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T5,T6 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T6,T7 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T6,T7 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T5,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T6 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T6 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T31,T33,T34 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T33,T34 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T31,T33,T34 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T1,T5,T6 |
1 |
0 |
- |
Covered |
T1,T5,T6 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
404137943 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
326330865 |
0 |
0 |
T1 |
40896 |
32796 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
193949 |
0 |
0 |
T6 |
272230 |
189274 |
0 |
0 |
T7 |
82147 |
62056 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
6208548 |
0 |
0 |
T11 |
150595 |
0 |
0 |
0 |
T12 |
48554 |
0 |
0 |
0 |
T31 |
117904 |
1774 |
0 |
0 |
T33 |
0 |
8011 |
0 |
0 |
T34 |
0 |
29961 |
0 |
0 |
T43 |
10377 |
0 |
0 |
0 |
T54 |
194332 |
0 |
0 |
0 |
T58 |
266111 |
0 |
0 |
0 |
T64 |
0 |
57049 |
0 |
0 |
T67 |
0 |
16275 |
0 |
0 |
T68 |
0 |
39902 |
0 |
0 |
T70 |
0 |
67641 |
0 |
0 |
T71 |
0 |
18543 |
0 |
0 |
T76 |
25295 |
0 |
0 |
0 |
T79 |
22418 |
0 |
0 |
0 |
T80 |
209336 |
0 |
0 |
0 |
T87 |
435957 |
0 |
0 |
0 |
T166 |
0 |
56522 |
0 |
0 |
T167 |
0 |
32135 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
203411 |
0 |
0 |
T1 |
40896 |
44 |
0 |
0 |
T2 |
212264 |
0 |
0 |
0 |
T3 |
458584 |
0 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
3 |
0 |
0 |
T6 |
272230 |
49 |
0 |
0 |
T7 |
82147 |
135 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T12 |
0 |
43 |
0 |
0 |
T29 |
0 |
46 |
0 |
0 |
T31 |
0 |
232 |
0 |
0 |
T32 |
0 |
58 |
0 |
0 |
T33 |
0 |
759 |
0 |
0 |
T34 |
0 |
541 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
203411 |
0 |
0 |
T1 |
40896 |
44 |
0 |
0 |
T2 |
212264 |
0 |
0 |
0 |
T3 |
458584 |
0 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
3 |
0 |
0 |
T6 |
272230 |
49 |
0 |
0 |
T7 |
82147 |
135 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T12 |
0 |
43 |
0 |
0 |
T29 |
0 |
46 |
0 |
0 |
T31 |
0 |
232 |
0 |
0 |
T32 |
0 |
58 |
0 |
0 |
T33 |
0 |
759 |
0 |
0 |
T34 |
0 |
541 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T8 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T59,T60 |
1 | 1 | Covered | T2,T3,T8 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T8 |
0 | 1 | Covered | T2,T3,T8 |
1 | 0 | Covered | T59,T60,T168 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T59,T60,T168 |
1 | Covered | T2,T3,T8 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T59,T60,T168 |
0 | 1 | Covered | T2,T3,T8 |
1 | 0 | Covered | T2,T3,T8 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T8 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T8 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T8 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T148,T149 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T148,T149 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T8 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T148,T149 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T2,T3,T8 |
1 |
0 |
- |
Covered |
T2,T3,T8 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
404137943 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
352990250 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
63482 |
0 |
0 |
T3 |
458584 |
243992 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
20140 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
13221114 |
0 |
0 |
T2 |
212264 |
44312 |
0 |
0 |
T3 |
458584 |
0 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T38 |
0 |
14747 |
0 |
0 |
T39 |
0 |
28899 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T69 |
0 |
23131 |
0 |
0 |
T72 |
0 |
40012 |
0 |
0 |
T73 |
0 |
256055 |
0 |
0 |
T148 |
0 |
12845 |
0 |
0 |
T149 |
0 |
32838 |
0 |
0 |
T154 |
0 |
9292 |
0 |
0 |
T155 |
0 |
59931 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
165880 |
0 |
0 |
T2 |
212264 |
731 |
0 |
0 |
T3 |
458584 |
1260 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
8 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T57 |
20255 |
24 |
0 |
0 |
T58 |
0 |
756 |
0 |
0 |
T76 |
0 |
10 |
0 |
0 |
T79 |
0 |
86 |
0 |
0 |
T80 |
0 |
630 |
0 |
0 |
T87 |
0 |
1197 |
0 |
0 |
T165 |
0 |
135 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
165880 |
0 |
0 |
T2 |
212264 |
731 |
0 |
0 |
T3 |
458584 |
1260 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
8 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T57 |
20255 |
24 |
0 |
0 |
T58 |
0 |
756 |
0 |
0 |
T76 |
0 |
10 |
0 |
0 |
T79 |
0 |
86 |
0 |
0 |
T80 |
0 |
630 |
0 |
0 |
T87 |
0 |
1197 |
0 |
0 |
T165 |
0 |
135 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 42 | 82.35 |
Logical | 51 | 42 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T23 |
1 | 1 | Covered | T1,T5,T6 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T7 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T34,T68,T70 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T34,T68,T70 |
1 | Covered | T5,T6,T7 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T34,T68,T70 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T7 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T7 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T23 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T22,T23 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T5,T6,T7 |
1 |
0 |
- |
Covered |
T5,T6,T7 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
404137943 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
224787449 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
27153 |
0 |
0 |
T6 |
272230 |
68460 |
0 |
0 |
T7 |
82147 |
35348 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
33 |
0 |
0 |
T22 |
197402 |
13 |
0 |
0 |
T23 |
0 |
20 |
0 |
0 |
T156 |
95600 |
0 |
0 |
0 |
T157 |
15390 |
0 |
0 |
0 |
T158 |
80712 |
0 |
0 |
0 |
T159 |
341826 |
0 |
0 |
0 |
T160 |
1669 |
0 |
0 |
0 |
T161 |
180395 |
0 |
0 |
0 |
T162 |
96794 |
0 |
0 |
0 |
T163 |
165518 |
0 |
0 |
0 |
T164 |
22278 |
0 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
173471 |
0 |
0 |
T5 |
196673 |
96 |
0 |
0 |
T6 |
272230 |
126 |
0 |
0 |
T7 |
82147 |
331 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T11 |
150595 |
550 |
0 |
0 |
T12 |
0 |
89 |
0 |
0 |
T19 |
0 |
689 |
0 |
0 |
T31 |
117904 |
232 |
0 |
0 |
T32 |
0 |
162 |
0 |
0 |
T33 |
0 |
281 |
0 |
0 |
T34 |
0 |
427 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T79 |
22418 |
0 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
173471 |
0 |
0 |
T5 |
196673 |
96 |
0 |
0 |
T6 |
272230 |
126 |
0 |
0 |
T7 |
82147 |
331 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T11 |
150595 |
550 |
0 |
0 |
T12 |
0 |
89 |
0 |
0 |
T19 |
0 |
689 |
0 |
0 |
T31 |
117904 |
232 |
0 |
0 |
T32 |
0 |
162 |
0 |
0 |
T33 |
0 |
281 |
0 |
0 |
T34 |
0 |
427 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T79 |
22418 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 164 | 3 | 3 | 100.00 |
ALWAYS | 174 | 28 | 28 | 100.00 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
CONT_ASSIGN | 249 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
120 |
1 |
1 |
121 |
1 |
1 |
125 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
162 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
177 |
1 |
1 |
178 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
187 |
1 |
1 |
|
|
|
MISSING_ELSE |
191 |
1 |
1 |
196 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
212 |
1 |
1 |
213 |
1 |
1 |
214 |
1 |
1 |
215 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
228 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
249 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Total | Covered | Percent |
Conditions | 51 | 43 | 84.31 |
Logical | 51 | 43 | 84.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (fifo_wvalid_i && fifo_wready_o)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T54,T55,T56 |
1 | 1 | Covered | T2,T3,T8 |
LINE 125
EXPRESSION (sram_req_o && sram_gnt_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T61,T62,T63 |
1 | 1 | Covered | T2,T3,T58 |
LINE 150
EXPRESSION (sram_access && sram_write_o)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 151
EXPRESSION (sram_access && ((!sram_write_o)))
-----1----- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 162
EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
-------------------------------1------------------------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T58 |
0 | 1 | Covered | T2,T3,T58 |
1 | 0 | Covered | T61,T62,T63 |
LINE 196
SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T61,T62,T63 |
1 | Covered | T2,T3,T58 |
LINE 196
SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
-------------------1------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T61,T62,T63 |
0 | 1 | Covered | T2,T3,T58 |
1 | 0 | Covered | T2,T3,T58 |
LINE 196
SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
---------1--------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 196
SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 204
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 207
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T2,T3,T58 |
LINE 212
EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T1,T2,T3 |
LINE 220
EXPRESSION (((!sram_full)) && inp_buf_rvalid)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T58 |
LINE 223
EXPRESSION (((!sram_full)) && sram_gnt_i)
-------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T58 |
LINE 236
EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
-------1------ ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T58 |
1 | 1 | Covered | T1,T2,T3 |
LINE 236
SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T58 |
LINE 236
SUB-EXPRESSION (sram_full && oup_buf_full)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T58 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T58 |
Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
IF |
164 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
191 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (clr_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 164 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (sram_read_in_prev_cyc_q)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T58 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!sram_empty))
-2-: 196 if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-: 212 if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T2,T3,T58 |
1 |
0 |
- |
Covered |
T2,T3,T58 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter
Assertion Details
MinimalSramAw_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
MinimalSramFifoDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1312 |
1312 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
404137943 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
212167 |
0 |
0 |
T3 |
458584 |
458529 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramReadWhenEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
374319798 |
0 |
0 |
T1 |
40896 |
40833 |
0 |
0 |
T2 |
212264 |
199875 |
0 |
0 |
T3 |
458584 |
242570 |
0 |
0 |
T4 |
967 |
901 |
0 |
0 |
T5 |
196673 |
196579 |
0 |
0 |
T6 |
272230 |
272162 |
0 |
0 |
T7 |
82147 |
82061 |
0 |
0 |
T8 |
22900 |
22818 |
0 |
0 |
T9 |
1343 |
1267 |
0 |
0 |
T10 |
1603 |
1529 |
0 |
0 |
NoSramWriteWhenFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
659103 |
0 |
0 |
T2 |
212264 |
9 |
0 |
0 |
T3 |
458584 |
697 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T54 |
0 |
2986 |
0 |
0 |
T55 |
0 |
3309 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T58 |
0 |
457 |
0 |
0 |
T80 |
0 |
103 |
0 |
0 |
T87 |
0 |
697 |
0 |
0 |
T142 |
0 |
148 |
0 |
0 |
T144 |
0 |
8 |
0 |
0 |
T148 |
0 |
11 |
0 |
0 |
OupBufWreadyAfterSramRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
173370 |
0 |
0 |
T2 |
212264 |
62 |
0 |
0 |
T3 |
458584 |
1240 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T54 |
0 |
1116 |
0 |
0 |
T55 |
0 |
1240 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T58 |
0 |
744 |
0 |
0 |
T80 |
0 |
620 |
0 |
0 |
T87 |
0 |
1178 |
0 |
0 |
T142 |
0 |
868 |
0 |
0 |
T148 |
0 |
67 |
0 |
0 |
T169 |
0 |
1054 |
0 |
0 |
SramRvalidAfterRead_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
404315798 |
173370 |
0 |
0 |
T2 |
212264 |
62 |
0 |
0 |
T3 |
458584 |
1240 |
0 |
0 |
T4 |
967 |
0 |
0 |
0 |
T5 |
196673 |
0 |
0 |
0 |
T6 |
272230 |
0 |
0 |
0 |
T7 |
82147 |
0 |
0 |
0 |
T8 |
22900 |
0 |
0 |
0 |
T9 |
1343 |
0 |
0 |
0 |
T10 |
1603 |
0 |
0 |
0 |
T54 |
0 |
1116 |
0 |
0 |
T55 |
0 |
1240 |
0 |
0 |
T57 |
20255 |
0 |
0 |
0 |
T58 |
0 |
744 |
0 |
0 |
T80 |
0 |
620 |
0 |
0 |
T87 |
0 |
1178 |
0 |
0 |
T142 |
0 |
868 |
0 |
0 |
T148 |
0 |
67 |
0 |
0 |
T169 |
0 |
1054 |
0 |
0 |