Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	764655	1			T1	3		T2	2		T3	2
all_values[1]	764655	1			T1	3		T2	2		T3	2
all_values[2]	764655	1			T1	3		T2	2		T3	2
all_values[3]	764655	1			T1	3		T2	2		T3	2
all_values[4]	764655	1			T1	3		T2	2		T3	2
all_values[5]	764655	1			T1	3		T2	2		T3	2
all_values[6]	764655	1			T1	3		T2	2		T3	2
all_values[7]	764655	1			T1	3		T2	2		T3	2
all_values[8]	764655	1			T1	3		T2	2		T3	2
all_values[9]	764655	1			T1	3		T2	2		T3	2
all_values[10]	764655	1			T1	3		T2	2		T3	2
all_values[11]	764655	1			T1	3		T2	2		T3	2
all_values[12]	764655	1			T1	3		T2	2		T3	2
all_values[13]	764655	1			T1	3		T2	2		T3	2
all_values[14]	764655	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8051626

1

T1

38

T2

26

T3

26

auto[1]

3418199

1

T1

7

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10206986

1

T1

45

T2

30

T3

30

auto[1]

1262839

1

T10

82398

T98

34816

T101

131871

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	67512	1			T7	2		T10	1		T17	1
all_values[0]	auto[0]	auto[1]	7738	1			T10	23		T98	1209		T101	671
all_values[0]	auto[1]	auto[0]	610759	1			T1	3		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	78646	1			T10	5471		T98	1114		T101	8119
all_values[1]	auto[0]	auto[0]	674208	1			T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	89877	1			T10	5492		T98	2310		T101	8788
all_values[1]	auto[1]	auto[0]	362	1			T148	11		T131	6		T65	3
all_values[1]	auto[1]	auto[1]	208	1			T10	2		T98	3		T101	2
all_values[2]	auto[0]	auto[0]	697624	1			T1	3		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	66828	1			T10	5492		T98	2321		T101	8788
all_values[2]	auto[1]	auto[1]	203	1			T10	1		T98	3		T101	3
all_values[3]	auto[0]	auto[0]	692409	1			T1	3		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	72046	1			T10	5491		T98	2309		T101	8790
all_values[3]	auto[1]	auto[1]	200	1			T10	3		T98	4		T101	1
all_values[4]	auto[0]	auto[0]	690845	1			T1	3		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	73612	1			T10	5491		T98	2319		T101	8787
all_values[4]	auto[1]	auto[0]	19	1			T219	1		T220	1		T221	1
all_values[4]	auto[1]	auto[1]	179	1			T10	1		T98	3		T101	5
all_values[5]	auto[0]	auto[0]	681329	1			T1	3		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	83099	1			T10	5490		T98	2318		T101	8787
all_values[5]	auto[1]	auto[1]	227	1			T10	2		T98	4		T101	5
all_values[6]	auto[0]	auto[0]	122929	1			T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	10985	1			T10	2851		T98	2318		T101	70
all_values[6]	auto[1]	auto[0]	554726	1			T17	1		T54	1		T68	1
all_values[6]	auto[1]	auto[1]	76015	1			T10	2641		T98	5		T101	8722
all_values[7]	auto[0]	auto[0]	649701	1			T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	86102	1			T10	5225		T98	2035		T101	8234
all_values[7]	auto[1]	auto[0]	25085	1			T17	1		T54	1		T68	1
all_values[7]	auto[1]	auto[1]	3767	1			T10	268		T98	289		T101	558
all_values[8]	auto[0]	auto[0]	92354	1			T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	8756	1			T10	2816		T98	2165		T101	73
all_values[8]	auto[1]	auto[0]	583423	1			T7	4		T17	1		T54	1
all_values[8]	auto[1]	auto[1]	80122	1			T10	2676		T98	158		T101	8718
all_values[9]	auto[0]	auto[0]	109939	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	12642	1			T10	2859		T98	2317		T101	213
all_values[9]	auto[1]	auto[0]	564664	1			T1	1		T5	1		T6	1
all_values[9]	auto[1]	auto[1]	77410	1			T10	2634		T98	7		T101	8579
all_values[10]	auto[0]	auto[0]	674596	1			T1	3		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	89886	1			T10	5491		T98	2311		T101	8789
all_values[10]	auto[1]	auto[1]	173	1			T10	3		T98	2		T101	3
all_values[11]	auto[0]	auto[0]	2771	1			T7	2		T10	2		T17	1
all_values[11]	auto[0]	auto[1]	496	1			T10	16		T98	6		T101	25
all_values[11]	auto[1]	auto[0]	671800	1			T1	3		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	89588	1			T10	5477		T98	2317		T101	8767
all_values[12]	auto[0]	auto[0]	674538	1			T1	3		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	89922	1			T10	5492		T98	2320		T101	8788
all_values[12]	auto[1]	auto[1]	195	1			T10	2		T98	2		T101	3
all_values[13]	auto[0]	auto[0]	674541	1			T1	3		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	89898	1			T10	5493		T98	2323		T101	8787
all_values[13]	auto[1]	auto[1]	216	1			T10	1		T98	1		T101	4
all_values[14]	auto[0]	auto[0]	690852	1			T1	3		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	73591	1			T10	5491		T98	2319		T101	8787
all_values[14]	auto[1]	auto[1]	212	1			T10	3		T98	4		T101	5