Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	764655	1			T1	3		T2	2		T3	2
all_pins[1]	764655	1			T1	3		T2	2		T3	2
all_pins[2]	764655	1			T1	3		T2	2		T3	2
all_pins[3]	764655	1			T1	3		T2	2		T3	2
all_pins[4]	764655	1			T1	3		T2	2		T3	2
all_pins[5]	764655	1			T1	3		T2	2		T3	2
all_pins[6]	764655	1			T1	3		T2	2		T3	2
all_pins[7]	764655	1			T1	3		T2	2		T3	2
all_pins[8]	764655	1			T1	3		T2	2		T3	2
all_pins[9]	764655	1			T1	3		T2	2		T3	2
all_pins[10]	764655	1			T1	3		T2	2		T3	2
all_pins[11]	764655	1			T1	3		T2	2		T3	2
all_pins[12]	764655	1			T1	3		T2	2		T3	2
all_pins[13]	764655	1			T1	3		T2	2		T3	2
all_pins[14]	764655	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8056527	1			T1	38		T2	26		T3	26
values[0x1]	3413298	1			T1	7		T2	4		T3	4
transitions[0x0=>0x1]	2730940	1			T1	7		T2	4		T3	4
transitions[0x1=>0x0]	2729907	1			T1	6		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78574	1			T7	2		T10	26		T17	1
all_pins[0]	values[0x1]	686081	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	685610	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	84	1			T98	1		T101	2		T244	2
all_pins[1]	values[0x0]	764100	1			T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	555	1			T148	15		T98	1		T131	8
all_pins[1]	transitions[0x0=>0x1]	521	1			T148	15		T98	1		T131	8
all_pins[1]	transitions[0x1=>0x0]	75	1			T98	3		T101	1		T169	3
all_pins[2]	values[0x0]	764546	1			T1	3		T2	2		T3	2
all_pins[2]	values[0x1]	109	1			T98	3		T101	1		T169	4
all_pins[2]	transitions[0x0=>0x1]	90	1			T98	3		T101	1		T169	4
all_pins[2]	transitions[0x1=>0x0]	69	1			T98	2		T101	1		T169	3
all_pins[3]	values[0x0]	764567	1			T1	3		T2	2		T3	2
all_pins[3]	values[0x1]	88	1			T98	2		T101	1		T169	3
all_pins[3]	transitions[0x0=>0x1]	70	1			T98	2		T101	1		T169	2
all_pins[3]	transitions[0x1=>0x0]	89	1			T101	4		T219	1		T169	2
all_pins[4]	values[0x0]	764548	1			T1	3		T2	2		T3	2
all_pins[4]	values[0x1]	107	1			T101	4		T219	1		T169	3
all_pins[4]	transitions[0x0=>0x1]	88	1			T101	4		T219	1		T169	2
all_pins[4]	transitions[0x1=>0x0]	81	1			T101	3		T169	2		T57	2
all_pins[5]	values[0x0]	764555	1			T1	3		T2	2		T3	2
all_pins[5]	values[0x1]	100	1			T101	3		T169	3		T57	2
all_pins[5]	transitions[0x0=>0x1]	79	1			T101	3		T169	2		T57	2
all_pins[5]	transitions[0x1=>0x0]	630423	1			T10	2639		T17	1		T54	1
all_pins[6]	values[0x0]	134211	1			T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	630444	1			T10	2639		T17	1		T54	1
all_pins[6]	transitions[0x0=>0x1]	610850	1			T10	2499		T79	11196		T78	9
all_pins[6]	transitions[0x1=>0x0]	12688	1			T10	137		T78	76		T50	1
all_pins[7]	values[0x0]	732373	1			T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	32282	1			T10	277		T17	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	10162	1			T10	125		T78	72		T71	1
all_pins[7]	transitions[0x1=>0x0]	641187	1			T7	4		T10	2524		T79	11168
all_pins[8]	values[0x0]	101348	1			T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	663307	1			T7	4		T10	2676		T17	1
all_pins[8]	transitions[0x0=>0x1]	23418	1			T7	4		T10	60		T79	160
all_pins[8]	transitions[0x1=>0x0]	2093	1			T1	1		T5	1		T6	1
all_pins[9]	values[0x0]	122673	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	641982	1			T1	1		T5	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	641965	1			T1	1		T5	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	70	1			T101	2		T169	2		T57	1
all_pins[10]	values[0x0]	764568	1			T1	3		T2	2		T3	2
all_pins[10]	values[0x1]	87	1			T10	1		T101	3		T169	2
all_pins[10]	transitions[0x0=>0x1]	62	1			T10	1		T101	3		T169	2
all_pins[10]	transitions[0x1=>0x0]	757804	1			T1	3		T2	2		T3	2
all_pins[11]	values[0x0]	6826	1			T7	2		T10	20		T17	1
all_pins[11]	values[0x1]	757829	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	757798	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	68	1			T10	2		T101	2		T169	1
all_pins[12]	values[0x0]	764556	1			T1	3		T2	2		T3	2
all_pins[12]	values[0x1]	99	1			T10	2		T98	1		T101	2
all_pins[12]	transitions[0x0=>0x1]	65	1			T10	1		T98	1		T101	2
all_pins[12]	transitions[0x1=>0x0]	94	1			T169	3		T245	1		T246	4
all_pins[13]	values[0x0]	764527	1			T1	3		T2	2		T3	2
all_pins[13]	values[0x1]	128	1			T10	1		T169	6		T245	1
all_pins[13]	transitions[0x0=>0x1]	97	1			T10	1		T169	3		T247	1
all_pins[13]	transitions[0x1=>0x0]	69	1			T98	3		T101	3		T57	1
all_pins[14]	values[0x0]	764555	1			T1	3		T2	2		T3	2
all_pins[14]	values[0x1]	100	1			T98	3		T101	3		T169	3
all_pins[14]	transitions[0x0=>0x1]	65	1			T98	1		T101	1		T169	2
all_pins[14]	transitions[0x1=>0x0]	685013	1			T1	2		T2	1		T3	1