Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	458	1			T10	4		T98	8		T101	7
all_values[1]	458	1			T10	4		T98	8		T101	7
all_values[2]	458	1			T10	4		T98	8		T101	7
all_values[3]	458	1			T10	4		T98	8		T101	7
all_values[4]	458	1			T10	4		T98	8		T101	7
all_values[5]	458	1			T10	4		T98	8		T101	7
all_values[6]	458	1			T10	4		T98	8		T101	7
all_values[7]	458	1			T10	4		T98	8		T101	7
all_values[8]	458	1			T10	4		T98	8		T101	7
all_values[9]	458	1			T10	4		T98	8		T101	7
all_values[10]	458	1			T10	4		T98	8		T101	7
all_values[11]	458	1			T10	4		T98	8		T101	7
all_values[12]	458	1			T10	4		T98	8		T101	7
all_values[13]	458	1			T10	4		T98	8		T101	7
all_values[14]	458	1			T10	4		T98	8		T101	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3575

1

T10

30

T98

59

T101

59

auto[1]

3295

1

T10

30

T98

61

T101

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T10

12

T98

23

T101

9

auto[1]

5750

1

T10

48

T98

97

T101

96

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4025

1

T10

35

T98

81

T101

56

auto[1]

2845

1

T10

25

T98

39

T101

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	53	1			T101	1		T119	4		T248	3
all_values[0]	auto[0]	auto[0]	auto[1]	102	1			T10	2		T98	3		T101	1
all_values[0]	auto[0]	auto[1]	auto[0]	45	1			T98	1		T101	1		T247	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T98	2		T101	1		T169	3
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T10	2		T98	2		T101	1
all_values[0]	auto[1]	auto[1]	auto[1]	74	1			T101	2		T169	8		T57	1
all_values[1]	auto[0]	auto[0]	auto[0]	47	1			T98	4		T101	1		T247	2
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T98	1		T169	4		T57	1
all_values[1]	auto[0]	auto[1]	auto[0]	25	1			T101	1		T247	2		T249	1
all_values[1]	auto[0]	auto[1]	auto[1]	106	1			T10	2		T101	3		T169	6
all_values[1]	auto[1]	auto[0]	auto[1]	94	1			T10	2		T98	2		T169	3
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T98	1		T101	2		T169	2
all_values[2]	auto[0]	auto[0]	auto[0]	35	1			T101	1		T245	1		T120	1
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T101	2		T169	2		T57	4
all_values[2]	auto[0]	auto[1]	auto[0]	32	1			T10	1		T245	1		T247	1
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T10	2		T98	5		T101	1
all_values[2]	auto[1]	auto[0]	auto[1]	101	1			T101	3		T169	3		T57	3
all_values[2]	auto[1]	auto[1]	auto[1]	102	1			T10	1		T98	3		T169	5
all_values[3]	auto[0]	auto[0]	auto[0]	44	1			T98	2		T101	1		T169	1
all_values[3]	auto[0]	auto[0]	auto[1]	101	1			T10	1		T98	1		T101	2
all_values[3]	auto[0]	auto[1]	auto[0]	28	1			T98	2		T169	1		T245	2
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T98	1		T101	2		T169	7
all_values[3]	auto[1]	auto[0]	auto[1]	105	1			T10	3		T98	1		T169	1
all_values[3]	auto[1]	auto[1]	auto[1]	78	1			T98	1		T101	2		T169	3
all_values[4]	auto[0]	auto[0]	auto[0]	48	1			T10	2		T249	3		T235	2
all_values[4]	auto[0]	auto[0]	auto[1]	97	1			T10	1		T98	3		T169	4
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T98	2		T169	1		T119	1
all_values[4]	auto[0]	auto[1]	auto[1]	101	1			T101	2		T169	5		T57	5
all_values[4]	auto[1]	auto[0]	auto[1]	102	1			T10	1		T98	2		T101	2
all_values[4]	auto[1]	auto[1]	auto[1]	77	1			T98	1		T101	3		T169	2
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T98	1		T57	2		T245	1
all_values[5]	auto[0]	auto[0]	auto[1]	103	1			T10	1		T98	3		T101	2
all_values[5]	auto[0]	auto[1]	auto[0]	37	1			T10	2		T98	1		T248	1
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T98	1		T101	1		T169	6
all_values[5]	auto[1]	auto[0]	auto[1]	103	1			T10	1		T98	1		T101	2
all_values[5]	auto[1]	auto[1]	auto[1]	86	1			T98	1		T101	2		T169	2
all_values[6]	auto[0]	auto[0]	auto[0]	39	1			T57	2		T120	1		T250	1
all_values[6]	auto[0]	auto[0]	auto[1]	100	1			T10	1		T98	4		T101	3
all_values[6]	auto[0]	auto[1]	auto[0]	30	1			T10	2		T98	1		T245	1
all_values[6]	auto[0]	auto[1]	auto[1]	99	1			T98	1		T101	2		T169	4
all_values[6]	auto[1]	auto[0]	auto[1]	99	1			T10	1		T98	2		T101	2
all_values[6]	auto[1]	auto[1]	auto[1]	91	1			T169	3		T57	2		T247	1
all_values[7]	auto[0]	auto[0]	auto[0]	36	1			T169	3		T57	1		T119	1
all_values[7]	auto[0]	auto[0]	auto[1]	92	1			T57	3		T245	1		T246	2
all_values[7]	auto[0]	auto[1]	auto[0]	33	1			T10	1		T169	1		T119	3
all_values[7]	auto[0]	auto[1]	auto[1]	107	1			T10	2		T98	4		T101	2
all_values[7]	auto[1]	auto[0]	auto[1]	105	1			T101	3		T169	3		T57	1
all_values[7]	auto[1]	auto[1]	auto[1]	85	1			T10	1		T98	4		T101	2
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T10	2		T101	1		T57	1
all_values[8]	auto[0]	auto[0]	auto[1]	103	1			T10	1		T98	1		T101	2
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T98	1		T169	1		T245	2
all_values[8]	auto[0]	auto[1]	auto[1]	87	1			T98	2		T169	4		T57	2
all_values[8]	auto[1]	auto[0]	auto[1]	101	1			T10	1		T98	2		T101	3
all_values[8]	auto[1]	auto[1]	auto[1]	100	1			T98	2		T101	1		T169	4
all_values[9]	auto[0]	auto[0]	auto[0]	30	1			T246	2		T251	1		T252	1
all_values[9]	auto[0]	auto[0]	auto[1]	104	1			T98	2		T101	1		T169	4
all_values[9]	auto[0]	auto[1]	auto[0]	38	1			T10	1		T169	1		T248	4
all_values[9]	auto[0]	auto[1]	auto[1]	93	1			T10	1		T98	4		T101	2
all_values[9]	auto[1]	auto[0]	auto[1]	97	1			T101	1		T169	3		T57	1
all_values[9]	auto[1]	auto[1]	auto[1]	96	1			T10	2		T98	2		T101	3
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T98	2		T57	2		T247	1
all_values[10]	auto[0]	auto[0]	auto[1]	93	1			T98	2		T101	1		T169	4
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T98	2		T247	1		T249	1
all_values[10]	auto[0]	auto[1]	auto[1]	110	1			T10	1		T101	3		T169	6
all_values[10]	auto[1]	auto[0]	auto[1]	88	1			T10	2		T98	2		T101	1
all_values[10]	auto[1]	auto[1]	auto[1]	85	1			T10	1		T101	2		T169	3
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T169	2		T57	2		T252	2
all_values[11]	auto[0]	auto[0]	auto[1]	80	1			T10	1		T98	3		T101	4
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T10	1		T98	1		T169	6
all_values[11]	auto[0]	auto[1]	auto[1]	90	1			T98	2		T101	1		T169	2
all_values[11]	auto[1]	auto[0]	auto[1]	103	1			T10	1		T101	2		T169	1
all_values[11]	auto[1]	auto[1]	auto[1]	100	1			T10	1		T98	2		T169	2
all_values[12]	auto[0]	auto[0]	auto[0]	38	1			T98	2		T101	1		T57	1
all_values[12]	auto[0]	auto[0]	auto[1]	116	1			T98	2		T101	3		T169	6
all_values[12]	auto[0]	auto[1]	auto[0]	32	1			T120	1		T121	1		T122	2
all_values[12]	auto[0]	auto[1]	auto[1]	77	1			T10	2		T98	2		T169	1
all_values[12]	auto[1]	auto[0]	auto[1]	100	1			T98	2		T101	1		T169	4
all_values[12]	auto[1]	auto[1]	auto[1]	95	1			T10	2		T101	2		T169	4
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T101	1		T245	1		T119	1
all_values[13]	auto[0]	auto[0]	auto[1]	87	1			T98	1		T101	3		T169	5
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T249	1		T250	1		T121	1
all_values[13]	auto[0]	auto[1]	auto[1]	109	1			T10	3		T98	4		T169	1
all_values[13]	auto[1]	auto[0]	auto[1]	93	1			T98	1		T101	2		T169	5
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T10	1		T98	2		T101	1
all_values[14]	auto[0]	auto[0]	auto[0]	46	1			T98	1		T57	1		T246	1
all_values[14]	auto[0]	auto[0]	auto[1]	106	1			T10	2		T98	2		T101	2
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T247	1		T119	1		T249	4
all_values[14]	auto[0]	auto[1]	auto[1]	96	1			T98	2		T101	1		T169	4
all_values[14]	auto[1]	auto[0]	auto[1]	96	1			T10	2		T98	2		T101	3
all_values[14]	auto[1]	auto[1]	auto[1]	87	1			T98	1		T101	1		T169	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal