Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.34 97.15 90.87 97.67 83.58 94.42 98.45 91.26


Total test records in report: 1473
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T1310 /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3361317351 May 14 12:45:53 PM PDT 24 May 14 12:45:59 PM PDT 24 969818270 ps
T1311 /workspace/coverage/default/40.i2c_target_stress_rd.3215399359 May 14 12:48:49 PM PDT 24 May 14 12:49:11 PM PDT 24 475942372 ps
T1312 /workspace/coverage/default/37.i2c_host_fifo_overflow.4202422633 May 14 12:48:28 PM PDT 24 May 14 12:49:35 PM PDT 24 8112669577 ps
T1313 /workspace/coverage/default/13.i2c_target_stress_wr.3663206657 May 14 12:46:23 PM PDT 24 May 14 01:42:57 PM PDT 24 72120398401 ps
T1314 /workspace/coverage/default/26.i2c_host_override.185052481 May 14 12:47:21 PM PDT 24 May 14 12:47:23 PM PDT 24 25314541 ps
T1315 /workspace/coverage/default/7.i2c_host_smoke.1191321489 May 14 12:46:09 PM PDT 24 May 14 12:46:39 PM PDT 24 5345629077 ps
T1316 /workspace/coverage/default/25.i2c_host_stretch_timeout.795988266 May 14 12:47:35 PM PDT 24 May 14 12:47:48 PM PDT 24 3025863468 ps
T1317 /workspace/coverage/default/28.i2c_host_fifo_full.235654251 May 14 12:47:43 PM PDT 24 May 14 12:48:14 PM PDT 24 2322798330 ps
T1318 /workspace/coverage/default/1.i2c_target_stress_wr.2440230516 May 14 12:45:32 PM PDT 24 May 14 12:45:38 PM PDT 24 21674499348 ps
T1319 /workspace/coverage/default/40.i2c_host_fifo_full.2952161333 May 14 12:48:43 PM PDT 24 May 14 12:49:32 PM PDT 24 1648228227 ps
T1320 /workspace/coverage/default/35.i2c_alert_test.3853121157 May 14 12:48:20 PM PDT 24 May 14 12:48:22 PM PDT 24 24033568 ps
T1321 /workspace/coverage/default/4.i2c_target_stress_wr.1407643767 May 14 12:45:46 PM PDT 24 May 14 01:14:01 PM PDT 24 59069646235 ps
T1322 /workspace/coverage/default/16.i2c_target_stress_wr.1335468451 May 14 12:46:45 PM PDT 24 May 14 12:59:38 PM PDT 24 43294363545 ps
T1323 /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3090728356 May 14 12:48:24 PM PDT 24 May 14 12:48:35 PM PDT 24 766017091 ps
T1324 /workspace/coverage/default/46.i2c_host_override.4010742270 May 14 12:49:15 PM PDT 24 May 14 12:49:18 PM PDT 24 25831538 ps
T1325 /workspace/coverage/default/33.i2c_target_intr_smoke.655424265 May 14 12:48:10 PM PDT 24 May 14 12:48:17 PM PDT 24 2222484414 ps
T1326 /workspace/coverage/default/7.i2c_host_stress_all.2090366552 May 14 12:45:49 PM PDT 24 May 14 12:51:40 PM PDT 24 64792152779 ps
T1327 /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2960979554 May 14 12:47:22 PM PDT 24 May 14 12:47:31 PM PDT 24 318848520 ps
T1328 /workspace/coverage/default/19.i2c_host_mode_toggle.3144233282 May 14 12:46:57 PM PDT 24 May 14 12:48:05 PM PDT 24 5269150883 ps
T1329 /workspace/coverage/default/33.i2c_host_perf.3417026999 May 14 12:48:07 PM PDT 24 May 14 12:49:07 PM PDT 24 5140248266 ps
T61 /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3220905754 May 14 12:47:44 PM PDT 24 May 14 12:48:00 PM PDT 24 10378056130 ps
T1330 /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3183804608 May 14 12:45:32 PM PDT 24 May 14 12:45:36 PM PDT 24 120422904 ps
T1331 /workspace/coverage/default/23.i2c_host_error_intr.2892501464 May 14 12:47:16 PM PDT 24 May 14 12:47:19 PM PDT 24 116715230 ps
T1332 /workspace/coverage/default/35.i2c_host_may_nack.536408679 May 14 12:48:22 PM PDT 24 May 14 12:48:35 PM PDT 24 1194493772 ps
T1333 /workspace/coverage/default/32.i2c_host_may_nack.3673022382 May 14 12:48:04 PM PDT 24 May 14 12:48:16 PM PDT 24 3913984027 ps
T1334 /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2166775690 May 14 12:48:46 PM PDT 24 May 14 12:50:01 PM PDT 24 10135072189 ps
T125 /workspace/coverage/default/23.i2c_host_stress_all.2853507135 May 14 12:47:11 PM PDT 24 May 14 12:53:09 PM PDT 24 196383590754 ps
T1335 /workspace/coverage/default/2.i2c_host_may_nack.1428337689 May 14 12:45:40 PM PDT 24 May 14 12:45:54 PM PDT 24 736115750 ps
T1336 /workspace/coverage/default/7.i2c_target_bad_addr.3317017322 May 14 12:46:02 PM PDT 24 May 14 12:46:09 PM PDT 24 2659199117 ps
T1337 /workspace/coverage/default/22.i2c_host_may_nack.2124066967 May 14 12:47:09 PM PDT 24 May 14 12:47:25 PM PDT 24 1123015191 ps
T1338 /workspace/coverage/default/15.i2c_target_timeout.2019857973 May 14 12:46:36 PM PDT 24 May 14 12:46:46 PM PDT 24 1136736073 ps
T1339 /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3494963442 May 14 12:45:57 PM PDT 24 May 14 12:46:32 PM PDT 24 10098597727 ps
T1340 /workspace/coverage/default/8.i2c_alert_test.993604818 May 14 12:45:53 PM PDT 24 May 14 12:45:54 PM PDT 24 124262746 ps
T1341 /workspace/coverage/default/42.i2c_host_fifo_full.2010284245 May 14 12:48:56 PM PDT 24 May 14 12:49:49 PM PDT 24 3278453429 ps
T1342 /workspace/coverage/default/4.i2c_host_fifo_watermark.1843516810 May 14 12:45:39 PM PDT 24 May 14 12:51:15 PM PDT 24 4273738404 ps
T1343 /workspace/coverage/default/5.i2c_target_bad_addr.134765833 May 14 12:45:41 PM PDT 24 May 14 12:45:48 PM PDT 24 2898121130 ps
T1344 /workspace/coverage/default/20.i2c_host_fifo_reset_rx.4094960898 May 14 12:46:55 PM PDT 24 May 14 12:47:06 PM PDT 24 1232949844 ps
T1345 /workspace/coverage/default/32.i2c_alert_test.2671929070 May 14 12:48:05 PM PDT 24 May 14 12:48:07 PM PDT 24 19909148 ps
T1346 /workspace/coverage/default/7.i2c_target_timeout.808300560 May 14 12:45:58 PM PDT 24 May 14 12:46:06 PM PDT 24 1253593799 ps
T1347 /workspace/coverage/default/37.i2c_host_may_nack.3898777065 May 14 12:48:29 PM PDT 24 May 14 12:48:35 PM PDT 24 851401644 ps
T1348 /workspace/coverage/default/27.i2c_host_fifo_overflow.3535321870 May 14 12:47:32 PM PDT 24 May 14 12:49:28 PM PDT 24 6431594233 ps
T1349 /workspace/coverage/default/8.i2c_host_stress_all.461650881 May 14 12:46:11 PM PDT 24 May 14 01:04:38 PM PDT 24 39006135726 ps
T1350 /workspace/coverage/default/24.i2c_alert_test.2254469325 May 14 12:47:31 PM PDT 24 May 14 12:47:32 PM PDT 24 39726574 ps
T1351 /workspace/coverage/default/38.i2c_target_unexp_stop.3183209148 May 14 12:48:37 PM PDT 24 May 14 12:48:44 PM PDT 24 2489672853 ps
T1352 /workspace/coverage/default/24.i2c_target_timeout.2066118718 May 14 12:47:14 PM PDT 24 May 14 12:47:23 PM PDT 24 2913531338 ps
T1353 /workspace/coverage/default/33.i2c_host_fifo_overflow.868279110 May 14 12:48:02 PM PDT 24 May 14 12:50:26 PM PDT 24 3769680879 ps
T1354 /workspace/coverage/default/16.i2c_host_stretch_timeout.3305095696 May 14 12:46:36 PM PDT 24 May 14 12:47:11 PM PDT 24 2623929434 ps
T1355 /workspace/coverage/default/32.i2c_host_override.4281174091 May 14 12:47:56 PM PDT 24 May 14 12:47:59 PM PDT 24 74544854 ps
T1356 /workspace/coverage/default/14.i2c_host_fifo_overflow.3609434331 May 14 12:46:27 PM PDT 24 May 14 12:47:22 PM PDT 24 3494014699 ps
T1357 /workspace/coverage/default/20.i2c_host_may_nack.2851339385 May 14 12:47:03 PM PDT 24 May 14 12:47:10 PM PDT 24 1110461696 ps
T1358 /workspace/coverage/default/8.i2c_host_fifo_overflow.4104132246 May 14 12:46:06 PM PDT 24 May 14 12:47:17 PM PDT 24 1116474636 ps
T1359 /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1344727171 May 14 12:46:36 PM PDT 24 May 14 12:46:43 PM PDT 24 205777706 ps
T1360 /workspace/coverage/default/25.i2c_target_stress_rd.995153547 May 14 12:47:26 PM PDT 24 May 14 12:47:41 PM PDT 24 3528380867 ps
T126 /workspace/coverage/default/25.i2c_host_stress_all.1625624128 May 14 12:47:24 PM PDT 24 May 14 12:50:16 PM PDT 24 18314689031 ps
T1361 /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.4023008772 May 14 12:46:16 PM PDT 24 May 14 12:46:19 PM PDT 24 466230343 ps
T1362 /workspace/coverage/default/31.i2c_host_fifo_overflow.3670566793 May 14 12:48:04 PM PDT 24 May 14 12:49:00 PM PDT 24 1693401254 ps
T1363 /workspace/coverage/default/26.i2c_host_fifo_overflow.2172108004 May 14 12:47:21 PM PDT 24 May 14 12:47:56 PM PDT 24 6006304410 ps
T1364 /workspace/coverage/default/30.i2c_host_mode_toggle.2066695571 May 14 12:47:56 PM PDT 24 May 14 12:48:22 PM PDT 24 1114496657 ps
T1365 /workspace/coverage/default/26.i2c_target_fifo_reset_acq.4232655396 May 14 12:47:44 PM PDT 24 May 14 12:47:54 PM PDT 24 10534211707 ps
T1366 /workspace/coverage/default/25.i2c_target_hrst.2718299949 May 14 12:47:21 PM PDT 24 May 14 12:47:25 PM PDT 24 1187579742 ps
T1367 /workspace/coverage/cover_reg_top/40.i2c_intr_test.794109712 May 14 12:39:54 PM PDT 24 May 14 12:39:57 PM PDT 24 22050481 ps
T87 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2426788048 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 165880435 ps
T145 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.967079766 May 14 12:39:31 PM PDT 24 May 14 12:39:33 PM PDT 24 158437195 ps
T1368 /workspace/coverage/cover_reg_top/45.i2c_intr_test.529846367 May 14 12:39:49 PM PDT 24 May 14 12:39:53 PM PDT 24 17277460 ps
T146 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.715555382 May 14 12:39:42 PM PDT 24 May 14 12:39:44 PM PDT 24 34671863 ps
T1369 /workspace/coverage/cover_reg_top/38.i2c_intr_test.28258069 May 14 12:40:11 PM PDT 24 May 14 12:40:14 PM PDT 24 45653304 ps
T147 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1592359359 May 14 12:39:57 PM PDT 24 May 14 12:40:02 PM PDT 24 142858299 ps
T88 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.4058940921 May 14 12:39:40 PM PDT 24 May 14 12:39:42 PM PDT 24 36793908 ps
T174 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.482666583 May 14 12:39:54 PM PDT 24 May 14 12:39:57 PM PDT 24 144022504 ps
T204 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4233470149 May 14 12:39:48 PM PDT 24 May 14 12:39:53 PM PDT 24 339941163 ps
T175 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.712263842 May 14 12:39:54 PM PDT 24 May 14 12:39:57 PM PDT 24 81059816 ps
T1370 /workspace/coverage/cover_reg_top/14.i2c_intr_test.528876539 May 14 12:39:34 PM PDT 24 May 14 12:39:36 PM PDT 24 20202089 ps
T1371 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1197415378 May 14 12:39:35 PM PDT 24 May 14 12:39:36 PM PDT 24 41445202 ps
T1372 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3557531771 May 14 12:39:44 PM PDT 24 May 14 12:39:46 PM PDT 24 24458724 ps
T1373 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2760334665 May 14 12:39:29 PM PDT 24 May 14 12:39:31 PM PDT 24 23765519 ps
T89 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2055657722 May 14 12:39:55 PM PDT 24 May 14 12:39:57 PM PDT 24 213910160 ps
T90 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1292604581 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 292392946 ps
T205 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2159311810 May 14 12:39:46 PM PDT 24 May 14 12:39:48 PM PDT 24 17744666 ps
T1374 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2486979194 May 14 12:40:06 PM PDT 24 May 14 12:40:10 PM PDT 24 35855626 ps
T176 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1751317835 May 14 12:39:52 PM PDT 24 May 14 12:39:56 PM PDT 24 101014190 ps
T191 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3737951538 May 14 12:39:58 PM PDT 24 May 14 12:40:03 PM PDT 24 127021459 ps
T1375 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1758866930 May 14 12:39:52 PM PDT 24 May 14 12:40:00 PM PDT 24 78345898 ps
T192 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4195173505 May 14 12:39:49 PM PDT 24 May 14 12:39:53 PM PDT 24 27236793 ps
T195 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3670955403 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 18210334 ps
T196 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3233535400 May 14 12:40:05 PM PDT 24 May 14 12:40:09 PM PDT 24 49575507 ps
T1376 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2844565908 May 14 12:39:47 PM PDT 24 May 14 12:39:50 PM PDT 24 18855868 ps
T177 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3639056571 May 14 12:39:43 PM PDT 24 May 14 12:39:47 PM PDT 24 165732565 ps
T1377 /workspace/coverage/cover_reg_top/17.i2c_intr_test.508723445 May 14 12:39:45 PM PDT 24 May 14 12:39:47 PM PDT 24 46812033 ps
T194 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.517920327 May 14 12:39:32 PM PDT 24 May 14 12:39:33 PM PDT 24 81784874 ps
T206 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.515232000 May 14 12:39:31 PM PDT 24 May 14 12:39:32 PM PDT 24 36462595 ps
T197 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3210846437 May 14 12:39:45 PM PDT 24 May 14 12:39:47 PM PDT 24 118954543 ps
T207 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1853092739 May 14 12:39:53 PM PDT 24 May 14 12:39:56 PM PDT 24 29387201 ps
T1378 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.670408109 May 14 12:39:31 PM PDT 24 May 14 12:39:33 PM PDT 24 27166244 ps
T208 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3182031171 May 14 12:39:49 PM PDT 24 May 14 12:39:53 PM PDT 24 49194384 ps
T1379 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3464959227 May 14 12:39:49 PM PDT 24 May 14 12:39:53 PM PDT 24 32449463 ps
T198 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.638334452 May 14 12:39:47 PM PDT 24 May 14 12:39:50 PM PDT 24 62241904 ps
T182 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4153166226 May 14 12:39:37 PM PDT 24 May 14 12:39:40 PM PDT 24 133989169 ps
T1380 /workspace/coverage/cover_reg_top/6.i2c_intr_test.4025969225 May 14 12:39:50 PM PDT 24 May 14 12:39:54 PM PDT 24 24751791 ps
T1381 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2856090497 May 14 12:39:46 PM PDT 24 May 14 12:39:49 PM PDT 24 17635619 ps
T1382 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3709217934 May 14 12:40:00 PM PDT 24 May 14 12:40:03 PM PDT 24 69762278 ps
T91 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3723776636 May 14 12:39:31 PM PDT 24 May 14 12:39:33 PM PDT 24 20509947 ps
T1383 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1294607662 May 14 12:39:57 PM PDT 24 May 14 12:40:01 PM PDT 24 28098142 ps
T1384 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2609423799 May 14 12:39:55 PM PDT 24 May 14 12:39:58 PM PDT 24 17360595 ps
T199 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.478091001 May 14 12:39:50 PM PDT 24 May 14 12:39:59 PM PDT 24 36217054 ps
T92 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1308983918 May 14 12:39:33 PM PDT 24 May 14 12:39:35 PM PDT 24 266345616 ps
T93 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.108291723 May 14 12:39:30 PM PDT 24 May 14 12:39:34 PM PDT 24 171823448 ps
T94 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4118190491 May 14 12:39:47 PM PDT 24 May 14 12:39:52 PM PDT 24 273657618 ps
T193 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.161164602 May 14 12:39:52 PM PDT 24 May 14 12:39:55 PM PDT 24 22318832 ps
T113 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.808804188 May 14 12:39:48 PM PDT 24 May 14 12:39:52 PM PDT 24 125327275 ps
T114 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3186059778 May 14 12:39:46 PM PDT 24 May 14 12:39:48 PM PDT 24 20774617 ps
T181 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1961536025 May 14 12:39:51 PM PDT 24 May 14 12:39:54 PM PDT 24 68040580 ps
T95 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3489492036 May 14 12:39:34 PM PDT 24 May 14 12:39:36 PM PDT 24 232462671 ps
T1385 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1218024096 May 14 12:40:03 PM PDT 24 May 14 12:40:07 PM PDT 24 58673958 ps
T1386 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3745570828 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 38004932 ps
T1387 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.247893135 May 14 12:39:56 PM PDT 24 May 14 12:40:00 PM PDT 24 40105941 ps
T1388 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.269205745 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 59260082 ps
T96 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.488568994 May 14 12:39:48 PM PDT 24 May 14 12:39:52 PM PDT 24 189198629 ps
T115 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2653132488 May 14 12:39:42 PM PDT 24 May 14 12:39:44 PM PDT 24 90932712 ps
T187 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3576296955 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 74263840 ps
T184 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2318078108 May 14 12:39:24 PM PDT 24 May 14 12:39:27 PM PDT 24 506747099 ps
T116 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3167191191 May 14 12:39:41 PM PDT 24 May 14 12:39:42 PM PDT 24 19628021 ps
T117 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1803055658 May 14 12:40:16 PM PDT 24 May 14 12:40:19 PM PDT 24 24374343 ps
T179 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1716528121 May 14 12:39:48 PM PDT 24 May 14 12:39:53 PM PDT 24 338330622 ps
T186 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3476930026 May 14 12:39:33 PM PDT 24 May 14 12:39:34 PM PDT 24 25872800 ps
T1389 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1667768129 May 14 12:40:02 PM PDT 24 May 14 12:40:05 PM PDT 24 15209934 ps
T118 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2294161923 May 14 12:39:40 PM PDT 24 May 14 12:39:48 PM PDT 24 185636607 ps
T1390 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.596386653 May 14 12:39:20 PM PDT 24 May 14 12:39:22 PM PDT 24 65005788 ps
T1391 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1080043709 May 14 12:39:45 PM PDT 24 May 14 12:39:46 PM PDT 24 19198069 ps
T1392 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1481719430 May 14 12:39:48 PM PDT 24 May 14 12:39:52 PM PDT 24 28991591 ps
T185 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1874259502 May 14 12:39:43 PM PDT 24 May 14 12:39:45 PM PDT 24 410683274 ps
T225 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2492197928 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 51675962 ps
T1393 /workspace/coverage/cover_reg_top/2.i2c_intr_test.492547054 May 14 12:39:47 PM PDT 24 May 14 12:39:50 PM PDT 24 16363815 ps
T1394 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3672304314 May 14 12:39:43 PM PDT 24 May 14 12:39:44 PM PDT 24 83316298 ps
T1395 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4099475810 May 14 12:39:40 PM PDT 24 May 14 12:39:42 PM PDT 24 117849843 ps
T1396 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2236776130 May 14 12:39:56 PM PDT 24 May 14 12:40:00 PM PDT 24 46593020 ps
T200 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.154104172 May 14 12:39:46 PM PDT 24 May 14 12:39:53 PM PDT 24 133690830 ps
T1397 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1028698131 May 14 12:39:43 PM PDT 24 May 14 12:39:45 PM PDT 24 45510309 ps
T1398 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2867309030 May 14 12:39:45 PM PDT 24 May 14 12:39:48 PM PDT 24 125601089 ps
T1399 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4241759792 May 14 12:40:00 PM PDT 24 May 14 12:40:04 PM PDT 24 16916812 ps
T1400 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1747337525 May 14 12:39:57 PM PDT 24 May 14 12:40:02 PM PDT 24 74082130 ps
T1401 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.299133789 May 14 12:39:39 PM PDT 24 May 14 12:39:41 PM PDT 24 116663707 ps
T1402 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2222938430 May 14 12:39:33 PM PDT 24 May 14 12:39:34 PM PDT 24 38973318 ps
T201 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.4106157902 May 14 12:39:41 PM PDT 24 May 14 12:39:43 PM PDT 24 27821601 ps
T1403 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2953192116 May 14 12:39:50 PM PDT 24 May 14 12:39:55 PM PDT 24 482500281 ps
T1404 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1895942517 May 14 12:39:53 PM PDT 24 May 14 12:39:55 PM PDT 24 32342190 ps
T1405 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3832784477 May 14 12:39:47 PM PDT 24 May 14 12:39:52 PM PDT 24 56326731 ps
T1406 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3138480718 May 14 12:39:49 PM PDT 24 May 14 12:39:52 PM PDT 24 18114524 ps
T183 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3438553994 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 86506537 ps
T203 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2556144669 May 14 12:39:32 PM PDT 24 May 14 12:39:34 PM PDT 24 102026898 ps
T1407 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4193632820 May 14 12:39:48 PM PDT 24 May 14 12:39:52 PM PDT 24 25196041 ps
T188 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2825310458 May 14 12:39:24 PM PDT 24 May 14 12:39:26 PM PDT 24 57216047 ps
T1408 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1907694673 May 14 12:39:29 PM PDT 24 May 14 12:39:31 PM PDT 24 79658333 ps
T202 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3668712673 May 14 12:39:36 PM PDT 24 May 14 12:39:44 PM PDT 24 106391483 ps
T1409 /workspace/coverage/cover_reg_top/24.i2c_intr_test.3380002144 May 14 12:39:53 PM PDT 24 May 14 12:39:56 PM PDT 24 153775590 ps
T1410 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3394263129 May 14 12:39:54 PM PDT 24 May 14 12:39:56 PM PDT 24 88641282 ps
T1411 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3093500716 May 14 12:39:48 PM PDT 24 May 14 12:39:51 PM PDT 24 26894799 ps
T1412 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2969798423 May 14 12:39:46 PM PDT 24 May 14 12:39:49 PM PDT 24 27509112 ps
T1413 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2489641363 May 14 12:39:48 PM PDT 24 May 14 12:39:51 PM PDT 24 24387278 ps
T1414 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4201258314 May 14 12:39:58 PM PDT 24 May 14 12:40:01 PM PDT 24 76588526 ps
T1415 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2792758064 May 14 12:39:26 PM PDT 24 May 14 12:39:29 PM PDT 24 133381851 ps
T1416 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2574920228 May 14 12:39:56 PM PDT 24 May 14 12:40:00 PM PDT 24 52742715 ps
T1417 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1166503775 May 14 12:39:58 PM PDT 24 May 14 12:40:02 PM PDT 24 25913056 ps
T1418 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3094652602 May 14 12:39:42 PM PDT 24 May 14 12:39:44 PM PDT 24 25962559 ps
T1419 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4243984955 May 14 12:39:48 PM PDT 24 May 14 12:39:51 PM PDT 24 25245052 ps
T189 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2859216355 May 14 12:39:43 PM PDT 24 May 14 12:39:47 PM PDT 24 152240541 ps
T1420 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3170865400 May 14 12:39:39 PM PDT 24 May 14 12:39:41 PM PDT 24 21437171 ps
T190 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.959131458 May 14 12:39:44 PM PDT 24 May 14 12:39:47 PM PDT 24 625292071 ps
T1421 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1900474328 May 14 12:39:45 PM PDT 24 May 14 12:39:48 PM PDT 24 118187564 ps
T1422 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1930675494 May 14 12:39:19 PM PDT 24 May 14 12:39:22 PM PDT 24 427547263 ps
T1423 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4291558154 May 14 12:39:26 PM PDT 24 May 14 12:39:28 PM PDT 24 52275833 ps
T1424 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1646589332 May 14 12:39:28 PM PDT 24 May 14 12:39:31 PM PDT 24 170343367 ps
T1425 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.190232826 May 14 12:39:33 PM PDT 24 May 14 12:39:35 PM PDT 24 37543818 ps
T1426 /workspace/coverage/cover_reg_top/47.i2c_intr_test.294104744 May 14 12:39:50 PM PDT 24 May 14 12:39:54 PM PDT 24 22746891 ps
T1427 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.557316691 May 14 12:39:39 PM PDT 24 May 14 12:39:42 PM PDT 24 108724600 ps
T1428 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2276074323 May 14 12:39:56 PM PDT 24 May 14 12:40:00 PM PDT 24 120450873 ps
T1429 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2576923576 May 14 12:40:03 PM PDT 24 May 14 12:40:07 PM PDT 24 42741493 ps
T1430 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2756999990 May 14 12:39:40 PM PDT 24 May 14 12:39:41 PM PDT 24 41124121 ps
T1431 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1974572335 May 14 12:39:46 PM PDT 24 May 14 12:39:49 PM PDT 24 46987844 ps
T1432 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1957369100 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 320571433 ps
T1433 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3630429974 May 14 12:39:56 PM PDT 24 May 14 12:39:59 PM PDT 24 14602250 ps
T1434 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.184509987 May 14 12:39:43 PM PDT 24 May 14 12:39:45 PM PDT 24 17735274 ps
T1435 /workspace/coverage/cover_reg_top/21.i2c_intr_test.706666536 May 14 12:39:54 PM PDT 24 May 14 12:39:57 PM PDT 24 18357524 ps
T1436 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1405289044 May 14 12:39:46 PM PDT 24 May 14 12:39:50 PM PDT 24 114085330 ps
T1437 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3422465764 May 14 12:39:53 PM PDT 24 May 14 12:39:56 PM PDT 24 19127003 ps
T1438 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1426994692 May 14 12:39:57 PM PDT 24 May 14 12:40:01 PM PDT 24 159314213 ps
T1439 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3787211093 May 14 12:39:46 PM PDT 24 May 14 12:39:49 PM PDT 24 27873483 ps
T1440 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1964401414 May 14 12:39:29 PM PDT 24 May 14 12:39:31 PM PDT 24 24778971 ps
T1441 /workspace/coverage/cover_reg_top/28.i2c_intr_test.778299638 May 14 12:40:04 PM PDT 24 May 14 12:40:08 PM PDT 24 44044301 ps
T1442 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3331739415 May 14 12:39:27 PM PDT 24 May 14 12:39:29 PM PDT 24 24216868 ps
T1443 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1232534278 May 14 12:40:11 PM PDT 24 May 14 12:40:13 PM PDT 24 111465377 ps
T1444 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2393918444 May 14 12:39:40 PM PDT 24 May 14 12:39:47 PM PDT 24 18574135 ps
T1445 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2097836948 May 14 12:39:38 PM PDT 24 May 14 12:39:41 PM PDT 24 128866209 ps
T1446 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.634134941 May 14 12:39:35 PM PDT 24 May 14 12:39:37 PM PDT 24 211836613 ps
T1447 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.151860283 May 14 12:39:42 PM PDT 24 May 14 12:39:44 PM PDT 24 26026614 ps
T1448 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1724154285 May 14 12:39:56 PM PDT 24 May 14 12:40:01 PM PDT 24 429457303 ps
T1449 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.142015601 May 14 12:39:38 PM PDT 24 May 14 12:39:40 PM PDT 24 356294841 ps
T1450 /workspace/coverage/cover_reg_top/7.i2c_intr_test.514437129 May 14 12:39:36 PM PDT 24 May 14 12:39:38 PM PDT 24 41947924 ps
T1451 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2803474368 May 14 12:39:36 PM PDT 24 May 14 12:39:38 PM PDT 24 27135251 ps
T1452 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3576061303 May 14 12:40:02 PM PDT 24 May 14 12:40:06 PM PDT 24 19847696 ps
T1453 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3626036117 May 14 12:39:51 PM PDT 24 May 14 12:39:54 PM PDT 24 16598412 ps
T1454 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2118110390 May 14 12:39:27 PM PDT 24 May 14 12:39:29 PM PDT 24 82647315 ps
T1455 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3468421502 May 14 12:40:12 PM PDT 24 May 14 12:40:15 PM PDT 24 52937291 ps
T1456 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3654983720 May 14 12:39:42 PM PDT 24 May 14 12:39:44 PM PDT 24 22753654 ps
T1457 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3793068486 May 14 12:39:48 PM PDT 24 May 14 12:39:52 PM PDT 24 54895783 ps
T226 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.335014746 May 14 12:39:28 PM PDT 24 May 14 12:39:32 PM PDT 24 765175248 ps
T1458 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2465890829 May 14 12:39:24 PM PDT 24 May 14 12:39:28 PM PDT 24 254556479 ps
T1459 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3331479059 May 14 12:39:59 PM PDT 24 May 14 12:40:03 PM PDT 24 88073477 ps
T178 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3768652607 May 14 12:39:46 PM PDT 24 May 14 12:39:51 PM PDT 24 103807566 ps
T1460 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2854235563 May 14 12:39:36 PM PDT 24 May 14 12:39:37 PM PDT 24 712158648 ps
T1461 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1815317231 May 14 12:39:29 PM PDT 24 May 14 12:39:30 PM PDT 24 139049376 ps
T1462 /workspace/coverage/cover_reg_top/1.i2c_intr_test.545466078 May 14 12:39:26 PM PDT 24 May 14 12:39:27 PM PDT 24 25677462 ps
T1463 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.846466429 May 14 12:40:24 PM PDT 24 May 14 12:40:27 PM PDT 24 129649238 ps
T1464 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3393082018 May 14 12:39:50 PM PDT 24 May 14 12:39:55 PM PDT 24 693343946 ps
T1465 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2814150189 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 55389387 ps
T1466 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.113325473 May 14 12:39:40 PM PDT 24 May 14 12:39:42 PM PDT 24 75924279 ps
T1467 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1429495124 May 14 12:39:47 PM PDT 24 May 14 12:39:51 PM PDT 24 59022699 ps
T1468 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2291580888 May 14 12:40:00 PM PDT 24 May 14 12:40:04 PM PDT 24 48722475 ps
T1469 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2343683921 May 14 12:39:45 PM PDT 24 May 14 12:39:47 PM PDT 24 40246300 ps
T1470 /workspace/coverage/cover_reg_top/8.i2c_intr_test.4145016695 May 14 12:39:44 PM PDT 24 May 14 12:39:46 PM PDT 24 19041850 ps
T1471 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2607743749 May 14 12:39:39 PM PDT 24 May 14 12:39:45 PM PDT 24 1668116128 ps
T180 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2446646250 May 14 12:39:36 PM PDT 24 May 14 12:39:39 PM PDT 24 194985245 ps
T1472 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2444926165 May 14 12:39:19 PM PDT 24 May 14 12:39:20 PM PDT 24 119343703 ps
T1473 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3045210893 May 14 12:39:44 PM PDT 24 May 14 12:39:46 PM PDT 24 62672511 ps

Test location /workspace/coverage/default/49.i2c_host_stress_all.1535273927
Short name T10
Test name
Test status
Simulation time 101143709479 ps
CPU time 1110.69 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 2652436 kb
Host smart-9728c4c7-f89d-4305-93d0-1125e3a1a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535273927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1535273927
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3756546491
Short name T2
Test name
Test status
Simulation time 1836068030 ps
CPU time 4.59 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:44 PM PDT 24
Peak memory 205740 kb
Host smart-ce3b777e-251f-4005-855c-6feeb94111dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756546491 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3756546491
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3039227026
Short name T15
Test name
Test status
Simulation time 3927411762 ps
CPU time 10.75 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:45:36 PM PDT 24
Peak memory 212892 kb
Host smart-1187a964-1f99-489b-b1b0-8e8ab5f8373c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039227026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3039227026
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2426788048
Short name T87
Test name
Test status
Simulation time 165880435 ps
CPU time 1.46 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203492 kb
Host smart-d60ce061-4f2d-42ca-91a3-005c3883e37f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426788048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2426788048
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2207418772
Short name T101
Test name
Test status
Simulation time 21039914032 ps
CPU time 402.79 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:55:40 PM PDT 24
Peak memory 2290380 kb
Host smart-ece59ea7-be30-4629-9388-6b7db42cc47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207418772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2207418772
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1055331065
Short name T168
Test name
Test status
Simulation time 683498918 ps
CPU time 0.98 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:45 PM PDT 24
Peak memory 221420 kb
Host smart-09936bd7-b7b5-4034-a129-c3687a0a16ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055331065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1055331065
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.606121787
Short name T18
Test name
Test status
Simulation time 58642387451 ps
CPU time 124.13 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 1607772 kb
Host smart-134f5599-7f8e-4726-9905-c3e709b4b25e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606121787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.606121787
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_host_override.1737651195
Short name T42
Test name
Test status
Simulation time 28311471 ps
CPU time 0.7 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 204164 kb
Host smart-0e455b50-9892-4b52-8de7-1d0c8d656c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737651195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1737651195
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.4058940921
Short name T88
Test name
Test status
Simulation time 36793908 ps
CPU time 0.77 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:42 PM PDT 24
Peak memory 203680 kb
Host smart-a492c283-c818-40ee-97ae-e891600e0dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058940921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.4058940921
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1524687414
Short name T219
Test name
Test status
Simulation time 2264273125 ps
CPU time 9.21 seconds
Started May 14 12:47:38 PM PDT 24
Finished May 14 12:47:49 PM PDT 24
Peak memory 204492 kb
Host smart-d390eeeb-dfd9-4686-b070-9150244fe413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524687414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1524687414
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1790298940
Short name T31
Test name
Test status
Simulation time 10081136445 ps
CPU time 71.16 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:47:44 PM PDT 24
Peak memory 500516 kb
Host smart-f6005f21-a755-4b66-9ec1-7b7471f35ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790298940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1790298940
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3817826002
Short name T57
Test name
Test status
Simulation time 21334610397 ps
CPU time 1772.64 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 2339736 kb
Host smart-fcbbc9ac-23ca-48ef-9de0-dd6a86c8d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817826002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3817826002
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.108291723
Short name T93
Test name
Test status
Simulation time 171823448 ps
CPU time 2.54 seconds
Started May 14 12:39:30 PM PDT 24
Finished May 14 12:39:34 PM PDT 24
Peak memory 203424 kb
Host smart-ab1fb007-5874-4e6c-9294-96c2c1e6f312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108291723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.108291723
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3126648176
Short name T314
Test name
Test status
Simulation time 1430230358 ps
CPU time 7.45 seconds
Started May 14 12:45:21 PM PDT 24
Finished May 14 12:45:30 PM PDT 24
Peak memory 204424 kb
Host smart-c6d7c6cc-1676-409c-a03b-f0b1b3d4c6e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126648176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3126648176
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_host_perf.503590669
Short name T71
Test name
Test status
Simulation time 3477714255 ps
CPU time 21.34 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 12:48:37 PM PDT 24
Peak memory 229016 kb
Host smart-72d6ef3f-a20a-41a1-a3e5-5007c394b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503590669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.503590669
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.625983490
Short name T214
Test name
Test status
Simulation time 135738171 ps
CPU time 1.02 seconds
Started May 14 12:47:57 PM PDT 24
Finished May 14 12:48:00 PM PDT 24
Peak memory 204140 kb
Host smart-327b9c1f-5dc5-4dbc-a610-7c66a3828ca6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625983490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.625983490
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1282221225
Short name T397
Test name
Test status
Simulation time 2434712542 ps
CPU time 3.74 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 204536 kb
Host smart-f3d8fc60-8f46-47b8-b0d4-1af6ddcc0648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282221225 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1282221225
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3210846437
Short name T197
Test name
Test status
Simulation time 118954543 ps
CPU time 0.69 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203244 kb
Host smart-e30988fd-abb7-4830-ab09-76608a82bfa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210846437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3210846437
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.592093404
Short name T247
Test name
Test status
Simulation time 5920120001 ps
CPU time 287.71 seconds
Started May 14 12:48:40 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 1545952 kb
Host smart-d5d66bd0-0845-4312-863c-e4e6182541be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592093404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.592093404
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3169188244
Short name T124
Test name
Test status
Simulation time 8800371224 ps
CPU time 374.2 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:54:16 PM PDT 24
Peak memory 1486232 kb
Host smart-f546ee44-b0b2-4be7-881b-6f4fa411f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169188244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3169188244
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4141057311
Short name T33
Test name
Test status
Simulation time 2777205386 ps
CPU time 90.15 seconds
Started May 14 12:48:11 PM PDT 24
Finished May 14 12:49:42 PM PDT 24
Peak memory 374352 kb
Host smart-ed5a74ed-7594-4a52-800e-bd1761a4cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141057311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4141057311
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_alert_test.780861710
Short name T361
Test name
Test status
Simulation time 63185216 ps
CPU time 0.63 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:34 PM PDT 24
Peak memory 204152 kb
Host smart-d3d9ac5a-4f1d-42bd-85b5-232827dde110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780861710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.780861710
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1751317835
Short name T176
Test name
Test status
Simulation time 101014190 ps
CPU time 2.42 seconds
Started May 14 12:39:52 PM PDT 24
Finished May 14 12:39:56 PM PDT 24
Peak memory 203404 kb
Host smart-23dbed6b-bee5-4f67-bbeb-7ffad1b32c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751317835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1751317835
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2768779347
Short name T50
Test name
Test status
Simulation time 156384679 ps
CPU time 4.05 seconds
Started May 14 12:46:41 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 228852 kb
Host smart-ab3a3868-d77c-4900-8219-40745221edbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768779347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2768779347
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1405133773
Short name T211
Test name
Test status
Simulation time 10098293166 ps
CPU time 87.91 seconds
Started May 14 12:48:31 PM PDT 24
Finished May 14 12:50:00 PM PDT 24
Peak memory 570416 kb
Host smart-1e34ca6e-049c-47f1-aaf8-233251189119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405133773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1405133773
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1620187587
Short name T252
Test name
Test status
Simulation time 11571530040 ps
CPU time 615.04 seconds
Started May 14 12:45:28 PM PDT 24
Finished May 14 12:55:44 PM PDT 24
Peak memory 873440 kb
Host smart-7220fe25-0754-4348-9f8b-11331fb7b081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620187587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1620187587
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.2359822883
Short name T1121
Test name
Test status
Simulation time 2626288319 ps
CPU time 8.67 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:42 PM PDT 24
Peak memory 212424 kb
Host smart-79824f14-317b-440a-b0c1-927b8f72da05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359822883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.2359822883
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1136677866
Short name T253
Test name
Test status
Simulation time 438778889 ps
CPU time 2.71 seconds
Started May 14 12:46:41 PM PDT 24
Finished May 14 12:46:46 PM PDT 24
Peak memory 204420 kb
Host smart-d930f1c8-1a19-410b-aea0-f0539fa9ba1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136677866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1136677866
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3607990517
Short name T1143
Test name
Test status
Simulation time 436340919 ps
CPU time 1.03 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 204440 kb
Host smart-3ef55f2c-fe74-4d39-80d2-cd2422b95349
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607990517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3607990517
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_perf.1679083925
Short name T7
Test name
Test status
Simulation time 830414743 ps
CPU time 34.8 seconds
Started May 14 12:46:19 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 204332 kb
Host smart-06b04085-fd6e-4190-8e62-abce70dabbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679083925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1679083925
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.4095436722
Short name T120
Test name
Test status
Simulation time 7396780239 ps
CPU time 321.46 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:51:57 PM PDT 24
Peak memory 1686060 kb
Host smart-383487c6-03b8-422f-8710-46f5c757d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095436722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.4095436722
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1592359359
Short name T147
Test name
Test status
Simulation time 142858299 ps
CPU time 1.58 seconds
Started May 14 12:39:57 PM PDT 24
Finished May 14 12:40:02 PM PDT 24
Peak memory 203628 kb
Host smart-5bd5c74e-5845-4d48-9b40-cc8e39e1053d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592359359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1592359359
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2859216355
Short name T189
Test name
Test status
Simulation time 152240541 ps
CPU time 2.45 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203668 kb
Host smart-2243ce5a-5a76-4458-8a4c-e8bdc13e262c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859216355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2859216355
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1409270062
Short name T222
Test name
Test status
Simulation time 50624127275 ps
CPU time 129.27 seconds
Started May 14 12:46:32 PM PDT 24
Finished May 14 12:48:47 PM PDT 24
Peak memory 1720852 kb
Host smart-1c7d0f2b-30c7-464f-9b96-40bae937182d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409270062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1409270062
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.4135875579
Short name T238
Test name
Test status
Simulation time 1808746137 ps
CPU time 21.35 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:47:01 PM PDT 24
Peak memory 212588 kb
Host smart-50290808-0554-455c-b7b5-9821bfbe0412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135875579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4135875579
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1906158587
Short name T230
Test name
Test status
Simulation time 1064487223 ps
CPU time 18.55 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:34 PM PDT 24
Peak memory 214264 kb
Host smart-cce04c2b-f09f-4aea-86de-64af17800d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906158587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1906158587
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.794386891
Short name T237
Test name
Test status
Simulation time 19216967792 ps
CPU time 129.7 seconds
Started May 14 12:49:24 PM PDT 24
Finished May 14 12:51:35 PM PDT 24
Peak memory 1207508 kb
Host smart-c1ce420b-1334-4782-8b7c-576c4484b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794386891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.794386891
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3220905754
Short name T61
Test name
Test status
Simulation time 10378056130 ps
CPU time 15.1 seconds
Started May 14 12:47:44 PM PDT 24
Finished May 14 12:48:00 PM PDT 24
Peak memory 271564 kb
Host smart-9bce4233-1958-45b4-a991-b500a0173202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220905754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3220905754
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1874259502
Short name T185
Test name
Test status
Simulation time 410683274 ps
CPU time 1.5 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:45 PM PDT 24
Peak memory 203536 kb
Host smart-12b17a55-eddb-4f21-ac2e-9250ad09ea92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874259502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1874259502
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1716528121
Short name T179
Test name
Test status
Simulation time 338330622 ps
CPU time 2.24 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203172 kb
Host smart-c211a35e-b175-4557-b8b5-a812e0156ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716528121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1716528121
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3768652607
Short name T178
Test name
Test status
Simulation time 103807566 ps
CPU time 2.34 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203552 kb
Host smart-44770a0e-c8e9-44f0-b77b-6698bcafc008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768652607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3768652607
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.230205304
Short name T149
Test name
Test status
Simulation time 10105367735 ps
CPU time 78.66 seconds
Started May 14 12:47:30 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 456132 kb
Host smart-7f59f827-7891-4f8f-aa13-24cef8123508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230205304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.230205304
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1308983918
Short name T92
Test name
Test status
Simulation time 266345616 ps
CPU time 1.37 seconds
Started May 14 12:39:33 PM PDT 24
Finished May 14 12:39:35 PM PDT 24
Peak memory 203372 kb
Host smart-cff7ed9c-ffdf-496a-8043-a04667e024e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308983918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1308983918
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.154104172
Short name T200
Test name
Test status
Simulation time 133690830 ps
CPU time 5.5 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203472 kb
Host smart-7172869f-5a7d-4812-b7da-aa632f37c4f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154104172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.154104172
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.184509987
Short name T1434
Test name
Test status
Simulation time 17735274 ps
CPU time 0.71 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:45 PM PDT 24
Peak memory 203388 kb
Host smart-204fcc47-28b0-4f87-9d00-ea511d5d8d5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184509987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.184509987
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.517920327
Short name T194
Test name
Test status
Simulation time 81784874 ps
CPU time 0.78 seconds
Started May 14 12:39:32 PM PDT 24
Finished May 14 12:39:33 PM PDT 24
Peak memory 203360 kb
Host smart-88703c84-99dc-4345-bd3a-823ad97d6db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517920327 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.517920327
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1292604581
Short name T90
Test name
Test status
Simulation time 292392946 ps
CPU time 0.7 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203116 kb
Host smart-da7b99e8-5abb-45c7-b2a9-63a58abdf9d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292604581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1292604581
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1815317231
Short name T1461
Test name
Test status
Simulation time 139049376 ps
CPU time 0.65 seconds
Started May 14 12:39:29 PM PDT 24
Finished May 14 12:39:30 PM PDT 24
Peak memory 203140 kb
Host smart-da1170ad-8568-4413-869b-9bb6f1a9b19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815317231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1815317231
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2814150189
Short name T1465
Test name
Test status
Simulation time 55389387 ps
CPU time 1.18 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203428 kb
Host smart-0f3b903d-190d-47da-857e-46a47f26a786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814150189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2814150189
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2465890829
Short name T1458
Test name
Test status
Simulation time 254556479 ps
CPU time 2.34 seconds
Started May 14 12:39:24 PM PDT 24
Finished May 14 12:39:28 PM PDT 24
Peak memory 203504 kb
Host smart-98b87814-e9d6-4230-989a-da64f857281a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465890829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2465890829
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3668712673
Short name T202
Test name
Test status
Simulation time 106391483 ps
CPU time 1.42 seconds
Started May 14 12:39:36 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 202636 kb
Host smart-8544e992-432f-43bc-b83c-b83bcec2905a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668712673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3668712673
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2607743749
Short name T1471
Test name
Test status
Simulation time 1668116128 ps
CPU time 5.98 seconds
Started May 14 12:39:39 PM PDT 24
Finished May 14 12:39:45 PM PDT 24
Peak memory 203496 kb
Host smart-44e095ef-91a4-4e26-a7e1-13ec994a23fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607743749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2607743749
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2756999990
Short name T1430
Test name
Test status
Simulation time 41124121 ps
CPU time 0.7 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:41 PM PDT 24
Peak memory 203204 kb
Host smart-a3e0d83f-eaf6-445a-9ac2-4810c33b571b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756999990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2756999990
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1166503775
Short name T1417
Test name
Test status
Simulation time 25913056 ps
CPU time 0.86 seconds
Started May 14 12:39:58 PM PDT 24
Finished May 14 12:40:02 PM PDT 24
Peak memory 203188 kb
Host smart-bce58861-618c-4988-886c-29ad1da8349c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166503775 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1166503775
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3186059778
Short name T114
Test name
Test status
Simulation time 20774617 ps
CPU time 0.71 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:48 PM PDT 24
Peak memory 203280 kb
Host smart-b3530286-8b85-4c56-89e8-66754079e841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186059778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3186059778
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.545466078
Short name T1462
Test name
Test status
Simulation time 25677462 ps
CPU time 0.69 seconds
Started May 14 12:39:26 PM PDT 24
Finished May 14 12:39:27 PM PDT 24
Peak memory 203148 kb
Host smart-a559f33f-455d-4e14-8b5e-0fa1353619d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545466078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.545466078
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2854235563
Short name T1460
Test name
Test status
Simulation time 712158648 ps
CPU time 1.19 seconds
Started May 14 12:39:36 PM PDT 24
Finished May 14 12:39:37 PM PDT 24
Peak memory 203448 kb
Host smart-e5b11d0e-bded-408d-992b-56ea5a496de4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854235563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2854235563
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.808804188
Short name T113
Test name
Test status
Simulation time 125327275 ps
CPU time 1.5 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203608 kb
Host smart-fb9b9ffc-79db-4ff6-83d2-8cab49d501cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808804188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.808804188
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2492197928
Short name T225
Test name
Test status
Simulation time 51675962 ps
CPU time 1.5 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203604 kb
Host smart-94b90cc6-8d64-491c-bc82-aa8af3f198a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492197928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2492197928
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.161164602
Short name T193
Test name
Test status
Simulation time 22318832 ps
CPU time 0.94 seconds
Started May 14 12:39:52 PM PDT 24
Finished May 14 12:39:55 PM PDT 24
Peak memory 203248 kb
Host smart-bd802ab1-dbf1-462c-9c0c-5edc1dd437a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161164602 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.161164602
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.4106157902
Short name T201
Test name
Test status
Simulation time 27821601 ps
CPU time 0.82 seconds
Started May 14 12:39:41 PM PDT 24
Finished May 14 12:39:43 PM PDT 24
Peak memory 203276 kb
Host smart-2e1864f7-f297-4d80-8d10-543fe9ba8f3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106157902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.4106157902
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2222938430
Short name T1402
Test name
Test status
Simulation time 38973318 ps
CPU time 0.62 seconds
Started May 14 12:39:33 PM PDT 24
Finished May 14 12:39:34 PM PDT 24
Peak memory 203068 kb
Host smart-9fccf58e-9526-4f08-9ae1-297d8ba2759e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222938430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2222938430
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.715555382
Short name T146
Test name
Test status
Simulation time 34671863 ps
CPU time 0.87 seconds
Started May 14 12:39:42 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 202536 kb
Host smart-960af188-8476-4953-96f1-1869ae07fecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715555382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.715555382
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2953192116
Short name T1403
Test name
Test status
Simulation time 482500281 ps
CPU time 1.79 seconds
Started May 14 12:39:50 PM PDT 24
Finished May 14 12:39:55 PM PDT 24
Peak memory 203520 kb
Host smart-af05df99-6717-45cb-9a2b-f6f1c08b69d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953192116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2953192116
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4243984955
Short name T1419
Test name
Test status
Simulation time 25245052 ps
CPU time 0.81 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203124 kb
Host smart-665c2e63-9550-4eea-801f-ee05fac52fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243984955 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.4243984955
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2159311810
Short name T205
Test name
Test status
Simulation time 17744666 ps
CPU time 0.7 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:48 PM PDT 24
Peak memory 203260 kb
Host smart-a7bd877c-c790-4ddf-963d-58279c8a1e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159311810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2159311810
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2760334665
Short name T1373
Test name
Test status
Simulation time 23765519 ps
CPU time 0.68 seconds
Started May 14 12:39:29 PM PDT 24
Finished May 14 12:39:31 PM PDT 24
Peak memory 203120 kb
Host smart-60f576c0-c53b-4840-95c3-5b74b638e202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760334665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2760334665
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2291580888
Short name T1468
Test name
Test status
Simulation time 48722475 ps
CPU time 1.07 seconds
Started May 14 12:40:00 PM PDT 24
Finished May 14 12:40:04 PM PDT 24
Peak memory 203436 kb
Host smart-08e2d22a-6f38-4757-b9c2-963024847767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291580888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2291580888
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1405289044
Short name T1436
Test name
Test status
Simulation time 114085330 ps
CPU time 1.28 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203420 kb
Host smart-84fb2afb-534b-4e1f-87ac-4318d1940fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405289044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1405289044
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.269205745
Short name T1388
Test name
Test status
Simulation time 59260082 ps
CPU time 1.39 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203456 kb
Host smart-c3828444-c9d5-49b7-9b37-44e804acae60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269205745 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.269205745
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2343683921
Short name T1469
Test name
Test status
Simulation time 40246300 ps
CPU time 0.68 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203268 kb
Host smart-57996a58-9238-4c33-b480-5f7bcb355240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343683921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2343683921
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1197415378
Short name T1371
Test name
Test status
Simulation time 41445202 ps
CPU time 0.66 seconds
Started May 14 12:39:35 PM PDT 24
Finished May 14 12:39:36 PM PDT 24
Peak memory 203160 kb
Host smart-ae356973-b199-4eae-b374-bedc0eec1555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197415378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1197415378
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1294607662
Short name T1383
Test name
Test status
Simulation time 28098142 ps
CPU time 1.22 seconds
Started May 14 12:39:57 PM PDT 24
Finished May 14 12:40:01 PM PDT 24
Peak memory 203516 kb
Host smart-9f8eda40-9ae6-498c-984b-3819f0a395af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294607662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1294607662
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2867309030
Short name T1398
Test name
Test status
Simulation time 125601089 ps
CPU time 1.6 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:48 PM PDT 24
Peak memory 203476 kb
Host smart-2bff21b5-41e0-4b9c-a5c9-6688e10629de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867309030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2867309030
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4153166226
Short name T182
Test name
Test status
Simulation time 133989169 ps
CPU time 2.27 seconds
Started May 14 12:39:37 PM PDT 24
Finished May 14 12:39:40 PM PDT 24
Peak memory 203916 kb
Host smart-dccc2577-d1c3-47e8-9123-85887196cd52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153166226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4153166226
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1803055658
Short name T117
Test name
Test status
Simulation time 24374343 ps
CPU time 0.78 seconds
Started May 14 12:40:16 PM PDT 24
Finished May 14 12:40:19 PM PDT 24
Peak memory 203432 kb
Host smart-853aba34-2f6c-485f-a5b8-f997d93c0fdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803055658 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1803055658
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3670955403
Short name T195
Test name
Test status
Simulation time 18210334 ps
CPU time 0.75 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203264 kb
Host smart-254ec6c6-0001-4c98-9400-9f504f7bc433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670955403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3670955403
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2609423799
Short name T1384
Test name
Test status
Simulation time 17360595 ps
CPU time 0.68 seconds
Started May 14 12:39:55 PM PDT 24
Finished May 14 12:39:58 PM PDT 24
Peak memory 203056 kb
Host smart-3ed61b01-62db-4b92-9cb5-3a64deddc91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609423799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2609423799
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1853092739
Short name T207
Test name
Test status
Simulation time 29387201 ps
CPU time 0.85 seconds
Started May 14 12:39:53 PM PDT 24
Finished May 14 12:39:56 PM PDT 24
Peak memory 203236 kb
Host smart-9c5853a8-c21d-4c83-ba34-a377bad594b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853092739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1853092739
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.142015601
Short name T1449
Test name
Test status
Simulation time 356294841 ps
CPU time 1.67 seconds
Started May 14 12:39:38 PM PDT 24
Finished May 14 12:39:40 PM PDT 24
Peak memory 203460 kb
Host smart-f02385dc-fbd2-484b-b847-77e017596519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142015601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.142015601
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.482666583
Short name T174
Test name
Test status
Simulation time 144022504 ps
CPU time 1.56 seconds
Started May 14 12:39:54 PM PDT 24
Finished May 14 12:39:57 PM PDT 24
Peak memory 203352 kb
Host smart-82ff43a3-2e0d-46cd-96e4-67038aceed40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482666583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.482666583
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4193632820
Short name T1407
Test name
Test status
Simulation time 25196041 ps
CPU time 0.82 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203368 kb
Host smart-1802af20-8bde-4fa4-9b88-a0b1933c3a73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193632820 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4193632820
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1974572335
Short name T1431
Test name
Test status
Simulation time 46987844 ps
CPU time 0.79 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:49 PM PDT 24
Peak memory 203172 kb
Host smart-993cc32a-2a15-4bf3-bcb9-c16a0b954c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974572335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1974572335
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.528876539
Short name T1370
Test name
Test status
Simulation time 20202089 ps
CPU time 0.67 seconds
Started May 14 12:39:34 PM PDT 24
Finished May 14 12:39:36 PM PDT 24
Peak memory 203096 kb
Host smart-b6a4b2c7-6f42-4e52-8c76-0f44dca790c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528876539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.528876539
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3182031171
Short name T208
Test name
Test status
Simulation time 49194384 ps
CPU time 1.16 seconds
Started May 14 12:39:49 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203464 kb
Host smart-14c24a17-b7fd-4ce1-8b29-7338dcb99870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182031171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3182031171
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3639056571
Short name T177
Test name
Test status
Simulation time 165732565 ps
CPU time 2.41 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203604 kb
Host smart-9218fed5-21b1-4c4f-af8d-d43e70c2ab8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639056571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3639056571
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3576296955
Short name T187
Test name
Test status
Simulation time 74263840 ps
CPU time 1.57 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203560 kb
Host smart-a617c9c1-e91e-4d85-b117-e7b346075a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576296955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3576296955
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1961536025
Short name T181
Test name
Test status
Simulation time 68040580 ps
CPU time 1.07 seconds
Started May 14 12:39:51 PM PDT 24
Finished May 14 12:39:54 PM PDT 24
Peak memory 203328 kb
Host smart-f7e363be-6c00-41a5-8735-a4e0604e3546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961536025 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1961536025
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2844565908
Short name T1376
Test name
Test status
Simulation time 18855868 ps
CPU time 0.66 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203144 kb
Host smart-4aec6f26-2565-4440-8652-f787a77196ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844565908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2844565908
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1028698131
Short name T1397
Test name
Test status
Simulation time 45510309 ps
CPU time 0.9 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:45 PM PDT 24
Peak memory 203228 kb
Host smart-dd77149e-d8eb-4473-8bd3-ec99324a217b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028698131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1028698131
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2097836948
Short name T1445
Test name
Test status
Simulation time 128866209 ps
CPU time 2.33 seconds
Started May 14 12:39:38 PM PDT 24
Finished May 14 12:39:41 PM PDT 24
Peak memory 203464 kb
Host smart-3deb6a34-1bda-4963-94c2-22ddbed1e986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097836948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2097836948
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2318078108
Short name T184
Test name
Test status
Simulation time 506747099 ps
CPU time 2.41 seconds
Started May 14 12:39:24 PM PDT 24
Finished May 14 12:39:27 PM PDT 24
Peak memory 203544 kb
Host smart-1b14176f-73f7-491a-8044-93963e85343b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318078108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2318078108
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.634134941
Short name T1446
Test name
Test status
Simulation time 211836613 ps
CPU time 0.79 seconds
Started May 14 12:39:35 PM PDT 24
Finished May 14 12:39:37 PM PDT 24
Peak memory 203212 kb
Host smart-fd33602e-78a6-477c-b5a8-16638c4f7748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634134941 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.634134941
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3672304314
Short name T1394
Test name
Test status
Simulation time 83316298 ps
CPU time 0.81 seconds
Started May 14 12:39:43 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 203228 kb
Host smart-9e8d25e0-9597-4ee5-8df7-cf794261c8c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672304314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3672304314
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3793068486
Short name T1457
Test name
Test status
Simulation time 54895783 ps
CPU time 0.63 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203152 kb
Host smart-13d14d2f-f5e6-4897-af66-c0e876c1b00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793068486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3793068486
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.247893135
Short name T1387
Test name
Test status
Simulation time 40105941 ps
CPU time 1.07 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:40:00 PM PDT 24
Peak memory 203888 kb
Host smart-ad4d77e4-dcfe-42da-ade4-1c0cb4300aeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247893135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.247893135
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.557316691
Short name T1427
Test name
Test status
Simulation time 108724600 ps
CPU time 2.13 seconds
Started May 14 12:39:39 PM PDT 24
Finished May 14 12:39:42 PM PDT 24
Peak memory 203488 kb
Host smart-2e92e0d6-af4e-4bff-a997-2daf13584192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557316691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.557316691
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.967079766
Short name T145
Test name
Test status
Simulation time 158437195 ps
CPU time 1.44 seconds
Started May 14 12:39:31 PM PDT 24
Finished May 14 12:39:33 PM PDT 24
Peak memory 203484 kb
Host smart-ccf8402a-7092-46c4-974d-863996b878b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967079766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.967079766
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3737951538
Short name T191
Test name
Test status
Simulation time 127021459 ps
CPU time 0.8 seconds
Started May 14 12:39:58 PM PDT 24
Finished May 14 12:40:03 PM PDT 24
Peak memory 203256 kb
Host smart-74350122-e8af-46a5-a2ca-f26ff59b8819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737951538 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3737951538
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4201258314
Short name T1414
Test name
Test status
Simulation time 76588526 ps
CPU time 0.72 seconds
Started May 14 12:39:58 PM PDT 24
Finished May 14 12:40:01 PM PDT 24
Peak memory 203620 kb
Host smart-23b31c13-1f26-405c-afac-26159f6ecb06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201258314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4201258314
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.508723445
Short name T1377
Test name
Test status
Simulation time 46812033 ps
CPU time 0.69 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203252 kb
Host smart-9e8e8d5f-ba64-427c-9f1f-7ebb2bb3c9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508723445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.508723445
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.846466429
Short name T1463
Test name
Test status
Simulation time 129649238 ps
CPU time 0.91 seconds
Started May 14 12:40:24 PM PDT 24
Finished May 14 12:40:27 PM PDT 24
Peak memory 203132 kb
Host smart-37432cba-2879-4a17-802b-fc7449f74912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846466429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.846466429
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1964401414
Short name T1440
Test name
Test status
Simulation time 24778971 ps
CPU time 1.14 seconds
Started May 14 12:39:29 PM PDT 24
Finished May 14 12:39:31 PM PDT 24
Peak memory 203472 kb
Host smart-1f3afce0-e4ca-4b4a-a3c2-03bcf56b56dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964401414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1964401414
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1429495124
Short name T1467
Test name
Test status
Simulation time 59022699 ps
CPU time 1.41 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203548 kb
Host smart-9af1485c-d093-453f-b754-ba35cd7c18f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429495124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1429495124
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4195173505
Short name T192
Test name
Test status
Simulation time 27236793 ps
CPU time 0.84 seconds
Started May 14 12:39:49 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203256 kb
Host smart-c052b1bd-b9ac-4765-9054-c8cca314a0af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195173505 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.4195173505
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.478091001
Short name T199
Test name
Test status
Simulation time 36217054 ps
CPU time 0.68 seconds
Started May 14 12:39:50 PM PDT 24
Finished May 14 12:39:59 PM PDT 24
Peak memory 203236 kb
Host smart-3133e062-b2c6-4f45-b338-b4abbc4c670f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478091001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.478091001
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1895942517
Short name T1404
Test name
Test status
Simulation time 32342190 ps
CPU time 0.67 seconds
Started May 14 12:39:53 PM PDT 24
Finished May 14 12:39:55 PM PDT 24
Peak memory 203236 kb
Host smart-194fb9f4-1055-4ed2-b96b-38baf046b528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895942517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1895942517
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3832784477
Short name T1405
Test name
Test status
Simulation time 56326731 ps
CPU time 1.28 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 202636 kb
Host smart-9f369ee7-220d-4c33-90c2-9d458145455d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832784477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3832784477
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.488568994
Short name T96
Test name
Test status
Simulation time 189198629 ps
CPU time 1.32 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203504 kb
Host smart-ec0d3457-2285-4a25-aa2b-875e5391759b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488568994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.488568994
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3393082018
Short name T1464
Test name
Test status
Simulation time 693343946 ps
CPU time 2.55 seconds
Started May 14 12:39:50 PM PDT 24
Finished May 14 12:39:55 PM PDT 24
Peak memory 203424 kb
Host smart-c5a4d456-63ab-4f9e-973d-b97250aba6af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393082018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3393082018
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.712263842
Short name T175
Test name
Test status
Simulation time 81059816 ps
CPU time 1.31 seconds
Started May 14 12:39:54 PM PDT 24
Finished May 14 12:39:57 PM PDT 24
Peak memory 219920 kb
Host smart-bc91b46f-9ea0-4f51-81d6-2f2a0f70072c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712263842 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.712263842
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.638334452
Short name T198
Test name
Test status
Simulation time 62241904 ps
CPU time 0.76 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203268 kb
Host smart-f908c55a-0269-4553-96f9-761a04a8fb3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638334452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.638334452
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1232534278
Short name T1443
Test name
Test status
Simulation time 111465377 ps
CPU time 0.66 seconds
Started May 14 12:40:11 PM PDT 24
Finished May 14 12:40:13 PM PDT 24
Peak memory 203140 kb
Host smart-bfb9e99b-78c0-4d1c-917b-a8d7f7ee44a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232534278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1232534278
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2055657722
Short name T89
Test name
Test status
Simulation time 213910160 ps
CPU time 0.82 seconds
Started May 14 12:39:55 PM PDT 24
Finished May 14 12:39:57 PM PDT 24
Peak memory 203196 kb
Host smart-7a9a1005-b016-47f5-80ac-16a87eddddd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055657722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2055657722
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1747337525
Short name T1400
Test name
Test status
Simulation time 74082130 ps
CPU time 1.94 seconds
Started May 14 12:39:57 PM PDT 24
Finished May 14 12:40:02 PM PDT 24
Peak memory 203492 kb
Host smart-e18c16dc-82f3-4f84-97dc-932040ad3dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747337525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1747337525
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2556144669
Short name T203
Test name
Test status
Simulation time 102026898 ps
CPU time 1.35 seconds
Started May 14 12:39:32 PM PDT 24
Finished May 14 12:39:34 PM PDT 24
Peak memory 203532 kb
Host smart-0bf3afbe-5518-47cd-b90e-e53be8a6ca15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556144669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2556144669
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1724154285
Short name T1448
Test name
Test status
Simulation time 429457303 ps
CPU time 3.37 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:40:01 PM PDT 24
Peak memory 203472 kb
Host smart-ac0676e3-5f62-4bfd-be7d-abb500a0a898
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724154285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1724154285
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.670408109
Short name T1378
Test name
Test status
Simulation time 27166244 ps
CPU time 0.66 seconds
Started May 14 12:39:31 PM PDT 24
Finished May 14 12:39:33 PM PDT 24
Peak memory 203188 kb
Host smart-aa6bc8d1-a0d4-461d-9de4-4626c6a25e42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670408109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.670408109
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3331739415
Short name T1442
Test name
Test status
Simulation time 24216868 ps
CPU time 0.8 seconds
Started May 14 12:39:27 PM PDT 24
Finished May 14 12:39:29 PM PDT 24
Peak memory 203308 kb
Host smart-92a57e18-09b8-4c74-be01-d31ab382ad12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331739415 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3331739415
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2118110390
Short name T1454
Test name
Test status
Simulation time 82647315 ps
CPU time 0.75 seconds
Started May 14 12:39:27 PM PDT 24
Finished May 14 12:39:29 PM PDT 24
Peak memory 203268 kb
Host smart-ecf513e5-e57a-4c84-9e04-640a6be74ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118110390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2118110390
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.492547054
Short name T1393
Test name
Test status
Simulation time 16363815 ps
CPU time 0.69 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:50 PM PDT 24
Peak memory 203164 kb
Host smart-cfc26083-d17b-4135-aac1-412b3f313cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492547054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.492547054
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.299133789
Short name T1401
Test name
Test status
Simulation time 116663707 ps
CPU time 0.88 seconds
Started May 14 12:39:39 PM PDT 24
Finished May 14 12:39:41 PM PDT 24
Peak memory 203300 kb
Host smart-c2f7c37e-2af4-4023-a2ab-af27da700382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299133789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.299133789
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1907694673
Short name T1408
Test name
Test status
Simulation time 79658333 ps
CPU time 1.21 seconds
Started May 14 12:39:29 PM PDT 24
Finished May 14 12:39:31 PM PDT 24
Peak memory 203460 kb
Host smart-1868797e-855e-46a1-a3e4-405ab46c5185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907694673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1907694673
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.335014746
Short name T226
Test name
Test status
Simulation time 765175248 ps
CPU time 2.24 seconds
Started May 14 12:39:28 PM PDT 24
Finished May 14 12:39:32 PM PDT 24
Peak memory 203432 kb
Host smart-c0bec0da-0375-4c7a-8833-4a6c5b0d8ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335014746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.335014746
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1481719430
Short name T1392
Test name
Test status
Simulation time 28991591 ps
CPU time 0.69 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203148 kb
Host smart-8af935a8-637c-4f47-91a6-018c2f02c5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481719430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1481719430
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.706666536
Short name T1435
Test name
Test status
Simulation time 18357524 ps
CPU time 0.68 seconds
Started May 14 12:39:54 PM PDT 24
Finished May 14 12:39:57 PM PDT 24
Peak memory 203052 kb
Host smart-23e5ea1b-f06b-41d9-bdab-e7b12d839389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706666536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.706666536
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4241759792
Short name T1399
Test name
Test status
Simulation time 16916812 ps
CPU time 0.73 seconds
Started May 14 12:40:00 PM PDT 24
Finished May 14 12:40:04 PM PDT 24
Peak memory 203128 kb
Host smart-76b02ecb-934f-440b-a1c2-f55f5b077702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241759792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4241759792
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3464959227
Short name T1379
Test name
Test status
Simulation time 32449463 ps
CPU time 0.67 seconds
Started May 14 12:39:49 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203008 kb
Host smart-df97a054-c05b-4f00-bbfb-a1e12a2d54c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464959227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3464959227
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.3380002144
Short name T1409
Test name
Test status
Simulation time 153775590 ps
CPU time 0.67 seconds
Started May 14 12:39:53 PM PDT 24
Finished May 14 12:39:56 PM PDT 24
Peak memory 203284 kb
Host smart-499311ab-6d9a-45ef-8c2f-f64d3a8e9956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380002144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3380002144
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3626036117
Short name T1453
Test name
Test status
Simulation time 16598412 ps
CPU time 0.66 seconds
Started May 14 12:39:51 PM PDT 24
Finished May 14 12:39:54 PM PDT 24
Peak memory 203104 kb
Host smart-af74b8f8-20f1-416b-91e0-ea94d63882e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626036117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3626036117
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1080043709
Short name T1391
Test name
Test status
Simulation time 19198069 ps
CPU time 0.64 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:46 PM PDT 24
Peak memory 203088 kb
Host smart-f130323b-5c5d-4e94-9edd-21e7089955b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080043709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1080043709
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1426994692
Short name T1438
Test name
Test status
Simulation time 159314213 ps
CPU time 0.68 seconds
Started May 14 12:39:57 PM PDT 24
Finished May 14 12:40:01 PM PDT 24
Peak memory 203124 kb
Host smart-127a6807-061e-4e66-95ee-20e9ebcdd079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426994692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1426994692
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.778299638
Short name T1441
Test name
Test status
Simulation time 44044301 ps
CPU time 0.66 seconds
Started May 14 12:40:04 PM PDT 24
Finished May 14 12:40:08 PM PDT 24
Peak memory 203112 kb
Host smart-c4dbc000-53ec-4788-b13b-cd6528f75475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778299638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.778299638
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3557531771
Short name T1372
Test name
Test status
Simulation time 24458724 ps
CPU time 0.64 seconds
Started May 14 12:39:44 PM PDT 24
Finished May 14 12:39:46 PM PDT 24
Peak memory 203136 kb
Host smart-4da518de-f829-4773-b72c-4c2b01b23e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557531771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3557531771
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.113325473
Short name T1466
Test name
Test status
Simulation time 75924279 ps
CPU time 1.33 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:42 PM PDT 24
Peak memory 203424 kb
Host smart-af974c11-7913-4703-beef-a5199b6c1334
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113325473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.113325473
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3167191191
Short name T116
Test name
Test status
Simulation time 19628021 ps
CPU time 0.7 seconds
Started May 14 12:39:41 PM PDT 24
Finished May 14 12:39:42 PM PDT 24
Peak memory 203216 kb
Host smart-32f06376-3c83-4c3e-a88a-7fe864913409
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167191191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3167191191
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3476930026
Short name T186
Test name
Test status
Simulation time 25872800 ps
CPU time 0.8 seconds
Started May 14 12:39:33 PM PDT 24
Finished May 14 12:39:34 PM PDT 24
Peak memory 203308 kb
Host smart-7815f963-f8a7-4e56-95a9-91f820c43cd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476930026 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3476930026
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1218024096
Short name T1385
Test name
Test status
Simulation time 58673958 ps
CPU time 0.73 seconds
Started May 14 12:40:03 PM PDT 24
Finished May 14 12:40:07 PM PDT 24
Peak memory 203412 kb
Host smart-19e4e6e4-4f46-4d69-9993-632655db479b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218024096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1218024096
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2856090497
Short name T1381
Test name
Test status
Simulation time 17635619 ps
CPU time 0.69 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:49 PM PDT 24
Peak memory 203252 kb
Host smart-8badcfe4-bec9-4534-a8a8-97d183d5a863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856090497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2856090497
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.190232826
Short name T1425
Test name
Test status
Simulation time 37543818 ps
CPU time 0.83 seconds
Started May 14 12:39:33 PM PDT 24
Finished May 14 12:39:35 PM PDT 24
Peak memory 203256 kb
Host smart-33e96631-c611-4884-870d-bcc35508ca48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190232826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.190232826
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1646589332
Short name T1424
Test name
Test status
Simulation time 170343367 ps
CPU time 2.54 seconds
Started May 14 12:39:28 PM PDT 24
Finished May 14 12:39:31 PM PDT 24
Peak memory 203488 kb
Host smart-b4c9ddff-bcb2-4766-998b-48328701ef8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646589332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1646589332
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2825310458
Short name T188
Test name
Test status
Simulation time 57216047 ps
CPU time 1.47 seconds
Started May 14 12:39:24 PM PDT 24
Finished May 14 12:39:26 PM PDT 24
Peak memory 203408 kb
Host smart-befb62fd-115f-4fc9-92b4-934bb7345ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825310458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2825310458
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2969798423
Short name T1412
Test name
Test status
Simulation time 27509112 ps
CPU time 0.67 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:49 PM PDT 24
Peak memory 203136 kb
Host smart-e332a3dd-062e-4d3e-a75e-47682014b41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969798423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2969798423
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3422465764
Short name T1437
Test name
Test status
Simulation time 19127003 ps
CPU time 0.72 seconds
Started May 14 12:39:53 PM PDT 24
Finished May 14 12:39:56 PM PDT 24
Peak memory 203124 kb
Host smart-a49d0a50-4ab5-4bed-b298-5764138e2cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422465764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3422465764
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3093500716
Short name T1411
Test name
Test status
Simulation time 26894799 ps
CPU time 0.65 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203144 kb
Host smart-4d54e377-ae83-4c3a-a981-b18a7cefaca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093500716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3093500716
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2574920228
Short name T1416
Test name
Test status
Simulation time 52742715 ps
CPU time 0.71 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:40:00 PM PDT 24
Peak memory 203540 kb
Host smart-86a950aa-367d-479f-b254-e8882186f0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574920228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2574920228
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3576061303
Short name T1452
Test name
Test status
Simulation time 19847696 ps
CPU time 0.68 seconds
Started May 14 12:40:02 PM PDT 24
Finished May 14 12:40:06 PM PDT 24
Peak memory 203132 kb
Host smart-6aec3703-03cb-4cb2-a815-e36438c2395f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576061303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3576061303
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3745570828
Short name T1386
Test name
Test status
Simulation time 38004932 ps
CPU time 0.69 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203112 kb
Host smart-20b99c0a-09bc-4a10-8699-5fc3a92f3eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745570828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3745570828
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2276074323
Short name T1428
Test name
Test status
Simulation time 120450873 ps
CPU time 0.66 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:40:00 PM PDT 24
Peak memory 203088 kb
Host smart-9e55d60f-89ff-4601-bf4d-3b5e31c78a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276074323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2276074323
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2486979194
Short name T1374
Test name
Test status
Simulation time 35855626 ps
CPU time 0.64 seconds
Started May 14 12:40:06 PM PDT 24
Finished May 14 12:40:10 PM PDT 24
Peak memory 203136 kb
Host smart-8d7c1f1c-005c-4f21-9595-2c316f685c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486979194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2486979194
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.28258069
Short name T1369
Test name
Test status
Simulation time 45653304 ps
CPU time 0.63 seconds
Started May 14 12:40:11 PM PDT 24
Finished May 14 12:40:14 PM PDT 24
Peak memory 203128 kb
Host smart-3b9cd89b-d1bf-4b0d-b1f0-aaa825bdab47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28258069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.28258069
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3709217934
Short name T1382
Test name
Test status
Simulation time 69762278 ps
CPU time 0.68 seconds
Started May 14 12:40:00 PM PDT 24
Finished May 14 12:40:03 PM PDT 24
Peak memory 203112 kb
Host smart-0b140fec-a474-471c-a098-427dc3245d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709217934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3709217934
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1930675494
Short name T1422
Test name
Test status
Simulation time 427547263 ps
CPU time 2.12 seconds
Started May 14 12:39:19 PM PDT 24
Finished May 14 12:39:22 PM PDT 24
Peak memory 203492 kb
Host smart-1ccd3625-e73d-4152-9f53-78a26f294f7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930675494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1930675494
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3094652602
Short name T1418
Test name
Test status
Simulation time 25962559 ps
CPU time 0.72 seconds
Started May 14 12:39:42 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 203132 kb
Host smart-4455d696-a863-4ca2-95a6-48dc0842df66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094652602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3094652602
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4099475810
Short name T1395
Test name
Test status
Simulation time 117849843 ps
CPU time 0.93 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:42 PM PDT 24
Peak memory 203372 kb
Host smart-c1a7dfa1-5e9f-4a1e-a8f8-3279502291f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099475810 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4099475810
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.151860283
Short name T1447
Test name
Test status
Simulation time 26026614 ps
CPU time 0.74 seconds
Started May 14 12:39:42 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 202268 kb
Host smart-84603d5e-f67a-42e3-9c12-bbb07c1d9579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151860283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.151860283
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3654983720
Short name T1456
Test name
Test status
Simulation time 22753654 ps
CPU time 0.67 seconds
Started May 14 12:39:42 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 203152 kb
Host smart-5cd71a1a-0e35-4ebd-8be9-4180a0025db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654983720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3654983720
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.515232000
Short name T206
Test name
Test status
Simulation time 36462595 ps
CPU time 0.9 seconds
Started May 14 12:39:31 PM PDT 24
Finished May 14 12:39:32 PM PDT 24
Peak memory 203176 kb
Host smart-e6ec865e-1a6b-4b63-be54-703094f5c120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515232000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.515232000
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2803474368
Short name T1451
Test name
Test status
Simulation time 27135251 ps
CPU time 1.29 seconds
Started May 14 12:39:36 PM PDT 24
Finished May 14 12:39:38 PM PDT 24
Peak memory 203488 kb
Host smart-23622134-7a3d-4310-b76d-ede7746b4b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803474368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2803474368
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3438553994
Short name T183
Test name
Test status
Simulation time 86506537 ps
CPU time 1.56 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203468 kb
Host smart-af24c94d-e6a5-4423-be35-a2deebf22bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438553994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3438553994
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.794109712
Short name T1367
Test name
Test status
Simulation time 22050481 ps
CPU time 0.64 seconds
Started May 14 12:39:54 PM PDT 24
Finished May 14 12:39:57 PM PDT 24
Peak memory 203140 kb
Host smart-07e12792-7f52-40dc-b309-e714492db789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794109712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.794109712
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2576923576
Short name T1429
Test name
Test status
Simulation time 42741493 ps
CPU time 0.65 seconds
Started May 14 12:40:03 PM PDT 24
Finished May 14 12:40:07 PM PDT 24
Peak memory 203144 kb
Host smart-c8fde9ea-d72f-412c-8497-00d4adcea3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576923576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2576923576
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3138480718
Short name T1406
Test name
Test status
Simulation time 18114524 ps
CPU time 0.65 seconds
Started May 14 12:39:49 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203088 kb
Host smart-4aa55953-fd6f-46cf-a3fa-3eb8503ffc3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138480718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3138480718
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1667768129
Short name T1389
Test name
Test status
Simulation time 15209934 ps
CPU time 0.65 seconds
Started May 14 12:40:02 PM PDT 24
Finished May 14 12:40:05 PM PDT 24
Peak memory 203116 kb
Host smart-a7e39593-e449-4e2e-a270-1eaacec30bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667768129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1667768129
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3630429974
Short name T1433
Test name
Test status
Simulation time 14602250 ps
CPU time 0.62 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:39:59 PM PDT 24
Peak memory 202976 kb
Host smart-9c3deeed-240d-478f-ac4f-ea247ddaac50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630429974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3630429974
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.529846367
Short name T1368
Test name
Test status
Simulation time 17277460 ps
CPU time 0.65 seconds
Started May 14 12:39:49 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203120 kb
Host smart-8254969f-8e12-4f97-8308-c18878d29ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529846367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.529846367
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2236776130
Short name T1396
Test name
Test status
Simulation time 46593020 ps
CPU time 0.65 seconds
Started May 14 12:39:56 PM PDT 24
Finished May 14 12:40:00 PM PDT 24
Peak memory 203144 kb
Host smart-01881af8-efa8-4fd4-b6fc-15467b09d9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236776130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2236776130
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.294104744
Short name T1426
Test name
Test status
Simulation time 22746891 ps
CPU time 0.72 seconds
Started May 14 12:39:50 PM PDT 24
Finished May 14 12:39:54 PM PDT 24
Peak memory 203236 kb
Host smart-a3d75bf7-09a9-4cc7-bcf2-e1f40bf759d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294104744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.294104744
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3468421502
Short name T1455
Test name
Test status
Simulation time 52937291 ps
CPU time 0.69 seconds
Started May 14 12:40:12 PM PDT 24
Finished May 14 12:40:15 PM PDT 24
Peak memory 203124 kb
Host smart-2d6510ff-299f-42f3-a727-f834479afd22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468421502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3468421502
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1758866930
Short name T1375
Test name
Test status
Simulation time 78345898 ps
CPU time 0.63 seconds
Started May 14 12:39:52 PM PDT 24
Finished May 14 12:40:00 PM PDT 24
Peak memory 203088 kb
Host smart-e649f572-b5e8-4747-8c8a-141fb89f7753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758866930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1758866930
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2393918444
Short name T1444
Test name
Test status
Simulation time 18574135 ps
CPU time 0.78 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203360 kb
Host smart-e1022a70-dd79-4ed7-aa9e-0a7f07aa6998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393918444 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2393918444
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3723776636
Short name T91
Test name
Test status
Simulation time 20509947 ps
CPU time 0.69 seconds
Started May 14 12:39:31 PM PDT 24
Finished May 14 12:39:33 PM PDT 24
Peak memory 203260 kb
Host smart-aa00fd30-3f3b-4779-844e-d420a76b27cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723776636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3723776636
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3170865400
Short name T1420
Test name
Test status
Simulation time 21437171 ps
CPU time 0.63 seconds
Started May 14 12:39:39 PM PDT 24
Finished May 14 12:39:41 PM PDT 24
Peak memory 203120 kb
Host smart-622133c7-968e-426f-bd21-cba09d863f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170865400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3170865400
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3787211093
Short name T1439
Test name
Test status
Simulation time 27873483 ps
CPU time 1.15 seconds
Started May 14 12:39:46 PM PDT 24
Finished May 14 12:39:49 PM PDT 24
Peak memory 203452 kb
Host smart-840c3187-810c-46d3-8eb1-7e9553b3fdf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787211093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3787211093
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2792758064
Short name T1415
Test name
Test status
Simulation time 133381851 ps
CPU time 1.7 seconds
Started May 14 12:39:26 PM PDT 24
Finished May 14 12:39:29 PM PDT 24
Peak memory 202656 kb
Host smart-91380ff5-c65d-4390-8a8c-62e43c790e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792758064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2792758064
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2446646250
Short name T180
Test name
Test status
Simulation time 194985245 ps
CPU time 1.59 seconds
Started May 14 12:39:36 PM PDT 24
Finished May 14 12:39:39 PM PDT 24
Peak memory 203556 kb
Host smart-b5e6b482-5171-4dc0-8b63-73e3a6f58044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446646250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2446646250
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2444926165
Short name T1472
Test name
Test status
Simulation time 119343703 ps
CPU time 0.95 seconds
Started May 14 12:39:19 PM PDT 24
Finished May 14 12:39:20 PM PDT 24
Peak memory 203324 kb
Host smart-99854f74-7968-4564-a2f4-f99c36c96956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444926165 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2444926165
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4291558154
Short name T1423
Test name
Test status
Simulation time 52275833 ps
CPU time 0.65 seconds
Started May 14 12:39:26 PM PDT 24
Finished May 14 12:39:28 PM PDT 24
Peak memory 203176 kb
Host smart-08197ae5-f41b-417d-91cd-656019e93363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291558154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4291558154
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.4025969225
Short name T1380
Test name
Test status
Simulation time 24751791 ps
CPU time 0.64 seconds
Started May 14 12:39:50 PM PDT 24
Finished May 14 12:39:54 PM PDT 24
Peak memory 203116 kb
Host smart-23539ea8-b6ad-4b81-8934-c8de58f364e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025969225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.4025969225
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.596386653
Short name T1390
Test name
Test status
Simulation time 65005788 ps
CPU time 0.87 seconds
Started May 14 12:39:20 PM PDT 24
Finished May 14 12:39:22 PM PDT 24
Peak memory 203276 kb
Host smart-ba9a0ff9-2def-499f-8a43-83ae62dd2605
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596386653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.596386653
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3394263129
Short name T1410
Test name
Test status
Simulation time 88641282 ps
CPU time 0.82 seconds
Started May 14 12:39:54 PM PDT 24
Finished May 14 12:39:56 PM PDT 24
Peak memory 203340 kb
Host smart-363efa29-22b1-41a6-92fc-48b88a065918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394263129 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3394263129
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.514437129
Short name T1450
Test name
Test status
Simulation time 41947924 ps
CPU time 0.69 seconds
Started May 14 12:39:36 PM PDT 24
Finished May 14 12:39:38 PM PDT 24
Peak memory 203152 kb
Host smart-8225adaf-d785-412a-870a-236e136fea54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514437129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.514437129
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3489492036
Short name T95
Test name
Test status
Simulation time 232462671 ps
CPU time 1.18 seconds
Started May 14 12:39:34 PM PDT 24
Finished May 14 12:39:36 PM PDT 24
Peak memory 203908 kb
Host smart-5b94c812-9d82-4c14-b39a-9134d503ab0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489492036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3489492036
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2294161923
Short name T118
Test name
Test status
Simulation time 185636607 ps
CPU time 1.94 seconds
Started May 14 12:39:40 PM PDT 24
Finished May 14 12:39:48 PM PDT 24
Peak memory 203500 kb
Host smart-a93fc913-10b7-49d9-92bb-3b05f780122e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294161923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2294161923
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2653132488
Short name T115
Test name
Test status
Simulation time 90932712 ps
CPU time 1.45 seconds
Started May 14 12:39:42 PM PDT 24
Finished May 14 12:39:44 PM PDT 24
Peak memory 203528 kb
Host smart-707f0394-e681-416b-a14b-2c66de7ded0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653132488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2653132488
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3331479059
Short name T1459
Test name
Test status
Simulation time 88073477 ps
CPU time 0.8 seconds
Started May 14 12:39:59 PM PDT 24
Finished May 14 12:40:03 PM PDT 24
Peak memory 203264 kb
Host smart-1931e611-dd22-401f-80a4-8d25289b2699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331479059 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3331479059
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3045210893
Short name T1473
Test name
Test status
Simulation time 62672511 ps
CPU time 0.76 seconds
Started May 14 12:39:44 PM PDT 24
Finished May 14 12:39:46 PM PDT 24
Peak memory 203240 kb
Host smart-899248b5-beaf-4e5d-bdf6-be1b67bafc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045210893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3045210893
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.4145016695
Short name T1470
Test name
Test status
Simulation time 19041850 ps
CPU time 0.68 seconds
Started May 14 12:39:44 PM PDT 24
Finished May 14 12:39:46 PM PDT 24
Peak memory 203060 kb
Host smart-fcc0b303-61a3-4bc2-aae8-67a9b77c767c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145016695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4145016695
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4118190491
Short name T94
Test name
Test status
Simulation time 273657618 ps
CPU time 1.17 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:52 PM PDT 24
Peak memory 203440 kb
Host smart-716a267e-5f93-41b0-b65f-a12ed8b07b62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118190491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4118190491
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1957369100
Short name T1432
Test name
Test status
Simulation time 320571433 ps
CPU time 2.03 seconds
Started May 14 12:39:47 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203484 kb
Host smart-8fd881e5-096a-4467-8b5e-7eb4f3f67047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957369100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1957369100
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2489641363
Short name T1413
Test name
Test status
Simulation time 24387278 ps
CPU time 0.97 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:51 PM PDT 24
Peak memory 203272 kb
Host smart-4e31c20c-f411-405e-b2a7-ec76bc1b6145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489641363 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2489641363
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3233535400
Short name T196
Test name
Test status
Simulation time 49575507 ps
CPU time 0.66 seconds
Started May 14 12:40:05 PM PDT 24
Finished May 14 12:40:09 PM PDT 24
Peak memory 203248 kb
Host smart-7e4897c6-2754-4d90-92d5-00d0389d8b12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233535400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3233535400
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1900474328
Short name T1421
Test name
Test status
Simulation time 118187564 ps
CPU time 0.7 seconds
Started May 14 12:39:45 PM PDT 24
Finished May 14 12:39:48 PM PDT 24
Peak memory 203272 kb
Host smart-a1c61da0-b9dd-48f3-9de4-d1abc06ad3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900474328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1900474328
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4233470149
Short name T204
Test name
Test status
Simulation time 339941163 ps
CPU time 1.13 seconds
Started May 14 12:39:48 PM PDT 24
Finished May 14 12:39:53 PM PDT 24
Peak memory 203464 kb
Host smart-02bdc626-7efc-48b8-9011-8c25570d90d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233470149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4233470149
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.959131458
Short name T190
Test name
Test status
Simulation time 625292071 ps
CPU time 2.17 seconds
Started May 14 12:39:44 PM PDT 24
Finished May 14 12:39:47 PM PDT 24
Peak memory 203480 kb
Host smart-f29aecff-baa6-4339-9ca1-4fa2c4409a24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959131458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.959131458
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2584835951
Short name T476
Test name
Test status
Simulation time 43888350 ps
CPU time 0.61 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:45:25 PM PDT 24
Peak memory 204008 kb
Host smart-d8b8c76c-12da-4272-84d6-ed20ff4325d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584835951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2584835951
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1239373518
Short name T47
Test name
Test status
Simulation time 103829101 ps
CPU time 1.43 seconds
Started May 14 12:45:15 PM PDT 24
Finished May 14 12:45:19 PM PDT 24
Peak memory 212796 kb
Host smart-8024cfde-da71-43b2-9a2b-5700379fae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239373518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1239373518
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1559175465
Short name T385
Test name
Test status
Simulation time 556114565 ps
CPU time 5.39 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:43 PM PDT 24
Peak memory 252184 kb
Host smart-c943c18a-c86b-4b2b-b6c0-a360ed0b1e61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559175465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1559175465
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2633943942
Short name T670
Test name
Test status
Simulation time 1728755079 ps
CPU time 40.87 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 528920 kb
Host smart-00111225-811e-41f0-a4b8-6722e08c3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633943942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2633943942
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2134432393
Short name T795
Test name
Test status
Simulation time 2850942024 ps
CPU time 97.47 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:47:16 PM PDT 24
Peak memory 530716 kb
Host smart-dca40fb6-d56f-4d0f-b28b-084203b18707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134432393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2134432393
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3183804608
Short name T1330
Test name
Test status
Simulation time 120422904 ps
CPU time 1.08 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:36 PM PDT 24
Peak memory 204428 kb
Host smart-cc7edbc3-ffe5-4a12-85d2-9304c1cf76ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183804608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3183804608
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.940470948
Short name T1036
Test name
Test status
Simulation time 352837697 ps
CPU time 8.58 seconds
Started May 14 12:45:22 PM PDT 24
Finished May 14 12:45:33 PM PDT 24
Peak memory 204460 kb
Host smart-49e79acc-76d5-4964-b816-97e07e4acab9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940470948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.940470948
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1034159448
Short name T1090
Test name
Test status
Simulation time 2623115430 ps
CPU time 66.46 seconds
Started May 14 12:45:29 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 800264 kb
Host smart-4f91a9be-2713-4171-a6d8-2c01c0efff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034159448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1034159448
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3672510605
Short name T1127
Test name
Test status
Simulation time 238243342 ps
CPU time 9.35 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:44 PM PDT 24
Peak memory 204396 kb
Host smart-ee2bde6d-725c-4ff8-a664-71f5b6baf6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672510605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3672510605
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1854514501
Short name T291
Test name
Test status
Simulation time 4341481893 ps
CPU time 19.76 seconds
Started May 14 12:45:33 PM PDT 24
Finished May 14 12:45:56 PM PDT 24
Peak memory 294748 kb
Host smart-4eb9f8e4-1a1f-4799-89ee-8490dd996f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854514501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1854514501
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2884911667
Short name T135
Test name
Test status
Simulation time 165468738 ps
CPU time 0.69 seconds
Started May 14 12:45:26 PM PDT 24
Finished May 14 12:45:28 PM PDT 24
Peak memory 204052 kb
Host smart-806e4044-2eb1-4411-9389-141a943c1583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884911667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2884911667
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3680407056
Short name T624
Test name
Test status
Simulation time 6387429406 ps
CPU time 19.82 seconds
Started May 14 12:45:21 PM PDT 24
Finished May 14 12:45:42 PM PDT 24
Peak memory 217652 kb
Host smart-a03abac1-2ac9-4075-a371-f2a09c5fcff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680407056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3680407056
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.432796723
Short name T679
Test name
Test status
Simulation time 3021720491 ps
CPU time 33.16 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:45:58 PM PDT 24
Peak memory 363332 kb
Host smart-7a150225-0003-401d-9e3e-4aae98a81176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432796723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.432796723
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.387877363
Short name T286
Test name
Test status
Simulation time 2483724940 ps
CPU time 12.41 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:45:37 PM PDT 24
Peak memory 220720 kb
Host smart-0fed4141-c291-4802-b50c-46e9a360cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387877363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.387877363
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3319549999
Short name T171
Test name
Test status
Simulation time 75138479 ps
CPU time 0.84 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:35 PM PDT 24
Peak memory 221488 kb
Host smart-121e3352-4100-4481-b1ae-976ab78de789
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319549999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3319549999
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1720948641
Short name T912
Test name
Test status
Simulation time 5879203474 ps
CPU time 3.86 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 204448 kb
Host smart-3838c8dc-4fd9-4f92-b5c1-f1e1b73c262b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720948641 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1720948641
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2344526686
Short name T532
Test name
Test status
Simulation time 10240627166 ps
CPU time 9.16 seconds
Started May 14 12:45:30 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 241732 kb
Host smart-cc514b64-0bef-41ff-b21b-f13474b7e7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344526686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2344526686
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.1677961101
Short name T490
Test name
Test status
Simulation time 10088125322 ps
CPU time 73.91 seconds
Started May 14 12:45:24 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 563020 kb
Host smart-1e177060-e9ed-45df-ac6c-ef7b149e0034
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677961101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.1677961101
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.266464275
Short name T21
Test name
Test status
Simulation time 8655184181 ps
CPU time 9.46 seconds
Started May 14 12:45:27 PM PDT 24
Finished May 14 12:45:37 PM PDT 24
Peak memory 213116 kb
Host smart-07847c56-abc6-45bf-a883-9458acb6df74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266464275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.266464275
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1396720475
Short name T706
Test name
Test status
Simulation time 1780800291 ps
CPU time 2.86 seconds
Started May 14 12:45:16 PM PDT 24
Finished May 14 12:45:21 PM PDT 24
Peak memory 204472 kb
Host smart-f05bc03b-78d5-4bd7-8848-ea4eb1899464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396720475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1396720475
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1188497749
Short name T107
Test name
Test status
Simulation time 7343795325 ps
CPU time 4.06 seconds
Started May 14 12:45:30 PM PDT 24
Finished May 14 12:45:35 PM PDT 24
Peak memory 206408 kb
Host smart-109ad4dc-7d72-4fc2-91b8-f80db95990d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188497749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1188497749
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.4043455303
Short name T855
Test name
Test status
Simulation time 6381844524 ps
CPU time 14.43 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:51 PM PDT 24
Peak memory 204448 kb
Host smart-131f1432-385a-46a3-ac14-a0d97708e8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043455303 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.4043455303
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.262315546
Short name T1303
Test name
Test status
Simulation time 4772306719 ps
CPU time 19.21 seconds
Started May 14 12:45:18 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 204432 kb
Host smart-41bb29aa-c59e-4d10-9f99-d6eff584f2c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262315546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.262315546
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1170908511
Short name T344
Test name
Test status
Simulation time 689255758 ps
CPU time 27.59 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:46:01 PM PDT 24
Peak memory 204492 kb
Host smart-1295bba2-23ff-4790-a66a-5d6dc9fea124
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170908511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1170908511
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1468908039
Short name T1057
Test name
Test status
Simulation time 54249672251 ps
CPU time 1619.66 seconds
Started May 14 12:45:28 PM PDT 24
Finished May 14 01:12:29 PM PDT 24
Peak memory 8527752 kb
Host smart-5d9e2f7b-c3ca-4ede-b8bc-4b3c5d74c1a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468908039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1468908039
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3681784404
Short name T233
Test name
Test status
Simulation time 31976573901 ps
CPU time 2188.18 seconds
Started May 14 12:45:18 PM PDT 24
Finished May 14 01:21:49 PM PDT 24
Peak memory 3899336 kb
Host smart-ab2501da-c8e4-4604-8e26-2ff2de7b57f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681784404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3681784404
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2193222411
Short name T667
Test name
Test status
Simulation time 15876060 ps
CPU time 0.61 seconds
Started May 14 12:45:30 PM PDT 24
Finished May 14 12:45:32 PM PDT 24
Peak memory 204184 kb
Host smart-ae278791-6841-4cee-b9f0-e639a3dd4e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193222411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2193222411
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3765650947
Short name T626
Test name
Test status
Simulation time 271396244 ps
CPU time 1.18 seconds
Started May 14 12:45:25 PM PDT 24
Finished May 14 12:45:27 PM PDT 24
Peak memory 212652 kb
Host smart-bcd181ef-e6c1-4bfa-991d-ddf0761e2f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765650947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3765650947
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2082580498
Short name T409
Test name
Test status
Simulation time 391526872 ps
CPU time 4.25 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:38 PM PDT 24
Peak memory 235248 kb
Host smart-d43e6936-574e-473b-9190-ebefba62bedb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082580498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2082580498
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3400391659
Short name T54
Test name
Test status
Simulation time 2263813944 ps
CPU time 62.65 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 660524 kb
Host smart-f589249a-fe1d-46e5-9a4b-74e868dc8a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400391659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3400391659
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2387922078
Short name T591
Test name
Test status
Simulation time 9404917267 ps
CPU time 77.89 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 791672 kb
Host smart-68fdc57f-c415-406c-987f-62ca53f68220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387922078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2387922078
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3073595153
Short name T400
Test name
Test status
Simulation time 163264697 ps
CPU time 4 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:41 PM PDT 24
Peak memory 204300 kb
Host smart-e9b39aa3-b45d-4386-9668-3a1d739be5ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073595153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3073595153
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.602920591
Short name T243
Test name
Test status
Simulation time 11325988680 ps
CPU time 62.21 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:46:42 PM PDT 24
Peak memory 881828 kb
Host smart-8b44fb48-6d66-493f-ba0a-85e6643b9d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602920591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.602920591
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1205736440
Short name T1039
Test name
Test status
Simulation time 644735407 ps
CPU time 6.82 seconds
Started May 14 12:45:31 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 204356 kb
Host smart-077ea805-7762-4336-aa6d-d67cc8cdc921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205736440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1205736440
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3593340248
Short name T1019
Test name
Test status
Simulation time 2109442403 ps
CPU time 50.6 seconds
Started May 14 12:45:22 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 312396 kb
Host smart-06ab543c-86f8-47ef-9d3b-ff701dc3c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593340248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3593340248
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3865215245
Short name T41
Test name
Test status
Simulation time 85407251 ps
CPU time 0.64 seconds
Started May 14 12:45:47 PM PDT 24
Finished May 14 12:45:49 PM PDT 24
Peak memory 203984 kb
Host smart-1bdefacc-5689-47c9-a1ab-10e2d7340c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865215245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3865215245
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1907293553
Short name T1175
Test name
Test status
Simulation time 48697971057 ps
CPU time 379.39 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:51:58 PM PDT 24
Peak memory 1264876 kb
Host smart-00fd4a43-7e32-488f-aa37-540a258ae6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907293553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1907293553
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3074037095
Short name T642
Test name
Test status
Simulation time 5379825576 ps
CPU time 26.62 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 343656 kb
Host smart-0abadd8f-3c4c-45dc-ac45-f2938796aa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074037095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3074037095
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1340665911
Short name T249
Test name
Test status
Simulation time 5310143742 ps
CPU time 158.97 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 522264 kb
Host smart-c000189a-f867-48be-b434-f8ca26f6c6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340665911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1340665911
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1999845289
Short name T1063
Test name
Test status
Simulation time 1068862518 ps
CPU time 10.87 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:47 PM PDT 24
Peak memory 213764 kb
Host smart-af333080-db08-46d8-a55d-dd84f4ae7fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999845289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1999845289
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2837567995
Short name T1007
Test name
Test status
Simulation time 494428822 ps
CPU time 2.92 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:38 PM PDT 24
Peak memory 204424 kb
Host smart-e4f44a19-e2f5-4d2f-83c4-a39cf9aa0c49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837567995 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2837567995
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3102209906
Short name T910
Test name
Test status
Simulation time 10156376235 ps
CPU time 69.86 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 445836 kb
Host smart-be9e0240-4cc8-4945-8ab4-1d79b97a6d86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102209906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3102209906
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.461753998
Short name T1076
Test name
Test status
Simulation time 10061140712 ps
CPU time 70.11 seconds
Started May 14 12:45:25 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 449804 kb
Host smart-77f415eb-cb9d-43b5-8194-e04c68e947fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461753998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.461753998
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2198092343
Short name T24
Test name
Test status
Simulation time 1476905457 ps
CPU time 2.38 seconds
Started May 14 12:45:22 PM PDT 24
Finished May 14 12:45:26 PM PDT 24
Peak memory 204440 kb
Host smart-1e65f496-23b6-42ce-9b20-dfc9502c4145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198092343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2198092343
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3262434367
Short name T420
Test name
Test status
Simulation time 747262157 ps
CPU time 4.73 seconds
Started May 14 12:45:28 PM PDT 24
Finished May 14 12:45:34 PM PDT 24
Peak memory 206136 kb
Host smart-54aa0814-4b35-4658-9410-eae84190ad6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262434367 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3262434367
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.309525024
Short name T133
Test name
Test status
Simulation time 2667653694 ps
CPU time 3.39 seconds
Started May 14 12:45:45 PM PDT 24
Finished May 14 12:45:50 PM PDT 24
Peak memory 204336 kb
Host smart-9bd1ea27-98b0-454f-bf8a-d39930af8b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309525024 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.309525024
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.973505617
Short name T427
Test name
Test status
Simulation time 1185086072 ps
CPU time 11.47 seconds
Started May 14 12:45:21 PM PDT 24
Finished May 14 12:45:34 PM PDT 24
Peak memory 204420 kb
Host smart-d73e5a8e-bf6e-4fc3-aabb-b1c84906a84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973505617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.973505617
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1661271520
Short name T725
Test name
Test status
Simulation time 803566607 ps
CPU time 12.6 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 216292 kb
Host smart-2c297c96-8e85-42cd-b622-e460ebd6c29d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661271520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1661271520
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2440230516
Short name T1318
Test name
Test status
Simulation time 21674499348 ps
CPU time 3.84 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:45:38 PM PDT 24
Peak memory 204412 kb
Host smart-05ecab5f-90de-4f1f-a8ba-41e0400ff76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440230516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2440230516
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1789667848
Short name T303
Test name
Test status
Simulation time 28128923850 ps
CPU time 2060.41 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 01:20:01 PM PDT 24
Peak memory 6863204 kb
Host smart-c96c254e-1593-470d-9d9a-774bbc9bc471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789667848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1789667848
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.434452434
Short name T43
Test name
Test status
Simulation time 1375784485 ps
CPU time 7.88 seconds
Started May 14 12:45:27 PM PDT 24
Finished May 14 12:45:36 PM PDT 24
Peak memory 220600 kb
Host smart-85cbeb3c-7d27-4703-a035-781605afbf14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434452434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.434452434
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1458513213
Short name T1277
Test name
Test status
Simulation time 61492436 ps
CPU time 0.59 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:46:16 PM PDT 24
Peak memory 204056 kb
Host smart-b2a09b28-ebc3-43e6-a964-f919cc1f8b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458513213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1458513213
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3344477568
Short name T715
Test name
Test status
Simulation time 100820276 ps
CPU time 1.41 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 212820 kb
Host smart-df8a6037-4c27-44f0-ab5a-af10a7e43bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344477568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3344477568
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3426084804
Short name T1029
Test name
Test status
Simulation time 1618512131 ps
CPU time 7.46 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:16 PM PDT 24
Peak memory 290492 kb
Host smart-1a367440-0679-4503-9787-71a70a1ac074
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426084804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3426084804
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.906626910
Short name T1218
Test name
Test status
Simulation time 1373568891 ps
CPU time 87.36 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 535196 kb
Host smart-6e0e96c8-4f7f-40b0-b0f7-325e3ed5bbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906626910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.906626910
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2407615389
Short name T404
Test name
Test status
Simulation time 1631709362 ps
CPU time 46.58 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 591276 kb
Host smart-77850aaf-b556-4c2d-adac-ee9ea0e5bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407615389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2407615389
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2369645879
Short name T1139
Test name
Test status
Simulation time 181969135 ps
CPU time 0.85 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 204092 kb
Host smart-97c14a54-347b-4c3d-9509-a620a52bb158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369645879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2369645879
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1411490282
Short name T1105
Test name
Test status
Simulation time 199081816 ps
CPU time 10.29 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 239932 kb
Host smart-03aceae2-d98f-4c37-a431-db12ded137af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411490282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1411490282
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1052093591
Short name T1168
Test name
Test status
Simulation time 25187071409 ps
CPU time 132.55 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 1206300 kb
Host smart-4ee4bd3d-a2b0-43c5-a2c8-bad1fcdda657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052093591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1052093591
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1424154992
Short name T471
Test name
Test status
Simulation time 285963526 ps
CPU time 11.78 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:25 PM PDT 24
Peak memory 204352 kb
Host smart-cae5e699-f9a9-40f4-8b47-fd2cd4d29b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424154992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1424154992
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.670230591
Short name T1009
Test name
Test status
Simulation time 6679318626 ps
CPU time 28.28 seconds
Started May 14 12:46:17 PM PDT 24
Finished May 14 12:46:46 PM PDT 24
Peak memory 366672 kb
Host smart-4dc77fc4-e73b-460f-9b85-79b7cfab708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670230591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.670230591
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3715839667
Short name T1297
Test name
Test status
Simulation time 46115501 ps
CPU time 0.66 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:17 PM PDT 24
Peak memory 204096 kb
Host smart-8cd1a3b1-f1fe-49c7-933d-76f3887a2d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715839667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3715839667
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3953131746
Short name T957
Test name
Test status
Simulation time 12549055608 ps
CPU time 66.69 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 204268 kb
Host smart-5d546a84-2e38-4069-b72c-2145002f537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953131746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3953131746
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1204551182
Short name T956
Test name
Test status
Simulation time 7223103188 ps
CPU time 29.98 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 359028 kb
Host smart-58a803ff-3ce5-4bc2-aa71-9b6995181748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204551182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1204551182
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1840051196
Short name T356
Test name
Test status
Simulation time 398717215 ps
CPU time 6.3 seconds
Started May 14 12:46:03 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 212708 kb
Host smart-37d23e84-23f6-4a62-9574-1d7a8952d86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840051196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1840051196
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.4234954654
Short name T691
Test name
Test status
Simulation time 1205523349 ps
CPU time 4.52 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:18 PM PDT 24
Peak memory 212600 kb
Host smart-7dcac3c8-5895-4972-9f67-a094d411e60a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234954654 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.4234954654
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2886217700
Short name T985
Test name
Test status
Simulation time 10052977826 ps
CPU time 82.77 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:47:37 PM PDT 24
Peak memory 420324 kb
Host smart-a85e9204-32a7-4e8c-811b-d5da9ae6e6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886217700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2886217700
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.4162509236
Short name T1043
Test name
Test status
Simulation time 10399643395 ps
CPU time 16.21 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:29 PM PDT 24
Peak memory 277636 kb
Host smart-403c4f17-81b3-423c-8824-7e7246264997
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162509236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.4162509236
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2746492458
Short name T1220
Test name
Test status
Simulation time 465364098 ps
CPU time 3 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 204484 kb
Host smart-de9dde21-78cf-446e-b8b1-32dccd1ee829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746492458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2746492458
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1661230597
Short name T827
Test name
Test status
Simulation time 1539136036 ps
CPU time 7.98 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:22 PM PDT 24
Peak memory 211788 kb
Host smart-88773ccc-dc77-489b-b95f-c57d625928f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661230597 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1661230597
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1314893278
Short name T407
Test name
Test status
Simulation time 16807755671 ps
CPU time 22.7 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:31 PM PDT 24
Peak memory 626504 kb
Host smart-015b4112-dfce-459f-a775-8caeb75e1ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314893278 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1314893278
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3998464034
Short name T428
Test name
Test status
Simulation time 3908827592 ps
CPU time 12.31 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:22 PM PDT 24
Peak memory 204456 kb
Host smart-14fbc985-d503-4c91-b22b-78666dcae2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998464034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3998464034
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1541801264
Short name T1243
Test name
Test status
Simulation time 1122608836 ps
CPU time 16.57 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:23 PM PDT 24
Peak memory 217904 kb
Host smart-82fe0498-9b66-4b7e-aec1-129ad55713e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541801264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1541801264
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.281492181
Short name T511
Test name
Test status
Simulation time 65806310177 ps
CPU time 3068.67 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 11586348 kb
Host smart-91a308d9-3cbe-48c2-9206-7444c1423add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281492181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.281492181
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.294126661
Short name T552
Test name
Test status
Simulation time 24756139870 ps
CPU time 542.55 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:55:19 PM PDT 24
Peak memory 3281620 kb
Host smart-5b59deea-2c46-42b7-b987-5816b002ffe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294126661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.294126661
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3134139912
Short name T44
Test name
Test status
Simulation time 5037082851 ps
CPU time 6.84 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:18 PM PDT 24
Peak memory 212668 kb
Host smart-2db9da46-84b3-4ae0-890e-ae8e78320568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134139912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3134139912
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.574944812
Short name T871
Test name
Test status
Simulation time 16448762 ps
CPU time 0.61 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:46:16 PM PDT 24
Peak memory 204180 kb
Host smart-5c9474e2-50df-4029-bc63-dce436aefacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574944812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.574944812
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1166983282
Short name T714
Test name
Test status
Simulation time 305947457 ps
CPU time 1.43 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:18 PM PDT 24
Peak memory 216968 kb
Host smart-2617e2aa-fa0a-4409-aca3-87836c5e1e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166983282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1166983282
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1466592519
Short name T321
Test name
Test status
Simulation time 353022289 ps
CPU time 18.23 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 275756 kb
Host smart-e54c2888-e0df-43e1-baff-a9694f3e7137
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466592519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1466592519
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3937920021
Short name T878
Test name
Test status
Simulation time 1152798856 ps
CPU time 26.47 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 213908 kb
Host smart-9b14bddd-52f1-4766-94f0-8e19ac873c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937920021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3937920021
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1005300079
Short name T1073
Test name
Test status
Simulation time 5947687094 ps
CPU time 79.65 seconds
Started May 14 12:46:14 PM PDT 24
Finished May 14 12:47:36 PM PDT 24
Peak memory 486624 kb
Host smart-1208d155-45ad-4926-8e93-9c646b53fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005300079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1005300079
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.4023008772
Short name T1361
Test name
Test status
Simulation time 466230343 ps
CPU time 0.87 seconds
Started May 14 12:46:16 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 204148 kb
Host smart-52cf78c7-cf04-4aec-b1e5-ad356fc3c95a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023008772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.4023008772
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1276329283
Short name T943
Test name
Test status
Simulation time 177644036 ps
CPU time 4.06 seconds
Started May 14 12:46:16 PM PDT 24
Finished May 14 12:46:22 PM PDT 24
Peak memory 204384 kb
Host smart-2bb0baa3-6a0c-4aca-b9db-77e4fc10b76c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276329283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1276329283
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.822559936
Short name T1028
Test name
Test status
Simulation time 39910773757 ps
CPU time 100.05 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 1167572 kb
Host smart-7da557d6-c243-4c3a-83a9-17f746be6343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822559936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.822559936
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.399045857
Short name T1126
Test name
Test status
Simulation time 2195683996 ps
CPU time 6.78 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 204448 kb
Host smart-cc2a244b-c9db-427a-9719-864d5adc23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399045857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.399045857
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.356800078
Short name T881
Test name
Test status
Simulation time 2972992152 ps
CPU time 61.16 seconds
Started May 14 12:46:17 PM PDT 24
Finished May 14 12:47:20 PM PDT 24
Peak memory 347096 kb
Host smart-4298d3a9-b878-41fe-88ab-288b31b46e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356800078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.356800078
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1840849924
Short name T139
Test name
Test status
Simulation time 17705341 ps
CPU time 0.67 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:13 PM PDT 24
Peak memory 204136 kb
Host smart-ffc8179f-aa03-4acb-af0f-73ccfad9c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840849924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1840849924
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3275227014
Short name T618
Test name
Test status
Simulation time 6571583312 ps
CPU time 18.88 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:32 PM PDT 24
Peak memory 219092 kb
Host smart-dedb681d-760f-447a-860b-c9ad056abeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275227014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3275227014
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3812432989
Short name T690
Test name
Test status
Simulation time 1188339404 ps
CPU time 16.93 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:34 PM PDT 24
Peak memory 285448 kb
Host smart-d1c129cb-7ce4-4e82-a903-1abf6badc459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812432989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3812432989
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1490548919
Short name T82
Test name
Test status
Simulation time 91008908413 ps
CPU time 176.26 seconds
Started May 14 12:46:24 PM PDT 24
Finished May 14 12:49:22 PM PDT 24
Peak memory 633276 kb
Host smart-786b3de4-a7a0-4dfb-8672-1674ca0edde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490548919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1490548919
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3076834764
Short name T918
Test name
Test status
Simulation time 3522636013 ps
CPU time 14.86 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:27 PM PDT 24
Peak memory 229000 kb
Host smart-f2457e89-fd24-409a-91a2-1b6687f56b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076834764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3076834764
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4283301935
Short name T1064
Test name
Test status
Simulation time 1598872709 ps
CPU time 4.5 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 212548 kb
Host smart-1255fa9e-ba71-4a21-8fbf-946c4414a1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283301935 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4283301935
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3813918549
Short name T859
Test name
Test status
Simulation time 10998830646 ps
CPU time 3.88 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:14 PM PDT 24
Peak memory 212612 kb
Host smart-22e0ea7d-dc6a-4d3a-8103-8a53d50abd58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813918549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3813918549
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2705459794
Short name T127
Test name
Test status
Simulation time 11854327955 ps
CPU time 4.79 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 239460 kb
Host smart-69bc5799-44bd-49a6-983d-35803c8a20a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705459794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2705459794
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.404104070
Short name T13
Test name
Test status
Simulation time 1232526617 ps
CPU time 2.33 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:16 PM PDT 24
Peak memory 204392 kb
Host smart-bb39314e-8a72-496d-9c63-1947fce6a5a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404104070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.404104070
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.287080770
Short name T1307
Test name
Test status
Simulation time 891855024 ps
CPU time 4.62 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 204620 kb
Host smart-4557b908-c670-412f-ad80-21ad28a9ae94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287080770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.287080770
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3297734490
Short name T157
Test name
Test status
Simulation time 12568948544 ps
CPU time 235.63 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:50:11 PM PDT 24
Peak memory 3028288 kb
Host smart-ad8a0bba-87ee-46a6-a919-0b769044b7a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297734490 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3297734490
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.736461112
Short name T882
Test name
Test status
Simulation time 753898636 ps
CPU time 9.78 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:23 PM PDT 24
Peak memory 204388 kb
Host smart-ccd895ef-635c-4b00-bb6f-9f7a4e391deb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736461112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.736461112
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2692970223
Short name T496
Test name
Test status
Simulation time 954914242 ps
CPU time 36.88 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:46:52 PM PDT 24
Peak memory 204388 kb
Host smart-6646938c-f870-4b76-a415-dd948a08efd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692970223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2692970223
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.161256984
Short name T832
Test name
Test status
Simulation time 24940289899 ps
CPU time 8.65 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 224296 kb
Host smart-763ba25d-5337-4bd2-9173-bc710cd6b7fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161256984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.161256984
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3448627571
Short name T1001
Test name
Test status
Simulation time 21291583828 ps
CPU time 1327.57 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 01:08:19 PM PDT 24
Peak memory 5002312 kb
Host smart-e74b2a66-7aad-4344-9a52-2c89c1c5cfae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448627571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3448627571
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1414875646
Short name T448
Test name
Test status
Simulation time 1947626745 ps
CPU time 7.05 seconds
Started May 14 12:46:17 PM PDT 24
Finished May 14 12:46:26 PM PDT 24
Peak memory 210420 kb
Host smart-bbbafce4-add2-4585-80d8-83ee548f9a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414875646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1414875646
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.3953548145
Short name T1266
Test name
Test status
Simulation time 711112979 ps
CPU time 3.9 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 204364 kb
Host smart-dbb3224e-4aea-4f73-8d0b-67a4cc1cc9a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953548145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.i2c_target_unexp_stop.3953548145
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.988600727
Short name T854
Test name
Test status
Simulation time 34742635 ps
CPU time 0.61 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:18 PM PDT 24
Peak memory 204208 kb
Host smart-294472b5-0072-41e8-9f51-fc6f14abc996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988600727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.988600727
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3812241807
Short name T335
Test name
Test status
Simulation time 192301051 ps
CPU time 1.46 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 212744 kb
Host smart-91d9d306-73b0-4dda-97f7-df6d14d40297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812241807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3812241807
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3457635181
Short name T1172
Test name
Test status
Simulation time 278987329 ps
CPU time 4.54 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:22 PM PDT 24
Peak memory 231092 kb
Host smart-2ca74ee3-36c1-4131-b27f-e4774ce068fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457635181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3457635181
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.143814694
Short name T1075
Test name
Test status
Simulation time 4081679612 ps
CPU time 68.33 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:47:43 PM PDT 24
Peak memory 683068 kb
Host smart-6e927237-a4db-480f-b66f-88fc347a4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143814694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.143814694
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3478242106
Short name T435
Test name
Test status
Simulation time 1428620253 ps
CPU time 44.85 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 546040 kb
Host smart-937fce74-927c-44b2-98cc-8090b901c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478242106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3478242106
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1374987650
Short name T803
Test name
Test status
Simulation time 662535541 ps
CPU time 1.17 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:14 PM PDT 24
Peak memory 204304 kb
Host smart-7a227fab-755f-4639-962d-86b5ddb204cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374987650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1374987650
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1195526941
Short name T1222
Test name
Test status
Simulation time 447004885 ps
CPU time 3.35 seconds
Started May 14 12:46:16 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 219720 kb
Host smart-f42052d4-6d38-4643-a42f-bb518ebc230c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195526941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1195526941
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1945323691
Short name T553
Test name
Test status
Simulation time 32588023835 ps
CPU time 297.56 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:51:12 PM PDT 24
Peak memory 1149824 kb
Host smart-29a9ba60-8418-4093-b536-60042cf89186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945323691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1945323691
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1173215402
Short name T1110
Test name
Test status
Simulation time 271467765 ps
CPU time 4.55 seconds
Started May 14 12:46:26 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 204476 kb
Host smart-3a90a658-9a47-4863-a963-2eaaa1dbc188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173215402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1173215402
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.529306733
Short name T40
Test name
Test status
Simulation time 3253160939 ps
CPU time 27.58 seconds
Started May 14 12:46:18 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 292368 kb
Host smart-631b9573-40f7-4f43-ba50-1c9a55c83a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529306733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.529306733
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3089753679
Short name T136
Test name
Test status
Simulation time 18171842 ps
CPU time 0.63 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:14 PM PDT 24
Peak memory 204096 kb
Host smart-3a376df7-6684-4f4d-93ab-e7f0f6bb6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089753679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3089753679
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3281217777
Short name T1112
Test name
Test status
Simulation time 759687164 ps
CPU time 13.03 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:29 PM PDT 24
Peak memory 285572 kb
Host smart-27aae39c-3e07-4493-9b46-14c2c4fddc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281217777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3281217777
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3966923717
Short name T1077
Test name
Test status
Simulation time 1019196826 ps
CPU time 7.23 seconds
Started May 14 12:46:21 PM PDT 24
Finished May 14 12:46:29 PM PDT 24
Peak memory 214424 kb
Host smart-12ae3812-1def-4a92-b083-8b7e4e8e7de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966923717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3966923717
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.175880436
Short name T654
Test name
Test status
Simulation time 10127189885 ps
CPU time 15.24 seconds
Started May 14 12:46:18 PM PDT 24
Finished May 14 12:46:34 PM PDT 24
Peak memory 274628 kb
Host smart-4f070249-2bf1-43d2-a683-a7dbc1bf7e00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175880436 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.175880436
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2223254037
Short name T66
Test name
Test status
Simulation time 10104586737 ps
CPU time 16.15 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 278240 kb
Host smart-3ac18303-d703-41f1-a125-a6a84fffebb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223254037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2223254037
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2376357552
Short name T1173
Test name
Test status
Simulation time 1113886933 ps
CPU time 3.42 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 204484 kb
Host smart-66a237a3-23e5-45c4-beaf-585dd4d535f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376357552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2376357552
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4235372448
Short name T265
Test name
Test status
Simulation time 3892382780 ps
CPU time 5.44 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 212684 kb
Host smart-414d8951-b407-4df9-958d-d853274bf1b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235372448 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4235372448
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2199590503
Short name T581
Test name
Test status
Simulation time 17685459537 ps
CPU time 236.38 seconds
Started May 14 12:46:26 PM PDT 24
Finished May 14 12:50:24 PM PDT 24
Peak memory 2667248 kb
Host smart-22855077-b434-4c57-bd34-c5e8e7189f14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199590503 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2199590503
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1647693697
Short name T1280
Test name
Test status
Simulation time 1356362654 ps
CPU time 17.84 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 204356 kb
Host smart-33c8b29a-dc1b-4d28-a842-a555e583eadc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647693697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1647693697
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1259807225
Short name T1021
Test name
Test status
Simulation time 9577600927 ps
CPU time 25.85 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:42 PM PDT 24
Peak memory 238352 kb
Host smart-842ccde0-efc3-450f-85ff-79ec2cedcc7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259807225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1259807225
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.4150573659
Short name T20
Test name
Test status
Simulation time 51717965393 ps
CPU time 1225.57 seconds
Started May 14 12:46:24 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 7970924 kb
Host smart-abcfd67b-16c9-4007-99ac-abac34f87fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150573659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.4150573659
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.845999002
Short name T563
Test name
Test status
Simulation time 25069232991 ps
CPU time 2142.32 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 01:22:16 PM PDT 24
Peak memory 3445484 kb
Host smart-7fcf6aed-b0b3-4cad-8cd5-ea28781d702c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845999002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.845999002
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.4220637438
Short name T570
Test name
Test status
Simulation time 4222691818 ps
CPU time 6.33 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 220700 kb
Host smart-58d0be40-5864-41f4-b7a9-02f3543af054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220637438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.4220637438
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1882214706
Short name T658
Test name
Test status
Simulation time 27862345 ps
CPU time 0.62 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 204172 kb
Host smart-1a96b551-e595-4793-939a-21be088e54d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882214706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1882214706
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3443162798
Short name T256
Test name
Test status
Simulation time 297949723 ps
CPU time 1.42 seconds
Started May 14 12:46:24 PM PDT 24
Finished May 14 12:46:28 PM PDT 24
Peak memory 212692 kb
Host smart-db37de5d-263c-4ebc-a594-bc2f448e19d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443162798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3443162798
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2185365751
Short name T440
Test name
Test status
Simulation time 223661401 ps
CPU time 11.22 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 12:46:35 PM PDT 24
Peak memory 242844 kb
Host smart-4873630e-de33-44aa-a9fb-a7731a7d2786
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185365751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2185365751
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2591549510
Short name T610
Test name
Test status
Simulation time 2777614974 ps
CPU time 23.33 seconds
Started May 14 12:46:17 PM PDT 24
Finished May 14 12:46:42 PM PDT 24
Peak memory 416220 kb
Host smart-3258933b-a2dc-42f5-9b0e-64d0597e0b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591549510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2591549510
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3030404616
Short name T1050
Test name
Test status
Simulation time 3190524265 ps
CPU time 44.67 seconds
Started May 14 12:46:26 PM PDT 24
Finished May 14 12:47:13 PM PDT 24
Peak memory 599740 kb
Host smart-85b7b8f9-2d60-4f09-8ce2-fd78af492448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030404616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3030404616
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2429220906
Short name T160
Test name
Test status
Simulation time 96307777 ps
CPU time 0.94 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 204116 kb
Host smart-93505ab6-89cf-452c-b728-012f20a82af5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429220906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2429220906
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3382278992
Short name T694
Test name
Test status
Simulation time 546083072 ps
CPU time 5.73 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 204292 kb
Host smart-fca12a22-2def-48cd-8d7e-9232c2be5ac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382278992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3382278992
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1238140090
Short name T828
Test name
Test status
Simulation time 9218056594 ps
CPU time 133.64 seconds
Started May 14 12:46:26 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 1158876 kb
Host smart-c443932b-39d7-4b01-8f75-f67140fbe5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238140090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1238140090
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1136648407
Short name T539
Test name
Test status
Simulation time 329475360 ps
CPU time 4.37 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 204364 kb
Host smart-b1be73a4-7c28-4eb5-95ee-813752654732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136648407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1136648407
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.100724047
Short name T301
Test name
Test status
Simulation time 1579485689 ps
CPU time 34.74 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:47:11 PM PDT 24
Peak memory 412036 kb
Host smart-44a03f2d-29f1-43f5-be1b-0400e59e536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100724047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.100724047
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.271759204
Short name T141
Test name
Test status
Simulation time 87859742 ps
CPU time 0.65 seconds
Started May 14 12:46:16 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 204044 kb
Host smart-a5887c0a-3385-4239-8e5e-90fc176da0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271759204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.271759204
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2877950799
Short name T391
Test name
Test status
Simulation time 6826819878 ps
CPU time 299.92 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:51:34 PM PDT 24
Peak memory 1733892 kb
Host smart-08f8c560-fa3a-4870-a58a-2bc4baf4290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877950799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2877950799
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2971953177
Short name T161
Test name
Test status
Simulation time 1818895669 ps
CPU time 34.46 seconds
Started May 14 12:46:26 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 414632 kb
Host smart-97902db4-d9bf-46e6-8038-facb1a0a3035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971953177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2971953177
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1771768994
Short name T1066
Test name
Test status
Simulation time 1724470163 ps
CPU time 18.97 seconds
Started May 14 12:46:24 PM PDT 24
Finished May 14 12:46:45 PM PDT 24
Peak memory 212604 kb
Host smart-55cba0b1-fe30-41db-ab98-36818ec46f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771768994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1771768994
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2994669897
Short name T1256
Test name
Test status
Simulation time 986512603 ps
CPU time 4.94 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 214632 kb
Host smart-c4283199-1397-4276-90f3-f0c452aa6c17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994669897 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2994669897
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1292370032
Short name T1106
Test name
Test status
Simulation time 10748854550 ps
CPU time 6.02 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 221772 kb
Host smart-1588a36c-c169-4814-9b7f-cfe515855d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292370032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1292370032
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3104320592
Short name T862
Test name
Test status
Simulation time 1417365776 ps
CPU time 2.28 seconds
Started May 14 12:46:27 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 204496 kb
Host smart-056bb2fe-b746-47ec-9f49-c60e62c8e2ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104320592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3104320592
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1503866684
Short name T1147
Test name
Test status
Simulation time 3171183380 ps
CPU time 4.5 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 204428 kb
Host smart-6cce633c-7f19-4c14-b930-5805b5c5e178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503866684 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1503866684
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.4283847042
Short name T434
Test name
Test status
Simulation time 9877394193 ps
CPU time 44.35 seconds
Started May 14 12:46:17 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 845612 kb
Host smart-69f04995-2b63-464e-a940-a7ea8a6a2e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283847042 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.4283847042
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3560906328
Short name T501
Test name
Test status
Simulation time 1201193735 ps
CPU time 44.92 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 204364 kb
Host smart-2a3d238e-14cf-47c5-9468-57c1cd7276be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560906328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3560906328
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1154951475
Short name T1061
Test name
Test status
Simulation time 783584076 ps
CPU time 13.65 seconds
Started May 14 12:46:18 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 211020 kb
Host smart-4d2e9dd3-f51c-4d00-b503-ffbaa838eb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154951475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1154951475
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3663206657
Short name T1313
Test name
Test status
Simulation time 72120398401 ps
CPU time 3392.23 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 01:42:57 PM PDT 24
Peak memory 12958808 kb
Host smart-e8d66f06-1941-4665-a630-87ca91798ca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663206657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3663206657
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.85367688
Short name T357
Test name
Test status
Simulation time 3155249670 ps
CPU time 9.61 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:27 PM PDT 24
Peak memory 274960 kb
Host smart-23e0d57c-adcf-46c8-b115-7e5d4dd687ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85367688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_stretch.85367688
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3455456055
Short name T1052
Test name
Test status
Simulation time 1464247620 ps
CPU time 7.47 seconds
Started May 14 12:46:27 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 209356 kb
Host smart-0b280396-e358-4fcb-a666-2c8c682b295d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455456055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3455456055
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.147173199
Short name T622
Test name
Test status
Simulation time 17465786 ps
CPU time 0.65 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 204232 kb
Host smart-78214cd8-165e-4965-8eb5-695bd4483ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147173199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.147173199
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1136561557
Short name T508
Test name
Test status
Simulation time 465944528 ps
CPU time 1.55 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 212712 kb
Host smart-250dea9e-11f3-4ab3-9d5b-7d13fcbc6ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136561557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1136561557
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1115513300
Short name T791
Test name
Test status
Simulation time 247239988 ps
CPU time 5.78 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 252316 kb
Host smart-0b53123a-eb8d-4887-8a31-6aea28009071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115513300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1115513300
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3064249141
Short name T1149
Test name
Test status
Simulation time 13372432308 ps
CPU time 39.04 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:47:16 PM PDT 24
Peak memory 505860 kb
Host smart-c76d8dad-4bc7-4150-93ff-f3802edc8406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064249141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3064249141
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3609434331
Short name T1356
Test name
Test status
Simulation time 3494014699 ps
CPU time 51.85 seconds
Started May 14 12:46:27 PM PDT 24
Finished May 14 12:47:22 PM PDT 24
Peak memory 597004 kb
Host smart-b48f26a8-4db5-487f-b4e7-13c6e2c4ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609434331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3609434331
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1143183715
Short name T268
Test name
Test status
Simulation time 141801448 ps
CPU time 1.15 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 204448 kb
Host smart-911d864b-0571-4c16-a62f-5badece997f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143183715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1143183715
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.600365955
Short name T465
Test name
Test status
Simulation time 284087752 ps
CPU time 4.35 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 229028 kb
Host smart-5ad018bc-c6a1-4573-a673-5d90757fd8f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600365955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
600365955
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1054041930
Short name T1267
Test name
Test status
Simulation time 3971467532 ps
CPU time 96.97 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:48:13 PM PDT 24
Peak memory 1143132 kb
Host smart-1cd1636e-73cf-4b5e-aa65-29b040dee87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054041930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1054041930
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.288002618
Short name T841
Test name
Test status
Simulation time 290560093 ps
CPU time 11.77 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:49 PM PDT 24
Peak memory 204260 kb
Host smart-1314b00a-0d62-47dd-b571-7a5d239b86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288002618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.288002618
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1919437394
Short name T915
Test name
Test status
Simulation time 2253268904 ps
CPU time 55.66 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:47:26 PM PDT 24
Peak memory 325816 kb
Host smart-0a3939d5-f1d3-4174-8f60-a38efb7d2158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919437394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1919437394
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.937230292
Short name T463
Test name
Test status
Simulation time 3089058532 ps
CPU time 68.9 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:47:44 PM PDT 24
Peak memory 284632 kb
Host smart-5a6dac6f-ce5f-4e9e-856d-af9a72a8b10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937230292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.937230292
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1185325705
Short name T1093
Test name
Test status
Simulation time 15893615679 ps
CPU time 1531.99 seconds
Started May 14 12:46:23 PM PDT 24
Finished May 14 01:11:56 PM PDT 24
Peak memory 1778436 kb
Host smart-66c3a907-d6c8-4c01-afc7-23fec8e2a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185325705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1185325705
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3675541065
Short name T677
Test name
Test status
Simulation time 9384024222 ps
CPU time 11.33 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 216160 kb
Host smart-690d783f-2795-4019-abef-d8eb2fcc34a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675541065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3675541065
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2092373129
Short name T930
Test name
Test status
Simulation time 1833285590 ps
CPU time 4.39 seconds
Started May 14 12:46:27 PM PDT 24
Finished May 14 12:46:34 PM PDT 24
Peak memory 212548 kb
Host smart-f3d9a3f0-a6da-45c0-b55d-dbd999c40f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092373129 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2092373129
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.4027255918
Short name T879
Test name
Test status
Simulation time 10132473296 ps
CPU time 69.32 seconds
Started May 14 12:46:27 PM PDT 24
Finished May 14 12:47:39 PM PDT 24
Peak memory 425756 kb
Host smart-1897bedb-9d9e-44ab-8f61-d585ada2b553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027255918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.4027255918
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.4257936208
Short name T1259
Test name
Test status
Simulation time 10069541779 ps
CPU time 78.06 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:47:53 PM PDT 24
Peak memory 561716 kb
Host smart-eaf40af5-f33a-494e-8640-fa5a228fe888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257936208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.4257936208
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.910667979
Short name T23
Test name
Test status
Simulation time 890777296 ps
CPU time 2.57 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 204360 kb
Host smart-02f2e556-3c3f-4397-a752-0c5a48b6a095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910667979 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.910667979
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.406848862
Short name T276
Test name
Test status
Simulation time 5554245200 ps
CPU time 6.28 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:42 PM PDT 24
Peak memory 207452 kb
Host smart-91ceec8b-fe0e-4b6c-9dd0-726239d0adb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406848862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.406848862
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2759247901
Short name T354
Test name
Test status
Simulation time 18764561358 ps
CPU time 372.09 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:52:49 PM PDT 24
Peak memory 4357200 kb
Host smart-d06add48-29f2-4cb2-a40c-3dcb418dba64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759247901 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2759247901
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2031773906
Short name T1262
Test name
Test status
Simulation time 1128680410 ps
CPU time 19.61 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 204384 kb
Host smart-213b47bf-f7a3-4917-9e4c-0d968813e66f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031773906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2031773906
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1131507384
Short name T967
Test name
Test status
Simulation time 1287118405 ps
CPU time 55.83 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:47:32 PM PDT 24
Peak memory 205860 kb
Host smart-4f0fb4db-a1b4-4149-8e0d-897ac39bbf89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131507384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1131507384
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3065875993
Short name T5
Test name
Test status
Simulation time 7179065064 ps
CPU time 78.92 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 940296 kb
Host smart-9c5995ca-8cd2-46a6-81cb-28f8d6b197bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065875993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3065875993
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4113160600
Short name T829
Test name
Test status
Simulation time 6320553607 ps
CPU time 8.11 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 218844 kb
Host smart-9c62ae3e-6f5a-483c-a4be-7578484fc7f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113160600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4113160600
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.397472354
Short name T869
Test name
Test status
Simulation time 240618980 ps
CPU time 1.36 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 212952 kb
Host smart-6b060364-2f76-4a5b-a1ed-39f33bdb40d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397472354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.397472354
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.771604698
Short name T274
Test name
Test status
Simulation time 1608530146 ps
CPU time 4.3 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 12:46:35 PM PDT 24
Peak memory 215360 kb
Host smart-6f76e5f6-ba34-406b-a8af-748f776e5f5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771604698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.771604698
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1008465265
Short name T1142
Test name
Test status
Simulation time 14655834376 ps
CPU time 77.21 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 497800 kb
Host smart-58be3029-a524-4a85-83ce-aab036fae982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008465265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1008465265
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2749427639
Short name T408
Test name
Test status
Simulation time 4725222363 ps
CPU time 73.91 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:47:48 PM PDT 24
Peak memory 485332 kb
Host smart-4e998013-ceee-41fe-b1df-e840c129f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749427639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2749427639
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3134085024
Short name T215
Test name
Test status
Simulation time 92073040 ps
CPU time 0.84 seconds
Started May 14 12:46:33 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 204128 kb
Host smart-ec89ade2-64be-4ec5-87d5-07fd669f5c15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134085024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3134085024
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.4225501940
Short name T619
Test name
Test status
Simulation time 458017173 ps
CPU time 3.48 seconds
Started May 14 12:46:22 PM PDT 24
Finished May 14 12:46:27 PM PDT 24
Peak memory 222696 kb
Host smart-5a7819ab-5af7-4fe6-a4ed-c90385512f47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225501940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.4225501940
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.584210706
Short name T102
Test name
Test status
Simulation time 15349380929 ps
CPU time 95.17 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:48:11 PM PDT 24
Peak memory 1158464 kb
Host smart-c953b466-ff8b-411a-b2d7-82c8194808a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584210706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.584210706
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.691235852
Short name T502
Test name
Test status
Simulation time 1045393175 ps
CPU time 4.41 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 204348 kb
Host smart-6ea59cf4-6f33-4e44-b4b5-f4d94e62f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691235852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.691235852
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3228212778
Short name T1202
Test name
Test status
Simulation time 29494866063 ps
CPU time 74.29 seconds
Started May 14 12:46:32 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 384572 kb
Host smart-82f7c870-9f86-451a-bb8f-4ce7c272b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228212778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3228212778
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.183224127
Short name T1204
Test name
Test status
Simulation time 29077100 ps
CPU time 0.68 seconds
Started May 14 12:46:29 PM PDT 24
Finished May 14 12:46:35 PM PDT 24
Peak memory 204092 kb
Host smart-dad5cd6d-c862-48af-bd27-5a9c29b2db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183224127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.183224127
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.617052526
Short name T796
Test name
Test status
Simulation time 928958179 ps
CPU time 5.47 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 229008 kb
Host smart-08fdde53-789a-4793-8934-b81d9f8d4174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617052526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.617052526
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3708710807
Short name T326
Test name
Test status
Simulation time 1447326681 ps
CPU time 26.59 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 302252 kb
Host smart-af30b48c-60e0-4998-9e66-04cdf070a619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708710807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3708710807
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1059938815
Short name T65
Test name
Test status
Simulation time 37819800168 ps
CPU time 411.49 seconds
Started May 14 12:46:34 PM PDT 24
Finished May 14 12:53:30 PM PDT 24
Peak memory 1503240 kb
Host smart-ef4eb3f2-0efd-4c86-b381-e92d9b704ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059938815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1059938815
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.524895130
Short name T524
Test name
Test status
Simulation time 4827329110 ps
CPU time 5.64 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:46:45 PM PDT 24
Peak memory 212572 kb
Host smart-6cbe4deb-5e55-4c4a-bb17-cca1544b4a54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524895130 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.524895130
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4193660599
Short name T724
Test name
Test status
Simulation time 10214199832 ps
CPU time 26.46 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:47:02 PM PDT 24
Peak memory 329556 kb
Host smart-a949abf4-88aa-483f-b328-d321abb20aec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193660599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4193660599
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.1385441960
Short name T958
Test name
Test status
Simulation time 10168832138 ps
CPU time 14.59 seconds
Started May 14 12:46:33 PM PDT 24
Finished May 14 12:46:53 PM PDT 24
Peak memory 262632 kb
Host smart-87f608e4-a3af-46a2-993f-946e76966993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385441960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.1385441960
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3993064075
Short name T959
Test name
Test status
Simulation time 1106174547 ps
CPU time 3 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:46:50 PM PDT 24
Peak memory 204388 kb
Host smart-04b37f8b-cae6-47d7-aba0-f703d3c2567b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993064075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3993064075
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3045675644
Short name T713
Test name
Test status
Simulation time 2755281203 ps
CPU time 3.87 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:46:43 PM PDT 24
Peak memory 204360 kb
Host smart-5b772ed6-fec4-4da2-abf5-df9408e6fa4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045675644 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3045675644
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2950608965
Short name T1229
Test name
Test status
Simulation time 3145162367 ps
CPU time 7.34 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 204272 kb
Host smart-ebefea28-071a-4663-ae4e-a94369d6607c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950608965 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2950608965
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.2162505010
Short name T547
Test name
Test status
Simulation time 1068858065 ps
CPU time 17.44 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 204340 kb
Host smart-69e00f07-9df2-4464-bdcb-610dccb6c8a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162505010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.2162505010
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1004790024
Short name T936
Test name
Test status
Simulation time 2330545967 ps
CPU time 10.94 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:46:58 PM PDT 24
Peak memory 207192 kb
Host smart-84aa4694-ec6d-47b9-a972-e6c0cb35907d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004790024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1004790024
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.942557421
Short name T766
Test name
Test status
Simulation time 66514314263 ps
CPU time 2845.12 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 01:34:15 PM PDT 24
Peak memory 11511228 kb
Host smart-467d241e-5159-43bc-abfc-c7fbfdb88abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942557421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.942557421
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.576362499
Short name T304
Test name
Test status
Simulation time 33832524231 ps
CPU time 706.72 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:58:36 PM PDT 24
Peak memory 1965916 kb
Host smart-a2bd46c6-aa1e-4ca6-8271-47493d52e82d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576362499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.576362499
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2019857973
Short name T1338
Test name
Test status
Simulation time 1136736073 ps
CPU time 6.62 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:46:46 PM PDT 24
Peak memory 220636 kb
Host smart-c760117a-2a68-4215-b728-86f05aff0592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019857973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2019857973
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.3428705723
Short name T227
Test name
Test status
Simulation time 721695612 ps
CPU time 4.49 seconds
Started May 14 12:46:37 PM PDT 24
Finished May 14 12:46:45 PM PDT 24
Peak memory 204360 kb
Host smart-cfd846fa-6776-46ee-8b30-0462e0110df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428705723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.3428705723
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1232209208
Short name T327
Test name
Test status
Simulation time 24903547 ps
CPU time 0.62 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 204176 kb
Host smart-ed3e9b9a-44cd-4759-b855-0b8afdbfb40f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232209208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1232209208
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.120413455
Short name T743
Test name
Test status
Simulation time 88982717 ps
CPU time 1.79 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 212704 kb
Host smart-6de77229-789d-4e2b-8110-22754e016730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120413455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.120413455
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1344727171
Short name T1359
Test name
Test status
Simulation time 205777706 ps
CPU time 3.83 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:46:43 PM PDT 24
Peak memory 237968 kb
Host smart-0dbefb2e-656c-4833-b21d-4da76034922f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344727171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1344727171
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1345000738
Short name T1101
Test name
Test status
Simulation time 3096766241 ps
CPU time 108.7 seconds
Started May 14 12:46:40 PM PDT 24
Finished May 14 12:48:31 PM PDT 24
Peak memory 590584 kb
Host smart-2abe4dc8-9a10-425e-b681-03315de4bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345000738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1345000738
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1266049473
Short name T365
Test name
Test status
Simulation time 1056872423 ps
CPU time 65.72 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:47:43 PM PDT 24
Peak memory 455236 kb
Host smart-732d7b9e-e74e-4569-814b-f02cca62d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266049473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1266049473
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.847989582
Short name T621
Test name
Test status
Simulation time 373345275 ps
CPU time 0.8 seconds
Started May 14 12:46:31 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 204092 kb
Host smart-d1da3bf8-2f2c-4d9c-8335-6ede8e332928
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847989582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.847989582
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3145519948
Short name T1125
Test name
Test status
Simulation time 8973385187 ps
CPU time 305.14 seconds
Started May 14 12:46:40 PM PDT 24
Finished May 14 12:51:47 PM PDT 24
Peak memory 1200736 kb
Host smart-5045a1b8-20fa-4587-9f09-fc817fdde2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145519948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3145519948
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.675354822
Short name T1136
Test name
Test status
Simulation time 402597679 ps
CPU time 6.69 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:46:58 PM PDT 24
Peak memory 204292 kb
Host smart-e887caa3-12fa-4d0c-97ec-b66f3d5c410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675354822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.675354822
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.4111830511
Short name T1018
Test name
Test status
Simulation time 1023300242 ps
CPU time 19.37 seconds
Started May 14 12:46:44 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 285536 kb
Host smart-b6e0f1c9-82cf-4516-aaaa-c050a82a91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111830511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.4111830511
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.799261941
Short name T395
Test name
Test status
Simulation time 33683931 ps
CPU time 0.7 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 204080 kb
Host smart-9a9b6f58-88cb-4e1c-bd04-372552232c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799261941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.799261941
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3586864178
Short name T328
Test name
Test status
Simulation time 471453934 ps
CPU time 2.38 seconds
Started May 14 12:46:39 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 229072 kb
Host smart-373053dd-d438-4b60-9a9a-526d4cb76da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586864178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3586864178
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1756197034
Short name T1211
Test name
Test status
Simulation time 3843921985 ps
CPU time 46.08 seconds
Started May 14 12:46:43 PM PDT 24
Finished May 14 12:47:30 PM PDT 24
Peak memory 303340 kb
Host smart-6d13328f-10aa-4408-83f7-ca8a106b0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756197034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1756197034
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2006462949
Short name T240
Test name
Test status
Simulation time 21143270818 ps
CPU time 1224.31 seconds
Started May 14 12:46:44 PM PDT 24
Finished May 14 01:07:10 PM PDT 24
Peak memory 2382552 kb
Host smart-f5e8d3dc-b729-4b0b-933e-e46e5285869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006462949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2006462949
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3305095696
Short name T1354
Test name
Test status
Simulation time 2623929434 ps
CPU time 30.93 seconds
Started May 14 12:46:36 PM PDT 24
Finished May 14 12:47:11 PM PDT 24
Peak memory 212560 kb
Host smart-75524871-0a67-45f3-8251-6dcdde7fa501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305095696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3305095696
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3709486116
Short name T1269
Test name
Test status
Simulation time 2082211842 ps
CPU time 2.69 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 204396 kb
Host smart-11b0f1ac-3379-4d61-92bb-d59174781b51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709486116 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3709486116
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1031090702
Short name T393
Test name
Test status
Simulation time 10230905844 ps
CPU time 29.14 seconds
Started May 14 12:46:38 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 326188 kb
Host smart-662b69ef-7d10-4a1e-9f6d-540df4d9a8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031090702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1031090702
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2016649270
Short name T144
Test name
Test status
Simulation time 10575160300 ps
CPU time 11.49 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:46:59 PM PDT 24
Peak memory 252208 kb
Host smart-c15aedec-5d2a-40b2-813f-2c85502f9697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016649270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2016649270
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1857068311
Short name T1268
Test name
Test status
Simulation time 5026052262 ps
CPU time 2.19 seconds
Started May 14 12:46:42 PM PDT 24
Finished May 14 12:46:45 PM PDT 24
Peak memory 204316 kb
Host smart-27143833-3e59-4a4e-a506-d9d0803b9cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857068311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1857068311
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1895660870
Short name T710
Test name
Test status
Simulation time 4534231187 ps
CPU time 6.08 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 212588 kb
Host smart-37f8bc53-9bc7-4aaa-bf6f-755ab15aa351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895660870 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1895660870
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2936320763
Short name T320
Test name
Test status
Simulation time 34564981705 ps
CPU time 25.27 seconds
Started May 14 12:46:30 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 613272 kb
Host smart-36f61844-5ee0-45b3-b324-2791f76e9cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936320763 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2936320763
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3108593640
Short name T398
Test name
Test status
Simulation time 4720056338 ps
CPU time 44.64 seconds
Started May 14 12:46:34 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 204444 kb
Host smart-f5809006-205c-431a-87ea-6ea33f91adc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108593640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3108593640
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.4281025500
Short name T785
Test name
Test status
Simulation time 1435785481 ps
CPU time 20.77 seconds
Started May 14 12:46:35 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 227456 kb
Host smart-cf4acabd-c38d-4fc9-8f97-e9f833d5ec54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281025500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.4281025500
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1335468451
Short name T1322
Test name
Test status
Simulation time 43294363545 ps
CPU time 771.54 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:59:38 PM PDT 24
Peak memory 5907176 kb
Host smart-e5b85a72-339d-4440-bd21-ad344be587c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335468451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1335468451
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2891690825
Short name T556
Test name
Test status
Simulation time 42017676110 ps
CPU time 888.85 seconds
Started May 14 12:46:28 PM PDT 24
Finished May 14 01:01:22 PM PDT 24
Peak memory 2326172 kb
Host smart-5d92b88f-302f-416c-b093-95890067129d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891690825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2891690825
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.898699684
Short name T1117
Test name
Test status
Simulation time 1511777725 ps
CPU time 7.78 seconds
Started May 14 12:46:37 PM PDT 24
Finished May 14 12:46:48 PM PDT 24
Peak memory 204532 kb
Host smart-f87fceb3-9f8a-418d-9fa0-dbdfca08ce80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898699684 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.898699684
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3591634892
Short name T399
Test name
Test status
Simulation time 28079359 ps
CPU time 0.61 seconds
Started May 14 12:46:51 PM PDT 24
Finished May 14 12:46:53 PM PDT 24
Peak memory 204156 kb
Host smart-1ff80bf2-78d7-4105-8935-4d6e62e98db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591634892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3591634892
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.254335144
Short name T370
Test name
Test status
Simulation time 325592880 ps
CPU time 1.56 seconds
Started May 14 12:46:42 PM PDT 24
Finished May 14 12:46:45 PM PDT 24
Peak memory 212644 kb
Host smart-44cae587-f812-4b71-a06a-0c0392dfad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254335144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.254335144
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.720517824
Short name T1272
Test name
Test status
Simulation time 1014122587 ps
CPU time 4.45 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:46:50 PM PDT 24
Peak memory 238948 kb
Host smart-0a5a5c70-8937-4578-9d44-22e2139b1077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720517824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.720517824
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3735325653
Short name T666
Test name
Test status
Simulation time 5548100597 ps
CPU time 45.5 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:47:37 PM PDT 24
Peak memory 537676 kb
Host smart-ec63e64c-cff2-4bf4-a83c-ae33b0f03b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735325653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3735325653
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3074977578
Short name T599
Test name
Test status
Simulation time 4701440220 ps
CPU time 29.5 seconds
Started May 14 12:46:41 PM PDT 24
Finished May 14 12:47:12 PM PDT 24
Peak memory 483220 kb
Host smart-2b16d94e-a825-4b25-853f-738e51a7b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074977578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3074977578
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1228494185
Short name T216
Test name
Test status
Simulation time 420822838 ps
CPU time 0.91 seconds
Started May 14 12:46:48 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 204152 kb
Host smart-2a34afda-c770-4a43-a587-b8b307c318b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228494185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1228494185
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.969177828
Short name T797
Test name
Test status
Simulation time 646997380 ps
CPU time 8.15 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:46:59 PM PDT 24
Peak memory 204460 kb
Host smart-de0fa82c-19b7-4ec3-9619-90fb3f03fed6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969177828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
969177828
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.407980062
Short name T826
Test name
Test status
Simulation time 7946916173 ps
CPU time 294.58 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:51:44 PM PDT 24
Peak memory 1097788 kb
Host smart-250915c5-dd23-4b82-bced-5c25a018691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407980062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.407980062
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1446410058
Short name T660
Test name
Test status
Simulation time 587825898 ps
CPU time 4.91 seconds
Started May 14 12:46:48 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 204432 kb
Host smart-d52ea1f9-83b6-4503-a3c2-7da9957fb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446410058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1446410058
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.70427488
Short name T1184
Test name
Test status
Simulation time 3001537726 ps
CPU time 14.78 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 245796 kb
Host smart-8fd3a6ce-91da-4be7-b3eb-a16c5bcfdc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70427488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.70427488
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1470129011
Short name T1304
Test name
Test status
Simulation time 25322730 ps
CPU time 0.64 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:46:50 PM PDT 24
Peak memory 204020 kb
Host smart-462ecbd6-d290-4e71-b3af-935b7899af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470129011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1470129011
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1155928019
Short name T1094
Test name
Test status
Simulation time 797803685 ps
CPU time 12.8 seconds
Started May 14 12:46:39 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 254308 kb
Host smart-44fb9270-fccb-447d-ae12-2f4fb5bba2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155928019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1155928019
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.908612062
Short name T413
Test name
Test status
Simulation time 8097162391 ps
CPU time 18.88 seconds
Started May 14 12:46:44 PM PDT 24
Finished May 14 12:47:04 PM PDT 24
Peak memory 310000 kb
Host smart-33c9ebc5-f110-4cf6-96cf-8b90ff2d9002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908612062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.908612062
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.408609254
Short name T948
Test name
Test status
Simulation time 30017721791 ps
CPU time 898.13 seconds
Started May 14 12:46:48 PM PDT 24
Finished May 14 01:01:48 PM PDT 24
Peak memory 2628808 kb
Host smart-af1eec6e-aa0f-4bab-86b6-553b60623ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408609254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.408609254
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2211804456
Short name T851
Test name
Test status
Simulation time 2316547692 ps
CPU time 26.54 seconds
Started May 14 12:46:40 PM PDT 24
Finished May 14 12:47:09 PM PDT 24
Peak memory 212620 kb
Host smart-0fce159e-0520-4597-a1f6-4ceec64f4031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211804456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2211804456
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1219357801
Short name T430
Test name
Test status
Simulation time 1612555169 ps
CPU time 2.41 seconds
Started May 14 12:46:40 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 204420 kb
Host smart-1afaa96a-b7f1-4f01-b205-1d1e56f42f6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219357801 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1219357801
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2506748726
Short name T613
Test name
Test status
Simulation time 10056655847 ps
CPU time 76.27 seconds
Started May 14 12:46:38 PM PDT 24
Finished May 14 12:47:57 PM PDT 24
Peak memory 500628 kb
Host smart-18d53417-c581-498e-8a35-b2ab70ea9ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506748726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2506748726
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.740646475
Short name T970
Test name
Test status
Simulation time 10078607518 ps
CPU time 84.84 seconds
Started May 14 12:46:52 PM PDT 24
Finished May 14 12:48:17 PM PDT 24
Peak memory 502652 kb
Host smart-ea119fd5-0e05-4d5e-ada6-cc3999931147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740646475 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.740646475
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1883566954
Short name T902
Test name
Test status
Simulation time 1649622452 ps
CPU time 4.71 seconds
Started May 14 12:46:44 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 204680 kb
Host smart-b9a1a07e-af15-4eef-bc07-6c6986e5ed31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883566954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1883566954
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.424223503
Short name T728
Test name
Test status
Simulation time 24889600800 ps
CPU time 20.03 seconds
Started May 14 12:46:43 PM PDT 24
Finished May 14 12:47:04 PM PDT 24
Peak memory 608448 kb
Host smart-68cb7cce-d1d3-4883-b5ce-59d6a607ddc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424223503 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.424223503
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2759250242
Short name T606
Test name
Test status
Simulation time 2681423173 ps
CPU time 9.76 seconds
Started May 14 12:46:39 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 204400 kb
Host smart-c9c20357-bb9d-4376-adcf-5f6d8e255aab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759250242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2759250242
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3373839140
Short name T730
Test name
Test status
Simulation time 318038574 ps
CPU time 5.12 seconds
Started May 14 12:46:40 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 204640 kb
Host smart-acaa87d1-adc2-4db7-be8e-6504e2d0a993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373839140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3373839140
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1599202206
Short name T277
Test name
Test status
Simulation time 48493085030 ps
CPU time 158.99 seconds
Started May 14 12:46:44 PM PDT 24
Finished May 14 12:49:24 PM PDT 24
Peak memory 1850524 kb
Host smart-ea7fd9a2-6871-4cda-911c-8169248179c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599202206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1599202206
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.738362664
Short name T696
Test name
Test status
Simulation time 6716210163 ps
CPU time 204.22 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:50:13 PM PDT 24
Peak memory 915852 kb
Host smart-4f844ecf-046f-4a34-9735-fba541ec618f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738362664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.738362664
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1284970533
Short name T1225
Test name
Test status
Simulation time 4672027754 ps
CPU time 6.77 seconds
Started May 14 12:46:42 PM PDT 24
Finished May 14 12:46:50 PM PDT 24
Peak memory 212544 kb
Host smart-8455bc62-0f25-4ce2-905e-1f9dda29caac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284970533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1284970533
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2969351220
Short name T748
Test name
Test status
Simulation time 17892136 ps
CPU time 0.64 seconds
Started May 14 12:46:55 PM PDT 24
Finished May 14 12:46:57 PM PDT 24
Peak memory 204048 kb
Host smart-24e19932-7b2d-4c5e-99be-5e248af33293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969351220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2969351220
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.468883899
Short name T1113
Test name
Test status
Simulation time 82957555 ps
CPU time 1.76 seconds
Started May 14 12:46:58 PM PDT 24
Finished May 14 12:47:01 PM PDT 24
Peak memory 212796 kb
Host smart-d604b850-7d96-47e3-9273-75b5aaa7ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468883899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.468883899
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.307955874
Short name T481
Test name
Test status
Simulation time 1167409800 ps
CPU time 4.67 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 254160 kb
Host smart-085c32e6-dfdb-4398-ab9e-7609bf59e347
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307955874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.307955874
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2608945240
Short name T390
Test name
Test status
Simulation time 1897208831 ps
CPU time 132.34 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:49:01 PM PDT 24
Peak memory 656852 kb
Host smart-4e496d55-bd05-443f-ab37-c3c9210c504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608945240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2608945240
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1888037713
Short name T1283
Test name
Test status
Simulation time 1514757528 ps
CPU time 97.71 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:48:28 PM PDT 24
Peak memory 539508 kb
Host smart-24df3df1-5cc1-46fd-a229-f17ef1470893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888037713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1888037713
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.763752384
Short name T1131
Test name
Test status
Simulation time 1087563779 ps
CPU time 0.91 seconds
Started May 14 12:46:48 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 204076 kb
Host smart-5a462857-f0eb-49be-8824-7fcec25ab854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763752384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.763752384
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.4255920740
Short name T1072
Test name
Test status
Simulation time 128349704 ps
CPU time 6.53 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 204404 kb
Host smart-3d0f468d-e8a3-42eb-a91f-431cc6c41976
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255920740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.4255920740
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3976503096
Short name T536
Test name
Test status
Simulation time 4271323729 ps
CPU time 101.08 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 1173448 kb
Host smart-a17a88f7-b137-4035-b5a7-a329ef3ad0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976503096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3976503096
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2421934978
Short name T453
Test name
Test status
Simulation time 505096366 ps
CPU time 8.06 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:16 PM PDT 24
Peak memory 204516 kb
Host smart-66262080-5137-4181-8707-52506c191869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421934978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2421934978
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1049725573
Short name T662
Test name
Test status
Simulation time 1095665214 ps
CPU time 18.43 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:26 PM PDT 24
Peak memory 349676 kb
Host smart-a70ac201-3b0f-4ace-8e11-04fa111a6b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049725573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1049725573
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1227746198
Short name T325
Test name
Test status
Simulation time 14670040 ps
CPU time 0.63 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:46:52 PM PDT 24
Peak memory 204100 kb
Host smart-88dd6896-86d7-42d0-a956-3bf059ba8182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227746198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1227746198
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.317944782
Short name T1169
Test name
Test status
Simulation time 3041765873 ps
CPU time 122.16 seconds
Started May 14 12:46:51 PM PDT 24
Finished May 14 12:48:54 PM PDT 24
Peak memory 255292 kb
Host smart-0f42681a-0582-41fd-9d28-99733f898e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317944782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.317944782
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2902594960
Short name T1174
Test name
Test status
Simulation time 17886668907 ps
CPU time 25.43 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 261212 kb
Host smart-a0e01134-0cca-4fda-bde2-f9d00d11d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902594960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2902594960
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.45886185
Short name T105
Test name
Test status
Simulation time 63846396220 ps
CPU time 654.76 seconds
Started May 14 12:46:51 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 2330804 kb
Host smart-318c2830-a37f-414a-92be-46a646bd3d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45886185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.45886185
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3717130119
Short name T585
Test name
Test status
Simulation time 469776454 ps
CPU time 21.77 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:47:11 PM PDT 24
Peak memory 212616 kb
Host smart-134151bd-eb97-411d-9f8e-4183c0a57065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717130119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3717130119
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1116637788
Short name T707
Test name
Test status
Simulation time 3380998892 ps
CPU time 4.16 seconds
Started May 14 12:46:50 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 212684 kb
Host smart-47969d05-2a0c-42aa-9130-6715aa9f4551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116637788 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1116637788
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2987442356
Short name T984
Test name
Test status
Simulation time 10462900148 ps
CPU time 13.86 seconds
Started May 14 12:46:45 PM PDT 24
Finished May 14 12:47:01 PM PDT 24
Peak memory 250968 kb
Host smart-8949e29b-0f07-4a55-a48e-87df75825fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987442356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2987442356
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1699873523
Short name T49
Test name
Test status
Simulation time 10147385116 ps
CPU time 9.49 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 262348 kb
Host smart-5656d2f6-5a7a-4a9c-8fe1-6d845348ac19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699873523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1699873523
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1781774859
Short name T980
Test name
Test status
Simulation time 2568982677 ps
CPU time 1.85 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:46:50 PM PDT 24
Peak memory 204504 kb
Host smart-7f88ab8a-9e12-4a39-8489-de30450dcbad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781774859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1781774859
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3370315219
Short name T816
Test name
Test status
Simulation time 4069581605 ps
CPU time 6.38 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:46:58 PM PDT 24
Peak memory 220752 kb
Host smart-d137a423-4b41-4ea3-b1f3-b35554c75703
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370315219 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3370315219
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2570244412
Short name T895
Test name
Test status
Simulation time 21379945475 ps
CPU time 52.03 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 1209784 kb
Host smart-fecb14db-f706-4286-80df-b1ea38343c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570244412 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2570244412
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2315062556
Short name T1224
Test name
Test status
Simulation time 2003601344 ps
CPU time 17.32 seconds
Started May 14 12:46:46 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 204660 kb
Host smart-d76fdce9-d567-4038-bf2b-314dd11fdbeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315062556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2315062556
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3323787651
Short name T129
Test name
Test status
Simulation time 1207051608 ps
CPU time 50.33 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 205232 kb
Host smart-1ebd58ae-2976-4241-b4c2-df2db5a9ca4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323787651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3323787651
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3528942707
Short name T19
Test name
Test status
Simulation time 50090823349 ps
CPU time 1204.01 seconds
Started May 14 12:46:50 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 7577112 kb
Host smart-c484fa6b-282e-4100-a38d-c010771a261a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528942707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3528942707
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3570398433
Short name T1069
Test name
Test status
Simulation time 27513840411 ps
CPU time 166.13 seconds
Started May 14 12:46:49 PM PDT 24
Finished May 14 12:49:37 PM PDT 24
Peak memory 676564 kb
Host smart-4269e7f9-cd53-4c48-b623-c27683b32467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570398433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3570398433
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4226964932
Short name T999
Test name
Test status
Simulation time 1064955689 ps
CPU time 7.09 seconds
Started May 14 12:46:47 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 219608 kb
Host smart-d5d8ba56-f6e3-4db3-baab-8b3e9f8e9207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226964932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4226964932
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.34054275
Short name T1252
Test name
Test status
Simulation time 97908593 ps
CPU time 0.58 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 204004 kb
Host smart-80fcf81c-8671-4d6d-9220-0d533c6d2b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34054275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.34054275
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1614422662
Short name T492
Test name
Test status
Simulation time 99742466 ps
CPU time 1.48 seconds
Started May 14 12:47:02 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 212720 kb
Host smart-a62d3bb4-546f-4d52-9951-99ec03d03308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614422662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1614422662
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1312278701
Short name T623
Test name
Test status
Simulation time 624038132 ps
CPU time 4.01 seconds
Started May 14 12:47:04 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 234412 kb
Host smart-bb2c0301-4457-468b-8f00-d40b30f0fdc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312278701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1312278701
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2592836106
Short name T545
Test name
Test status
Simulation time 9036862172 ps
CPU time 65.7 seconds
Started May 14 12:46:54 PM PDT 24
Finished May 14 12:48:01 PM PDT 24
Peak memory 669700 kb
Host smart-824bcc27-08db-4d23-93c9-bb7db9de15ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592836106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2592836106
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1296606378
Short name T549
Test name
Test status
Simulation time 10813739159 ps
CPU time 38.99 seconds
Started May 14 12:46:58 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 555668 kb
Host smart-f0ed3844-1175-41a9-8826-e6c9416b6859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296606378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1296606378
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3289807533
Short name T51
Test name
Test status
Simulation time 134282291 ps
CPU time 1.03 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 204452 kb
Host smart-d7456173-53e7-4a46-ba4b-2a73e6449b28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289807533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3289807533
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3875600741
Short name T213
Test name
Test status
Simulation time 172524266 ps
CPU time 4.98 seconds
Started May 14 12:46:54 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 216240 kb
Host smart-76653f2c-b45b-4fb0-bff5-50fefda717a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875600741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3875600741
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3129235913
Short name T1086
Test name
Test status
Simulation time 5142991431 ps
CPU time 69.79 seconds
Started May 14 12:47:04 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 750448 kb
Host smart-10146feb-dc2e-4752-9d2e-892d1bc1da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129235913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3129235913
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2688681183
Short name T674
Test name
Test status
Simulation time 815788180 ps
CPU time 6.58 seconds
Started May 14 12:46:58 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 204368 kb
Host smart-9581136b-29a4-4536-aa12-2393e3072974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688681183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2688681183
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3144233282
Short name T1328
Test name
Test status
Simulation time 5269150883 ps
CPU time 66.79 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 12:48:05 PM PDT 24
Peak memory 342616 kb
Host smart-89c231c5-e1b6-488e-90aa-6853e82180a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144233282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3144233282
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3079860253
Short name T284
Test name
Test status
Simulation time 75118374 ps
CPU time 0.7 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 12:46:59 PM PDT 24
Peak memory 204044 kb
Host smart-941306e1-0b99-4868-a440-61f1ad8f1912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079860253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3079860253
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1999566934
Short name T83
Test name
Test status
Simulation time 2505127710 ps
CPU time 158.05 seconds
Started May 14 12:47:04 PM PDT 24
Finished May 14 12:49:44 PM PDT 24
Peak memory 766220 kb
Host smart-80d3552a-e3c9-4973-af87-f584da6d9de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999566934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1999566934
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2314741920
Short name T460
Test name
Test status
Simulation time 12217835681 ps
CPU time 28.28 seconds
Started May 14 12:46:53 PM PDT 24
Finished May 14 12:47:22 PM PDT 24
Peak memory 358648 kb
Host smart-82d60de7-f4b5-4cc3-833c-e19aa8f7597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314741920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2314741920
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3602530187
Short name T246
Test name
Test status
Simulation time 5588087260 ps
CPU time 214.71 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 1289596 kb
Host smart-321981fa-fbb8-4a1a-8092-396433e47c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602530187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3602530187
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2816639
Short name T648
Test name
Test status
Simulation time 580956329 ps
CPU time 26.39 seconds
Started May 14 12:46:58 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 212680 kb
Host smart-cb43455e-0391-4edb-904d-45c82eb76e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2816639
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.673164415
Short name T788
Test name
Test status
Simulation time 3838255383 ps
CPU time 3.12 seconds
Started May 14 12:46:53 PM PDT 24
Finished May 14 12:46:57 PM PDT 24
Peak memory 204432 kb
Host smart-0def2812-cfc0-4dac-8ac3-e3477f19834a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673164415 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.673164415
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.504343771
Short name T960
Test name
Test status
Simulation time 10042383545 ps
CPU time 29.58 seconds
Started May 14 12:46:52 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 336656 kb
Host smart-b2ee0189-3f26-4759-9b45-e56d45e410ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504343771 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.504343771
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2520592420
Short name T963
Test name
Test status
Simulation time 10294902416 ps
CPU time 37.88 seconds
Started May 14 12:46:55 PM PDT 24
Finished May 14 12:47:34 PM PDT 24
Peak memory 426428 kb
Host smart-a327b41e-4705-4a9d-9915-e13f6b499068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520592420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2520592420
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4100045872
Short name T888
Test name
Test status
Simulation time 1618889309 ps
CPU time 2.66 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:47:00 PM PDT 24
Peak memory 204424 kb
Host smart-39ccffc9-8d1c-4dc3-b219-2658cc0b77f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100045872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4100045872
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.894391416
Short name T255
Test name
Test status
Simulation time 721577126 ps
CPU time 4.09 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 204468 kb
Host smart-bccddf1f-2f52-4bdc-8771-a6cf53d4dc22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894391416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.894391416
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3459338767
Short name T269
Test name
Test status
Simulation time 11632222355 ps
CPU time 7.17 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:47:04 PM PDT 24
Peak memory 332488 kb
Host smart-01ce42f4-a18e-42e8-a149-d4d276f338fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459338767 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3459338767
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3459058253
Short name T1047
Test name
Test status
Simulation time 1261581077 ps
CPU time 10.24 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:12 PM PDT 24
Peak memory 204344 kb
Host smart-2f6cd836-41c5-41d3-a869-f21e24c43898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459058253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3459058253
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.1107836618
Short name T557
Test name
Test status
Simulation time 26675323512 ps
CPU time 30.97 seconds
Started May 14 12:46:52 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 243224 kb
Host smart-76a2abf3-1a69-470d-b3b3-97321a4f58cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107836618 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.1107836618
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1910576113
Short name T1124
Test name
Test status
Simulation time 1143284074 ps
CPU time 24.39 seconds
Started May 14 12:47:09 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 204452 kb
Host smart-a3b5c09e-e96e-4576-b27f-a6a3e7e5d84e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910576113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1910576113
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2724113769
Short name T162
Test name
Test status
Simulation time 13666309016 ps
CPU time 13.36 seconds
Started May 14 12:46:59 PM PDT 24
Finished May 14 12:47:14 PM PDT 24
Peak memory 204484 kb
Host smart-a2adc359-684b-4499-8459-8a11f1f43790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724113769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2724113769
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1952972083
Short name T330
Test name
Test status
Simulation time 31766693690 ps
CPU time 2197.18 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 01:23:40 PM PDT 24
Peak memory 3683504 kb
Host smart-770f5931-4ae1-4582-9aca-d23e37353e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952972083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1952972083
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.858478387
Short name T1058
Test name
Test status
Simulation time 12347281033 ps
CPU time 7.21 seconds
Started May 14 12:46:59 PM PDT 24
Finished May 14 12:47:08 PM PDT 24
Peak memory 212912 kb
Host smart-a5417959-acbf-48ce-8957-dbafbec75e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858478387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.858478387
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.4012530197
Short name T873
Test name
Test status
Simulation time 1237657875 ps
CPU time 6.96 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 218432 kb
Host smart-cddbcb50-5ad1-45fc-91d7-6142ae77b22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012530197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.4012530197
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2295484349
Short name T727
Test name
Test status
Simulation time 47749273 ps
CPU time 0.65 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:45 PM PDT 24
Peak memory 203988 kb
Host smart-9f0d9b09-76e6-4afc-bf32-0bf03c7a3cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295484349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2295484349
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2070032229
Short name T904
Test name
Test status
Simulation time 106366647 ps
CPU time 1.71 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 212692 kb
Host smart-aa9ab07b-9892-4d88-8960-41537572ea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070032229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2070032229
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.658142230
Short name T559
Test name
Test status
Simulation time 493532525 ps
CPU time 12.75 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:58 PM PDT 24
Peak memory 252552 kb
Host smart-bcee377c-0d4d-4cf0-b614-a1a2db77e588
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658142230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.658142230
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.620035728
Short name T332
Test name
Test status
Simulation time 4733464768 ps
CPU time 87.5 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:46:52 PM PDT 24
Peak memory 781552 kb
Host smart-9001cc61-be7a-48e4-bc0a-fddf54ffdc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620035728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.620035728
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1931088285
Short name T558
Test name
Test status
Simulation time 6419204970 ps
CPU time 111.7 seconds
Started May 14 12:45:24 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 576832 kb
Host smart-e7674ce2-418e-415a-90a0-47335ac38567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931088285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1931088285
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1589213883
Short name T763
Test name
Test status
Simulation time 302464177 ps
CPU time 1.06 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 204320 kb
Host smart-90e3009e-f9db-456c-8d4e-783ce6eb7ee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589213883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1589213883
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2274009437
Short name T359
Test name
Test status
Simulation time 186707870 ps
CPU time 9.96 seconds
Started May 14 12:45:40 PM PDT 24
Finished May 14 12:45:53 PM PDT 24
Peak memory 237648 kb
Host smart-72689729-634e-445a-a8b6-dafd7915d86b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274009437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2274009437
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2401279990
Short name T697
Test name
Test status
Simulation time 7453336842 ps
CPU time 109.73 seconds
Started May 14 12:45:23 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 1069744 kb
Host smart-41e165e8-148c-4f63-a398-d91225e258ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401279990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2401279990
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1428337689
Short name T1335
Test name
Test status
Simulation time 736115750 ps
CPU time 11.53 seconds
Started May 14 12:45:40 PM PDT 24
Finished May 14 12:45:54 PM PDT 24
Peak memory 204432 kb
Host smart-22baac23-8a57-453d-ab3a-29bef3123019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428337689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1428337689
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.503371388
Short name T790
Test name
Test status
Simulation time 2274339234 ps
CPU time 22.33 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:46:04 PM PDT 24
Peak memory 310152 kb
Host smart-7ced46ca-0e72-4893-b840-c1a7a3060f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503371388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.503371388
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2242058884
Short name T603
Test name
Test status
Simulation time 49485281 ps
CPU time 0.69 seconds
Started May 14 12:45:24 PM PDT 24
Finished May 14 12:45:27 PM PDT 24
Peak memory 203976 kb
Host smart-80373548-1f23-4224-87d8-9da3c0f94012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242058884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2242058884
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2993278263
Short name T77
Test name
Test status
Simulation time 5103404774 ps
CPU time 9.03 seconds
Started May 14 12:45:21 PM PDT 24
Finished May 14 12:45:32 PM PDT 24
Peak memory 221128 kb
Host smart-98558094-6939-44cd-ac46-c4f0ba6665de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993278263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2993278263
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2048879170
Short name T1107
Test name
Test status
Simulation time 3206849816 ps
CPU time 34.14 seconds
Started May 14 12:45:45 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 261452 kb
Host smart-9db2cb0c-6260-48d4-a5c1-1ff298e5739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048879170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2048879170
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3156757229
Short name T374
Test name
Test status
Simulation time 22358071865 ps
CPU time 1816.39 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 2485008 kb
Host smart-400776ee-35fd-44cc-86b1-36a941fa0771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156757229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3156757229
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.547802274
Short name T459
Test name
Test status
Simulation time 948736193 ps
CPU time 15.84 seconds
Started May 14 12:45:24 PM PDT 24
Finished May 14 12:45:42 PM PDT 24
Peak memory 228704 kb
Host smart-4c643b66-dcd0-4e6e-8216-fe55f99501e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547802274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.547802274
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2854701167
Short name T172
Test name
Test status
Simulation time 109647896 ps
CPU time 0.94 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:42 PM PDT 24
Peak memory 222352 kb
Host smart-3c783598-2363-4d9b-bf2d-49808e2fd400
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854701167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2854701167
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3502574276
Short name T817
Test name
Test status
Simulation time 14185629125 ps
CPU time 4.5 seconds
Started May 14 12:45:28 PM PDT 24
Finished May 14 12:45:34 PM PDT 24
Peak memory 212616 kb
Host smart-60e0014c-3864-4e5d-95d6-485a6b7ae7af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502574276 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3502574276
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3521114193
Short name T1024
Test name
Test status
Simulation time 10035128731 ps
CPU time 75.51 seconds
Started May 14 12:45:33 PM PDT 24
Finished May 14 12:46:51 PM PDT 24
Peak memory 441540 kb
Host smart-b6df1623-e077-473f-9e98-84f177a858ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521114193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3521114193
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2222107811
Short name T996
Test name
Test status
Simulation time 10284978639 ps
CPU time 5.36 seconds
Started May 14 12:45:31 PM PDT 24
Finished May 14 12:45:38 PM PDT 24
Peak memory 235752 kb
Host smart-edacccb2-f415-407b-8292-c6b64275e87d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222107811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2222107811
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3373197928
Short name T25
Test name
Test status
Simulation time 1670405462 ps
CPU time 2.56 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 204392 kb
Host smart-9710772b-00f9-437b-bef5-240ecd8f5d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373197928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3373197928
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3157641121
Short name T1017
Test name
Test status
Simulation time 4880764677 ps
CPU time 6.51 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:45 PM PDT 24
Peak memory 212708 kb
Host smart-f3fd168f-c650-4ecc-99a3-3a4314881e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157641121 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3157641121
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.1403279021
Short name T507
Test name
Test status
Simulation time 2925610738 ps
CPU time 12.64 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:57 PM PDT 24
Peak memory 614908 kb
Host smart-d53b928d-eafa-4a10-aed6-acb272ecf388
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403279021 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.1403279021
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3873854706
Short name T1080
Test name
Test status
Simulation time 7121235765 ps
CPU time 47.7 seconds
Started May 14 12:45:24 PM PDT 24
Finished May 14 12:46:13 PM PDT 24
Peak memory 204328 kb
Host smart-f8577e37-1411-4ca5-b2a4-729fafd0552a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873854706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3873854706
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.4084427958
Short name T109
Test name
Test status
Simulation time 916822927 ps
CPU time 16.37 seconds
Started May 14 12:45:31 PM PDT 24
Finished May 14 12:45:49 PM PDT 24
Peak memory 212504 kb
Host smart-33040811-cfa1-43db-ad5a-297304eb6de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084427958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.4084427958
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.436781096
Short name T1004
Test name
Test status
Simulation time 46478844925 ps
CPU time 119.49 seconds
Started May 14 12:45:32 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 1725412 kb
Host smart-7e85e29f-c6cb-42f9-b129-d047f115673b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436781096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.436781096
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3087669726
Short name T322
Test name
Test status
Simulation time 45800245462 ps
CPU time 273.81 seconds
Started May 14 12:45:25 PM PDT 24
Finished May 14 12:50:00 PM PDT 24
Peak memory 956292 kb
Host smart-ba755811-5348-4091-95a3-f6138eee1a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087669726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3087669726
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1299054448
Short name T1236
Test name
Test status
Simulation time 4371505495 ps
CPU time 6.82 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 210612 kb
Host smart-bffda00e-f92b-427c-9590-b6890010a91c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299054448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1299054448
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2678988220
Short name T1155
Test name
Test status
Simulation time 41480347 ps
CPU time 0.6 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 204152 kb
Host smart-a5242680-cd0d-4c77-8b22-9eb806c48303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678988220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2678988220
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3557532898
Short name T543
Test name
Test status
Simulation time 144696230 ps
CPU time 1.77 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:46:59 PM PDT 24
Peak memory 212812 kb
Host smart-6ed270d3-b9cc-4aab-a07a-643b3341d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557532898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3557532898
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.628167093
Short name T1249
Test name
Test status
Simulation time 179060976 ps
CPU time 4.02 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:09 PM PDT 24
Peak memory 235676 kb
Host smart-6437daa1-dabc-47f5-9f21-b161679bed66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628167093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.628167093
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3572752789
Short name T17
Test name
Test status
Simulation time 8755352534 ps
CPU time 71.77 seconds
Started May 14 12:46:54 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 749132 kb
Host smart-698a1820-723b-4972-9302-53692e9b2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572752789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3572752789
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.861825870
Short name T716
Test name
Test status
Simulation time 7153191447 ps
CPU time 132.12 seconds
Started May 14 12:47:02 PM PDT 24
Finished May 14 12:49:16 PM PDT 24
Peak memory 620984 kb
Host smart-87fe1dc2-0e28-472f-9d48-501b1a814657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861825870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.861825870
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.4044105951
Short name T469
Test name
Test status
Simulation time 125636370 ps
CPU time 1.01 seconds
Started May 14 12:46:54 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 204176 kb
Host smart-5534a167-b302-4939-ac35-8820a2428e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044105951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.4044105951
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.4094960898
Short name T1344
Test name
Test status
Simulation time 1232949844 ps
CPU time 10.82 seconds
Started May 14 12:46:55 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 239352 kb
Host smart-9e7865ff-6bc1-465d-9387-117b7698ef54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094960898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.4094960898
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.4066835561
Short name T384
Test name
Test status
Simulation time 31737626062 ps
CPU time 314.78 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 1230844 kb
Host smart-078655d8-08ce-46fd-94f7-043ec37b6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066835561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.4066835561
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2851339385
Short name T1357
Test name
Test status
Simulation time 1110461696 ps
CPU time 4.91 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 204436 kb
Host smart-259f1fb3-cfef-45f0-8901-41e618f59cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851339385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2851339385
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.310277443
Short name T1291
Test name
Test status
Simulation time 2047898134 ps
CPU time 33.06 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:47:36 PM PDT 24
Peak memory 332600 kb
Host smart-b03b0218-24c5-4b60-af6c-54211550a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310277443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.310277443
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2381607280
Short name T852
Test name
Test status
Simulation time 34091814 ps
CPU time 0.65 seconds
Started May 14 12:46:53 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 204036 kb
Host smart-7998f087-7b03-4f04-bff2-a150826c9161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381607280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2381607280
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.589353109
Short name T719
Test name
Test status
Simulation time 772586293 ps
CPU time 4.71 seconds
Started May 14 12:46:59 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 241392 kb
Host smart-e8ab9431-4044-4f89-bdd6-410291f212ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589353109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.589353109
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1488264701
Short name T1178
Test name
Test status
Simulation time 4992911284 ps
CPU time 21.15 seconds
Started May 14 12:46:54 PM PDT 24
Finished May 14 12:47:16 PM PDT 24
Peak memory 310296 kb
Host smart-667f9a2e-5611-42de-a6d3-990ee4348e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488264701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1488264701
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.524169513
Short name T250
Test name
Test status
Simulation time 56024185348 ps
CPU time 1099.65 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 01:05:21 PM PDT 24
Peak memory 1946884 kb
Host smart-607455e9-24fd-4bb3-bc08-6df07a7fe45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524169513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.524169513
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3853744922
Short name T159
Test name
Test status
Simulation time 388046316 ps
CPU time 6.49 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:07 PM PDT 24
Peak memory 213844 kb
Host smart-bf0ce595-a6bb-42c6-af52-2b7928abbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853744922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3853744922
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3548262285
Short name T955
Test name
Test status
Simulation time 2732971745 ps
CPU time 3.97 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:47:07 PM PDT 24
Peak memory 206024 kb
Host smart-9415874d-6949-4a0d-a2d9-c244ea1f7208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548262285 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3548262285
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1108849866
Short name T1095
Test name
Test status
Simulation time 10073339195 ps
CPU time 62.08 seconds
Started May 14 12:47:02 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 456760 kb
Host smart-3448e06c-9c33-4e24-b841-14e506eb00d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108849866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1108849866
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3374100867
Short name T562
Test name
Test status
Simulation time 10383921655 ps
CPU time 13.11 seconds
Started May 14 12:47:02 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 304432 kb
Host smart-13b6910f-7ab0-4e02-a34c-afdfe19317d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374100867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3374100867
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.76892778
Short name T258
Test name
Test status
Simulation time 458177440 ps
CPU time 2.23 seconds
Started May 14 12:47:04 PM PDT 24
Finished May 14 12:47:09 PM PDT 24
Peak memory 204456 kb
Host smart-7bd8533e-6f31-4879-993f-024dc22cff5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76892778 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.i2c_target_hrst.76892778
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2173800782
Short name T1079
Test name
Test status
Simulation time 5229922674 ps
CPU time 6.83 seconds
Started May 14 12:47:04 PM PDT 24
Finished May 14 12:47:13 PM PDT 24
Peak memory 219740 kb
Host smart-88a9620c-c98e-4021-8381-346910db019a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173800782 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2173800782
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.1765505606
Short name T69
Test name
Test status
Simulation time 7204145264 ps
CPU time 5.18 seconds
Started May 14 12:46:55 PM PDT 24
Finished May 14 12:47:01 PM PDT 24
Peak memory 204388 kb
Host smart-5069c3e8-d733-44df-8b0c-01c95ea92501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765505606 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1765505606
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1452208971
Short name T1296
Test name
Test status
Simulation time 830851444 ps
CPU time 12.89 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 204344 kb
Host smart-5d93557a-8781-407d-83d1-af1c49f02d75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452208971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1452208971
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.81672113
Short name T270
Test name
Test status
Simulation time 2300683692 ps
CPU time 10.24 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 206792 kb
Host smart-88b260d2-e6d6-40ed-9ef3-7a85d11b4df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81672113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stress_rd.81672113
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.579947419
Short name T1254
Test name
Test status
Simulation time 42355338566 ps
CPU time 271.2 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:51:28 PM PDT 24
Peak memory 2937468 kb
Host smart-cbd7cc6d-c98e-43ac-ac84-16eaa42fec2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579947419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.579947419
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3911261223
Short name T260
Test name
Test status
Simulation time 33057842348 ps
CPU time 3034.28 seconds
Started May 14 12:46:57 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 8014048 kb
Host smart-26e3f69d-f91e-4a2a-8946-39227ce215ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911261223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3911261223
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2898122269
Short name T1286
Test name
Test status
Simulation time 1939641150 ps
CPU time 6.44 seconds
Started May 14 12:46:56 PM PDT 24
Finished May 14 12:47:04 PM PDT 24
Peak memory 214892 kb
Host smart-09af327d-fffa-4145-ad19-705a7c3351c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898122269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2898122269
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2016448418
Short name T165
Test name
Test status
Simulation time 20518077 ps
CPU time 0.62 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:47:07 PM PDT 24
Peak memory 204204 kb
Host smart-951e7bc3-ce1e-4519-8643-68b2e896e625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016448418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2016448418
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3145595419
Short name T1044
Test name
Test status
Simulation time 90872411 ps
CPU time 1.48 seconds
Started May 14 12:47:08 PM PDT 24
Finished May 14 12:47:11 PM PDT 24
Peak memory 212776 kb
Host smart-532364f5-f9c5-4d8e-875f-4dbeffe7db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145595419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3145595419
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2362312578
Short name T541
Test name
Test status
Simulation time 173811717 ps
CPU time 3.83 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:09 PM PDT 24
Peak memory 234120 kb
Host smart-68f47760-131b-4635-89d6-3b6b3367e4da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362312578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2362312578
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2253591544
Short name T442
Test name
Test status
Simulation time 2227849321 ps
CPU time 77.79 seconds
Started May 14 12:46:59 PM PDT 24
Finished May 14 12:48:17 PM PDT 24
Peak memory 734100 kb
Host smart-6df1deb6-952a-481b-afa2-a7b9bfb5a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253591544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2253591544
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.641825065
Short name T672
Test name
Test status
Simulation time 7526473807 ps
CPU time 66.12 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 674944 kb
Host smart-e63a0c6d-8920-4bfa-9b7e-81c2c3406e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641825065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.641825065
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3503540563
Short name T401
Test name
Test status
Simulation time 459257315 ps
CPU time 0.85 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:47:08 PM PDT 24
Peak memory 204196 kb
Host smart-150fefdd-0ace-430b-832c-e366b346b9fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503540563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3503540563
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2452862172
Short name T1293
Test name
Test status
Simulation time 134365675 ps
CPU time 7.54 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:09 PM PDT 24
Peak memory 224516 kb
Host smart-8b7de769-342a-418f-be1a-4ef59c0c06ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452862172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2452862172
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2522584137
Short name T647
Test name
Test status
Simulation time 18611375068 ps
CPU time 99.39 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:48:47 PM PDT 24
Peak memory 1157376 kb
Host smart-01ec7161-0fd0-4118-8fac-fc84597171fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522584137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2522584137
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.195457239
Short name T1233
Test name
Test status
Simulation time 1012535582 ps
CPU time 10.6 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:12 PM PDT 24
Peak memory 204428 kb
Host smart-4ba1058c-b593-42bc-a8ae-f6ba004c183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195457239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.195457239
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.863272615
Short name T1051
Test name
Test status
Simulation time 25522652187 ps
CPU time 26.23 seconds
Started May 14 12:47:07 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 342032 kb
Host smart-442b3bb9-560d-4e34-a367-dd304085f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863272615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.863272615
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.554625096
Short name T1186
Test name
Test status
Simulation time 20915939 ps
CPU time 0.64 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 204068 kb
Host smart-8bd18e43-0fcf-4348-936c-e171f80da681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554625096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.554625096
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.128567571
Short name T920
Test name
Test status
Simulation time 6686518293 ps
CPU time 47.22 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 229928 kb
Host smart-ca587b23-a929-46fb-97d9-9a39b7fd8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128567571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.128567571
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.599591557
Short name T353
Test name
Test status
Simulation time 18215485346 ps
CPU time 43.56 seconds
Started May 14 12:47:08 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 497500 kb
Host smart-bc0f119a-51dd-451f-bcdb-c10e9d1bd699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599591557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.599591557
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.33932789
Short name T1119
Test name
Test status
Simulation time 13827346838 ps
CPU time 644.03 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:57:50 PM PDT 24
Peak memory 1411072 kb
Host smart-6c0a42b6-2d55-4259-80f2-376ba5900b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33932789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.33932789
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.817903774
Short name T1212
Test name
Test status
Simulation time 786871012 ps
CPU time 14.75 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:16 PM PDT 24
Peak memory 215716 kb
Host smart-dcd9974a-8138-4f09-9a10-c721e2bf898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817903774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.817903774
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3108684542
Short name T1040
Test name
Test status
Simulation time 1197662992 ps
CPU time 3.06 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 204512 kb
Host smart-116ef515-816f-4366-a7cc-db048b2ece1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108684542 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3108684542
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.3922250566
Short name T858
Test name
Test status
Simulation time 10239544657 ps
CPU time 29.78 seconds
Started May 14 12:47:00 PM PDT 24
Finished May 14 12:47:31 PM PDT 24
Peak memory 320740 kb
Host smart-b04663de-b0c3-4cfa-aa84-aafb080b733a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922250566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.3922250566
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.187025847
Short name T1170
Test name
Test status
Simulation time 10032569980 ps
CPU time 68.1 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:48:15 PM PDT 24
Peak memory 429116 kb
Host smart-9eead9d6-7bb1-4707-95fe-294df9d659b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187025847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.187025847
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1727807566
Short name T765
Test name
Test status
Simulation time 1519954944 ps
CPU time 2.32 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:47:08 PM PDT 24
Peak memory 204388 kb
Host smart-7e72e5d2-aeb8-46ec-89c7-271b3b8266dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727807566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1727807566
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2559638037
Short name T638
Test name
Test status
Simulation time 543853141 ps
CPU time 3.4 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:11 PM PDT 24
Peak memory 204360 kb
Host smart-7df5f6d0-7af5-4dc5-8155-a8ce186433b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559638037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2559638037
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1546399025
Short name T592
Test name
Test status
Simulation time 15214712934 ps
CPU time 103.62 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:48:47 PM PDT 24
Peak memory 1880348 kb
Host smart-9710f273-2cc2-42f9-befe-d8a9e39c916f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546399025 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1546399025
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.766252654
Short name T899
Test name
Test status
Simulation time 10447286317 ps
CPU time 13.21 seconds
Started May 14 12:47:02 PM PDT 24
Finished May 14 12:47:17 PM PDT 24
Peak memory 204364 kb
Host smart-fc5c5d90-e85e-4c59-84a0-d328208fcf5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766252654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.766252654
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2999691906
Short name T1187
Test name
Test status
Simulation time 3381679083 ps
CPU time 23.32 seconds
Started May 14 12:47:05 PM PDT 24
Finished May 14 12:47:30 PM PDT 24
Peak memory 204464 kb
Host smart-3222e921-b34a-474c-aa70-16b88ad635e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999691906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2999691906
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4259028098
Short name T815
Test name
Test status
Simulation time 52890875875 ps
CPU time 314.52 seconds
Started May 14 12:47:09 PM PDT 24
Finished May 14 12:52:25 PM PDT 24
Peak memory 3294304 kb
Host smart-20b4ffcd-17cd-4dc6-9288-8cc93683b8b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259028098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4259028098
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.4126785608
Short name T747
Test name
Test status
Simulation time 15752869514 ps
CPU time 73.78 seconds
Started May 14 12:47:03 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 951924 kb
Host smart-a89504b0-00fd-44e6-bfc6-84907fad8063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126785608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.4126785608
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.4049400633
Short name T482
Test name
Test status
Simulation time 3294954540 ps
CPU time 7.17 seconds
Started May 14 12:47:06 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 212584 kb
Host smart-40e34237-04a6-48fe-8012-0246b0c499d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049400633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.4049400633
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1544408618
Short name T339
Test name
Test status
Simulation time 16260848 ps
CPU time 0.63 seconds
Started May 14 12:47:12 PM PDT 24
Finished May 14 12:47:14 PM PDT 24
Peak memory 204132 kb
Host smart-4829b77e-3a4d-4b1f-97c8-88f4eba7aaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544408618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1544408618
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.254206834
Short name T687
Test name
Test status
Simulation time 52760994 ps
CPU time 1.13 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:20 PM PDT 24
Peak memory 212724 kb
Host smart-80604696-9465-4a0e-9ad3-1ab028da17b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254206834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.254206834
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.23444450
Short name T429
Test name
Test status
Simulation time 4656336844 ps
CPU time 6.78 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 264164 kb
Host smart-b8386d6b-e2f2-482d-9a55-434601365673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty
.23444450
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2709323797
Short name T773
Test name
Test status
Simulation time 1645832528 ps
CPU time 46.68 seconds
Started May 14 12:47:11 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 554952 kb
Host smart-3142ca7e-382f-4081-bc82-341f2a0fb697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709323797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2709323797
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1580404584
Short name T758
Test name
Test status
Simulation time 6526438246 ps
CPU time 126.19 seconds
Started May 14 12:47:11 PM PDT 24
Finished May 14 12:49:19 PM PDT 24
Peak memory 627828 kb
Host smart-e944ce37-af35-4f4c-8440-109306af1f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580404584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1580404584
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3084546245
Short name T793
Test name
Test status
Simulation time 342746058 ps
CPU time 0.93 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:47:13 PM PDT 24
Peak memory 204176 kb
Host smart-2e226518-d7c2-4968-a960-2d3e1b0072ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084546245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3084546245
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.640003994
Short name T749
Test name
Test status
Simulation time 610250657 ps
CPU time 3.82 seconds
Started May 14 12:47:09 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 229388 kb
Host smart-25ceb955-38ec-4da5-be5c-ac3ed872d765
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640003994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
640003994
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.382754112
Short name T480
Test name
Test status
Simulation time 4279512314 ps
CPU time 126.27 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 1184412 kb
Host smart-8cc47967-6815-4c6a-a400-65b685eb5c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382754112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.382754112
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2124066967
Short name T1337
Test name
Test status
Simulation time 1123015191 ps
CPU time 14.35 seconds
Started May 14 12:47:09 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 204436 kb
Host smart-b727b86f-506e-4a9c-bfe5-005f0f419f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124066967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2124066967
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3827484360
Short name T891
Test name
Test status
Simulation time 1553245504 ps
CPU time 71.02 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:48:23 PM PDT 24
Peak memory 276300 kb
Host smart-ec267194-31f4-4e95-97d1-f356cf969505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827484360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3827484360
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.797786132
Short name T45
Test name
Test status
Simulation time 20354951 ps
CPU time 0.65 seconds
Started May 14 12:47:01 PM PDT 24
Finished May 14 12:47:03 PM PDT 24
Peak memory 204068 kb
Host smart-4b7c1d7d-b5f7-40e8-a889-c55421b04d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797786132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.797786132
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3090331270
Short name T84
Test name
Test status
Simulation time 4548188938 ps
CPU time 42.09 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:47:54 PM PDT 24
Peak memory 222824 kb
Host smart-06e02f84-ba89-4842-9531-e2298f706bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090331270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3090331270
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.703615538
Short name T1059
Test name
Test status
Simulation time 3124751897 ps
CPU time 60.67 seconds
Started May 14 12:47:07 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 292392 kb
Host smart-7742a1e7-bc70-4467-bfb3-0f7567e3d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703615538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.703615538
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1024070055
Short name T98
Test name
Test status
Simulation time 16579706489 ps
CPU time 931.57 seconds
Started May 14 12:47:11 PM PDT 24
Finished May 14 01:02:44 PM PDT 24
Peak memory 2410900 kb
Host smart-fb823beb-ea91-4ec6-8f8e-82862563f921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024070055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1024070055
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1762392336
Short name T368
Test name
Test status
Simulation time 2143216749 ps
CPU time 25.14 seconds
Started May 14 12:47:08 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 212524 kb
Host smart-bba58296-81fd-4573-9f38-0ddbc8bf1895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762392336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1762392336
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3102701346
Short name T708
Test name
Test status
Simulation time 1132146262 ps
CPU time 5.76 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:47:17 PM PDT 24
Peak memory 212652 kb
Host smart-95c2a64b-a301-4855-8db7-8234093e2a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102701346 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3102701346
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3346639984
Short name T60
Test name
Test status
Simulation time 10060665943 ps
CPU time 75.53 seconds
Started May 14 12:47:15 PM PDT 24
Finished May 14 12:48:32 PM PDT 24
Peak memory 513296 kb
Host smart-4df06e96-5a72-41ad-8351-15479e1d7f9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346639984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3346639984
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1232616537
Short name T990
Test name
Test status
Simulation time 10084820004 ps
CPU time 68.22 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:48:20 PM PDT 24
Peak memory 433836 kb
Host smart-dab98728-0408-4fcb-9052-62ce3f8900eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232616537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1232616537
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3062568909
Short name T1074
Test name
Test status
Simulation time 1324430033 ps
CPU time 2.39 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:47:17 PM PDT 24
Peak memory 204384 kb
Host smart-6f5cbecb-7e8d-4e1c-b6dc-46baa12e7d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062568909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3062568909
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3093133913
Short name T742
Test name
Test status
Simulation time 3808064246 ps
CPU time 4.88 seconds
Started May 14 12:47:12 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 204392 kb
Host smart-b37de188-8b96-44ec-b589-6c333199c144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093133913 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3093133913
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.4172238005
Short name T1232
Test name
Test status
Simulation time 19166742995 ps
CPU time 53.52 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 883156 kb
Host smart-1a23c379-e07f-4349-9d74-0c3224c01b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172238005 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.4172238005
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.749196694
Short name T534
Test name
Test status
Simulation time 1479845229 ps
CPU time 30 seconds
Started May 14 12:47:12 PM PDT 24
Finished May 14 12:47:44 PM PDT 24
Peak memory 204332 kb
Host smart-51e812a6-7d19-4de5-b950-9e49328f38da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749196694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.749196694
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3784865277
Short name T991
Test name
Test status
Simulation time 33447223247 ps
CPU time 40.23 seconds
Started May 14 12:47:09 PM PDT 24
Finished May 14 12:47:51 PM PDT 24
Peak memory 786928 kb
Host smart-ede1b5ce-b4eb-4158-b4b8-4a551c9716c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784865277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3784865277
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3607687744
Short name T1022
Test name
Test status
Simulation time 24628383214 ps
CPU time 186.03 seconds
Started May 14 12:47:08 PM PDT 24
Finished May 14 12:50:15 PM PDT 24
Peak memory 1356112 kb
Host smart-ff0cc27e-249e-4502-a8a4-0327d2281253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607687744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3607687744
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1570281929
Short name T461
Test name
Test status
Simulation time 4593303316 ps
CPU time 6.99 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:47:19 PM PDT 24
Peak memory 218148 kb
Host smart-a39008f9-b04d-4c36-95f9-109c6ebe8dbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570281929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1570281929
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1902920954
Short name T340
Test name
Test status
Simulation time 32108662 ps
CPU time 0.59 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 203840 kb
Host smart-2ed2d636-2bd4-4fee-be6b-7ee79acf28ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902920954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1902920954
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2892501464
Short name T1331
Test name
Test status
Simulation time 116715230 ps
CPU time 1.56 seconds
Started May 14 12:47:16 PM PDT 24
Finished May 14 12:47:19 PM PDT 24
Peak memory 212688 kb
Host smart-11ff68c9-4283-455a-be29-a92d2b8dc73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892501464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2892501464
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1759904790
Short name T1245
Test name
Test status
Simulation time 794251265 ps
CPU time 8.98 seconds
Started May 14 12:47:25 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 291420 kb
Host smart-39fee98f-00d4-4567-a103-3a713ea30569
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759904790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1759904790
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2946194901
Short name T526
Test name
Test status
Simulation time 19660151979 ps
CPU time 156.61 seconds
Started May 14 12:47:18 PM PDT 24
Finished May 14 12:49:55 PM PDT 24
Peak memory 612244 kb
Host smart-096c1cbf-749a-44f0-98b5-342cdc8e6b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946194901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2946194901
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1876519990
Short name T831
Test name
Test status
Simulation time 13253020122 ps
CPU time 38.54 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 544368 kb
Host smart-be2e647c-e7d2-4463-b4f7-d9b5631ac426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876519990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1876519990
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3838639802
Short name T1030
Test name
Test status
Simulation time 1154838927 ps
CPU time 1.09 seconds
Started May 14 12:47:15 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 204364 kb
Host smart-e638fef8-ee77-40ba-89d9-837f73f25ef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838639802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3838639802
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.992694984
Short name T940
Test name
Test status
Simulation time 1446118539 ps
CPU time 3.36 seconds
Started May 14 12:47:23 PM PDT 24
Finished May 14 12:47:28 PM PDT 24
Peak memory 204392 kb
Host smart-661f3896-aa6a-44aa-8ebe-7f58a3ed9412
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992694984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
992694984
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2544290045
Short name T130
Test name
Test status
Simulation time 9460955584 ps
CPU time 61.84 seconds
Started May 14 12:47:15 PM PDT 24
Finished May 14 12:48:18 PM PDT 24
Peak memory 770296 kb
Host smart-05abcea7-6a6d-4714-9751-d70e7949d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544290045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2544290045
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1723698923
Short name T890
Test name
Test status
Simulation time 1838497120 ps
CPU time 18.65 seconds
Started May 14 12:47:18 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 204444 kb
Host smart-d49d485e-450a-48db-abee-9302d8cf9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723698923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1723698923
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2111855004
Short name T472
Test name
Test status
Simulation time 1464341926 ps
CPU time 71.29 seconds
Started May 14 12:47:20 PM PDT 24
Finished May 14 12:48:33 PM PDT 24
Peak memory 334224 kb
Host smart-18450f07-3ab0-4cd8-9f87-7ad709643ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111855004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2111855004
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.706554673
Short name T974
Test name
Test status
Simulation time 186792839 ps
CPU time 0.62 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:47:15 PM PDT 24
Peak memory 204048 kb
Host smart-9de15aa7-588c-4a75-9ca4-66175be71a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706554673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.706554673
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2358536504
Short name T37
Test name
Test status
Simulation time 28612679507 ps
CPU time 504.11 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:55:40 PM PDT 24
Peak memory 473336 kb
Host smart-c6b059a6-606c-44b2-a6f3-e2c562d5b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358536504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2358536504
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3904136311
Short name T1104
Test name
Test status
Simulation time 1779811767 ps
CPU time 26.8 seconds
Started May 14 12:47:10 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 299976 kb
Host smart-f9af4e49-96c1-4c4a-b4a9-f19a553b99de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904136311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3904136311
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2853507135
Short name T125
Test name
Test status
Simulation time 196383590754 ps
CPU time 355.87 seconds
Started May 14 12:47:11 PM PDT 24
Finished May 14 12:53:09 PM PDT 24
Peak memory 2202716 kb
Host smart-38cf6982-5dc7-4130-8f84-2417c79ab116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853507135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2853507135
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1803381881
Short name T433
Test name
Test status
Simulation time 557901034 ps
CPU time 26.43 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 212484 kb
Host smart-90aff34f-1514-4858-b5f0-0bc118790707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803381881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1803381881
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1316959448
Short name T1026
Test name
Test status
Simulation time 1751468492 ps
CPU time 3.39 seconds
Started May 14 12:47:20 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 204264 kb
Host smart-32512149-5a8d-498f-8af5-6d3da9f55cb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316959448 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1316959448
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3654903921
Short name T804
Test name
Test status
Simulation time 10050455873 ps
CPU time 30.78 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 355408 kb
Host smart-510a484c-3354-441f-a450-8bcc7d55efd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654903921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3654903921
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1137234979
Short name T1235
Test name
Test status
Simulation time 10284505244 ps
CPU time 17.4 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 317092 kb
Host smart-8048014e-7a1c-4272-a5d2-26537a049460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137234979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1137234979
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3839818934
Short name T3
Test name
Test status
Simulation time 1648450344 ps
CPU time 2.65 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 204376 kb
Host smart-57d3bfe5-bc19-48d2-8f93-e8f1a2cc3ac7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839818934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3839818934
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3360812461
Short name T847
Test name
Test status
Simulation time 1781434030 ps
CPU time 4.53 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:27 PM PDT 24
Peak memory 204404 kb
Host smart-ba3d46f2-85ec-40ca-a118-3a59d1386a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360812461 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3360812461
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3384301361
Short name T704
Test name
Test status
Simulation time 17724964278 ps
CPU time 44.88 seconds
Started May 14 12:47:15 PM PDT 24
Finished May 14 12:48:02 PM PDT 24
Peak memory 1063980 kb
Host smart-d76de7c2-8cf2-4ecd-9912-1556350972c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384301361 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3384301361
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2636870628
Short name T6
Test name
Test status
Simulation time 5222461036 ps
CPU time 22.89 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:39 PM PDT 24
Peak memory 204372 kb
Host smart-434904ad-3078-4196-a44a-ad3a6ce0305d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636870628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2636870628
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.4290742913
Short name T1005
Test name
Test status
Simulation time 1624152028 ps
CPU time 69.54 seconds
Started May 14 12:47:16 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 207028 kb
Host smart-f2ed6125-67c6-4ff0-a012-91c8c46f2360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290742913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.4290742913
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2252557462
Short name T1042
Test name
Test status
Simulation time 30619357778 ps
CPU time 547.53 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 3533476 kb
Host smart-928d188d-9ad4-4aa8-bc44-a2b4208cb1db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252557462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2252557462
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.364508321
Short name T1144
Test name
Test status
Simulation time 1030197560 ps
CPU time 6.17 seconds
Started May 14 12:47:12 PM PDT 24
Finished May 14 12:47:20 PM PDT 24
Peak memory 212644 kb
Host smart-0230c54f-d400-4db0-a61c-bea64504b89a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364508321 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.364508321
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.2221123486
Short name T798
Test name
Test status
Simulation time 4699024815 ps
CPU time 6.95 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 212620 kb
Host smart-c3467a4e-c28f-49e6-9757-dfb7c959df39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221123486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.2221123486
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2254469325
Short name T1350
Test name
Test status
Simulation time 39726574 ps
CPU time 0.63 seconds
Started May 14 12:47:31 PM PDT 24
Finished May 14 12:47:32 PM PDT 24
Peak memory 204172 kb
Host smart-82ee6f61-7d84-4718-b0e9-1fb247efb927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254469325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2254469325
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1319122779
Short name T1152
Test name
Test status
Simulation time 59397725 ps
CPU time 1.26 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:17 PM PDT 24
Peak memory 212504 kb
Host smart-892db878-2789-4061-a21d-5db62d3aef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319122779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1319122779
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2857054372
Short name T512
Test name
Test status
Simulation time 1791463161 ps
CPU time 7.31 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 227908 kb
Host smart-5bc76dbb-43b9-45f4-9a98-d17403441eb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857054372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2857054372
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1924862652
Short name T1082
Test name
Test status
Simulation time 2622152278 ps
CPU time 37.94 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 496124 kb
Host smart-32eeeea7-7080-4f1f-b5fa-91456e82e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924862652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1924862652
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3744179333
Short name T497
Test name
Test status
Simulation time 16254204533 ps
CPU time 30.37 seconds
Started May 14 12:47:20 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 488592 kb
Host smart-6ca56c0d-35c2-460d-8e03-b291f1a5586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744179333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3744179333
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2577403074
Short name T1087
Test name
Test status
Simulation time 536157056 ps
CPU time 0.96 seconds
Started May 14 12:47:20 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 204048 kb
Host smart-0f840476-30b0-42f4-8803-9af45152a67d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577403074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2577403074
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3015485473
Short name T837
Test name
Test status
Simulation time 135170370 ps
CPU time 2.78 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 204348 kb
Host smart-65c51cd4-29f9-464a-bd51-a0357c759105
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015485473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3015485473
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2258170622
Short name T1207
Test name
Test status
Simulation time 13487326312 ps
CPU time 101.35 seconds
Started May 14 12:47:16 PM PDT 24
Finished May 14 12:48:58 PM PDT 24
Peak memory 1013264 kb
Host smart-01cd1b9b-6b1c-4dce-8810-52f9db30eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258170622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2258170622
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1437815207
Short name T221
Test name
Test status
Simulation time 1410988315 ps
CPU time 5.57 seconds
Started May 14 12:47:24 PM PDT 24
Finished May 14 12:47:31 PM PDT 24
Peak memory 204280 kb
Host smart-f6c2372a-aeba-4ec6-abcc-9a353b035377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437815207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1437815207
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2594741290
Short name T717
Test name
Test status
Simulation time 15007618991 ps
CPU time 43.22 seconds
Started May 14 12:47:15 PM PDT 24
Finished May 14 12:48:00 PM PDT 24
Peak memory 293720 kb
Host smart-b8984d61-233b-4f9b-84f2-561e07629dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594741290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2594741290
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2669076564
Short name T939
Test name
Test status
Simulation time 28337345 ps
CPU time 0.61 seconds
Started May 14 12:47:20 PM PDT 24
Finished May 14 12:47:22 PM PDT 24
Peak memory 203968 kb
Host smart-294164f2-8891-449f-a704-f3dbd2715c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669076564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2669076564
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1888502261
Short name T1002
Test name
Test status
Simulation time 54315399431 ps
CPU time 52.34 seconds
Started May 14 12:47:18 PM PDT 24
Finished May 14 12:48:11 PM PDT 24
Peak memory 204376 kb
Host smart-53df9a50-c27d-44a9-9b36-9d4987621e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888502261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1888502261
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2420728702
Short name T295
Test name
Test status
Simulation time 1615864696 ps
CPU time 30.09 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:48 PM PDT 24
Peak memory 297996 kb
Host smart-74033771-edee-407a-961f-160b3a1fb42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420728702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2420728702
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.639244013
Short name T235
Test name
Test status
Simulation time 23273439780 ps
CPU time 1618.08 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 2356416 kb
Host smart-9c28509b-457c-489b-8b2e-e6a3e08377f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639244013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.639244013
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1477863290
Short name T244
Test name
Test status
Simulation time 7049748237 ps
CPU time 36.17 seconds
Started May 14 12:47:13 PM PDT 24
Finished May 14 12:47:51 PM PDT 24
Peak memory 220844 kb
Host smart-279ce02d-8b61-4362-968d-59a7bbf0eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477863290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1477863290
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3117686828
Short name T1285
Test name
Test status
Simulation time 2173849826 ps
CPU time 5.15 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:28 PM PDT 24
Peak memory 212712 kb
Host smart-85ca97ee-cc4d-4d9c-baaa-8b2a7e3d8ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117686828 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3117686828
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3100959240
Short name T544
Test name
Test status
Simulation time 11816787397 ps
CPU time 4.05 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:24 PM PDT 24
Peak memory 220888 kb
Host smart-d243295b-6852-4687-a83c-c85f9c686d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100959240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3100959240
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2855028287
Short name T1135
Test name
Test status
Simulation time 10144613595 ps
CPU time 14.98 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 278680 kb
Host smart-9e95defe-1baa-4128-aa05-8cd841dd2316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855028287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2855028287
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.247004462
Short name T733
Test name
Test status
Simulation time 1721719321 ps
CPU time 2.8 seconds
Started May 14 12:47:17 PM PDT 24
Finished May 14 12:47:21 PM PDT 24
Peak memory 204372 kb
Host smart-88183748-e758-481d-a824-d4ea9140954d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247004462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.247004462
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.684610493
Short name T319
Test name
Test status
Simulation time 1181129240 ps
CPU time 6.41 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:27 PM PDT 24
Peak memory 216352 kb
Host smart-9275a2ba-ce76-42a4-b1df-89e288610db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684610493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.684610493
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2888082450
Short name T4
Test name
Test status
Simulation time 16214328542 ps
CPU time 307.29 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:52:30 PM PDT 24
Peak memory 3772668 kb
Host smart-8f858646-49ff-45b2-a18a-6e3ce40de52d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888082450 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2888082450
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3514422671
Short name T128
Test name
Test status
Simulation time 1255563404 ps
CPU time 21.62 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:42 PM PDT 24
Peak memory 204312 kb
Host smart-8799f915-2494-40aa-aad0-e0c981ec29c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514422671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3514422671
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4071370754
Short name T425
Test name
Test status
Simulation time 1632860566 ps
CPU time 26.66 seconds
Started May 14 12:47:19 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 229480 kb
Host smart-3d137dc3-bc8f-4868-836c-dfe337f1d25c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071370754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4071370754
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3751280163
Short name T1129
Test name
Test status
Simulation time 32112784840 ps
CPU time 94.7 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 1507824 kb
Host smart-c62827aa-291b-4bfe-9846-671184c98001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751280163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3751280163
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2145558523
Short name T1116
Test name
Test status
Simulation time 5178547929 ps
CPU time 35.41 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 669108 kb
Host smart-693da6f0-7aaa-45ce-8be0-ad3a9a591712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145558523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2145558523
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2066118718
Short name T1352
Test name
Test status
Simulation time 2913531338 ps
CPU time 7.17 seconds
Started May 14 12:47:14 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 204404 kb
Host smart-eaf5087e-9054-4cec-8b1f-b2dd0b6e08b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066118718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2066118718
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1569318551
Short name T441
Test name
Test status
Simulation time 43302933 ps
CPU time 0.62 seconds
Started May 14 12:47:24 PM PDT 24
Finished May 14 12:47:26 PM PDT 24
Peak memory 204248 kb
Host smart-ede9a3b3-605a-4e18-9ebf-d4091f325f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569318551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1569318551
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2173832650
Short name T934
Test name
Test status
Simulation time 196825470 ps
CPU time 1.58 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:24 PM PDT 24
Peak memory 220880 kb
Host smart-79961c8b-f500-4c41-86bc-f7a8dda560c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173832650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2173832650
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2960979554
Short name T1327
Test name
Test status
Simulation time 318848520 ps
CPU time 7.12 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:47:31 PM PDT 24
Peak memory 268316 kb
Host smart-d746a9c6-8981-4724-9c16-24dbe0bef7a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960979554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2960979554
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2799240423
Short name T994
Test name
Test status
Simulation time 40739128426 ps
CPU time 67.43 seconds
Started May 14 12:47:31 PM PDT 24
Finished May 14 12:48:39 PM PDT 24
Peak memory 711860 kb
Host smart-9836341c-9878-4576-b044-78c0cd5c36ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799240423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2799240423
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3231442178
Short name T783
Test name
Test status
Simulation time 13127113400 ps
CPU time 100.66 seconds
Started May 14 12:47:26 PM PDT 24
Finished May 14 12:49:07 PM PDT 24
Peak memory 501992 kb
Host smart-b4fdbf1c-08a3-4278-a894-d55091f82947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231442178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3231442178
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3475153219
Short name T979
Test name
Test status
Simulation time 261992364 ps
CPU time 0.86 seconds
Started May 14 12:47:25 PM PDT 24
Finished May 14 12:47:27 PM PDT 24
Peak memory 204152 kb
Host smart-ab177473-a5b7-4a86-baf7-32d99bfde1a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475153219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3475153219
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.852761573
Short name T927
Test name
Test status
Simulation time 706430000 ps
CPU time 5.12 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:47:29 PM PDT 24
Peak memory 237336 kb
Host smart-ce138114-866d-4147-853a-5d0a58ce9325
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852761573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
852761573
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2895597060
Short name T99
Test name
Test status
Simulation time 4240639357 ps
CPU time 82.25 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:48:45 PM PDT 24
Peak memory 1071196 kb
Host smart-86cae25f-e685-428f-9e3a-3c987295f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895597060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2895597060
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1512880760
Short name T1098
Test name
Test status
Simulation time 7229025607 ps
CPU time 8.47 seconds
Started May 14 12:47:26 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 204460 kb
Host smart-298363f7-1288-4316-8327-cb9a7491c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512880760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1512880760
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3406266526
Short name T446
Test name
Test status
Simulation time 5265470014 ps
CPU time 65.54 seconds
Started May 14 12:47:24 PM PDT 24
Finished May 14 12:48:31 PM PDT 24
Peak memory 326084 kb
Host smart-22cf07b4-5537-45c2-a09f-15f563bd1cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406266526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3406266526
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2024709094
Short name T579
Test name
Test status
Simulation time 20492377 ps
CPU time 0.62 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:24 PM PDT 24
Peak memory 204052 kb
Host smart-523a77c5-e04a-4228-9e07-c15542e50a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024709094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2024709094
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1326808710
Short name T155
Test name
Test status
Simulation time 13666299966 ps
CPU time 72.62 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:48:36 PM PDT 24
Peak memory 204432 kb
Host smart-eedbe1ef-934e-459e-af58-ce028f689f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326808710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1326808710
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3937744054
Short name T965
Test name
Test status
Simulation time 3743588990 ps
CPU time 17.22 seconds
Started May 14 12:47:24 PM PDT 24
Finished May 14 12:47:43 PM PDT 24
Peak memory 266032 kb
Host smart-f9a2b7c0-20a2-4b21-ba5d-155ed5168862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937744054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3937744054
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1625624128
Short name T126
Test name
Test status
Simulation time 18314689031 ps
CPU time 171.04 seconds
Started May 14 12:47:24 PM PDT 24
Finished May 14 12:50:16 PM PDT 24
Peak memory 1365432 kb
Host smart-b8fdbda2-eea8-4533-9639-c4e2b22a216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625624128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1625624128
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.795988266
Short name T1316
Test name
Test status
Simulation time 3025863468 ps
CPU time 12.58 seconds
Started May 14 12:47:35 PM PDT 24
Finished May 14 12:47:48 PM PDT 24
Peak memory 220716 kb
Host smart-c3a28073-0916-4ec8-aac5-bb6831440d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795988266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.795988266
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1234784427
Short name T986
Test name
Test status
Simulation time 2486029935 ps
CPU time 3.12 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:27 PM PDT 24
Peak memory 204500 kb
Host smart-651d4760-1a8b-4eed-bcb4-ab18a2409b39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234784427 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1234784427
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4148776192
Short name T416
Test name
Test status
Simulation time 10267268956 ps
CPU time 8.93 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 236560 kb
Host smart-12a76a71-0af1-4a36-8b0c-aede1ca01d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148776192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4148776192
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3205380895
Short name T392
Test name
Test status
Simulation time 10063461521 ps
CPU time 71.3 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:48:35 PM PDT 24
Peak memory 433684 kb
Host smart-2acc01a2-a032-45ae-88aa-2972be7dcd7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205380895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3205380895
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2718299949
Short name T1366
Test name
Test status
Simulation time 1187579742 ps
CPU time 2.27 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 204268 kb
Host smart-623bb67e-90d5-496a-bea9-8cc63f93049c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718299949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2718299949
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2665951597
Short name T267
Test name
Test status
Simulation time 882430287 ps
CPU time 4.93 seconds
Started May 14 12:47:32 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 206156 kb
Host smart-eea95ffa-3d08-49bf-8d7c-1bb647182de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665951597 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2665951597
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3996922363
Short name T923
Test name
Test status
Simulation time 10292948195 ps
CPU time 5.93 seconds
Started May 14 12:47:40 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 309996 kb
Host smart-15b43dcb-4037-40f4-9b7a-3a48aa424249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996922363 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3996922363
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2624938436
Short name T567
Test name
Test status
Simulation time 2705544880 ps
CPU time 17.7 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:47:42 PM PDT 24
Peak memory 204424 kb
Host smart-ed27e15f-c4a0-4704-8224-b8764525b302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624938436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2624938436
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.995153547
Short name T1360
Test name
Test status
Simulation time 3528380867 ps
CPU time 13.36 seconds
Started May 14 12:47:26 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 217980 kb
Host smart-6c3a15df-1099-4d2c-942b-1b57cbbda2c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995153547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.995153547
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1986973413
Short name T1055
Test name
Test status
Simulation time 51028974375 ps
CPU time 1315.36 seconds
Started May 14 12:47:27 PM PDT 24
Finished May 14 01:09:23 PM PDT 24
Peak memory 7899932 kb
Host smart-7a7218c2-1e1f-45a0-bc5a-de0b5272b4f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986973413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1986973413
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3713990427
Short name T928
Test name
Test status
Simulation time 40770913457 ps
CPU time 263.33 seconds
Started May 14 12:47:35 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 1864996 kb
Host smart-b9fcbb3f-32bc-4370-9857-6a1675e74133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713990427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3713990427
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2694024697
Short name T519
Test name
Test status
Simulation time 1397718439 ps
CPU time 7.13 seconds
Started May 14 12:47:27 PM PDT 24
Finished May 14 12:47:36 PM PDT 24
Peak memory 220628 kb
Host smart-d1a27ec4-daa9-4883-93d5-4c3bf71830dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694024697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2694024697
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.904671910
Short name T1198
Test name
Test status
Simulation time 2786696387 ps
CPU time 6.51 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:30 PM PDT 24
Peak memory 204388 kb
Host smart-28a2e403-4736-4d1e-a24a-96355bbc7dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904671910 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_unexp_stop.904671910
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2102260812
Short name T929
Test name
Test status
Simulation time 20943767 ps
CPU time 0.63 seconds
Started May 14 12:47:45 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 204148 kb
Host smart-7fb1d939-fb54-41c0-9026-7974a1eed572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102260812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2102260812
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3622889296
Short name T846
Test name
Test status
Simulation time 138375417 ps
CPU time 1.49 seconds
Started May 14 12:47:32 PM PDT 24
Finished May 14 12:47:34 PM PDT 24
Peak memory 212696 kb
Host smart-5404b7ca-de29-4491-9f0c-d7ca1fa58826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622889296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3622889296
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.444682903
Short name T396
Test name
Test status
Simulation time 474105946 ps
CPU time 5.72 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:29 PM PDT 24
Peak memory 252208 kb
Host smart-3bf9e438-0419-47e6-87fb-943479971b82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444682903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.444682903
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2582723205
Short name T1263
Test name
Test status
Simulation time 3915313543 ps
CPU time 139.84 seconds
Started May 14 12:47:32 PM PDT 24
Finished May 14 12:49:53 PM PDT 24
Peak memory 670440 kb
Host smart-0aaeea40-3cba-4d5b-bbca-7c003c05387d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582723205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2582723205
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2172108004
Short name T1363
Test name
Test status
Simulation time 6006304410 ps
CPU time 32.14 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 288276 kb
Host smart-367f0faa-ee30-437d-9447-04d83d423773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172108004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2172108004
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.72809294
Short name T317
Test name
Test status
Simulation time 223394809 ps
CPU time 0.86 seconds
Started May 14 12:47:22 PM PDT 24
Finished May 14 12:47:25 PM PDT 24
Peak memory 204128 kb
Host smart-a2f38ea2-fcfc-4a94-b6f6-7481623e430d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72809294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt
.72809294
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2342203791
Short name T403
Test name
Test status
Simulation time 338364694 ps
CPU time 4.46 seconds
Started May 14 12:47:25 PM PDT 24
Finished May 14 12:47:31 PM PDT 24
Peak memory 234920 kb
Host smart-6df3789a-0606-4055-b1c7-fdcac7f8fe7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342203791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2342203791
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3509712746
Short name T740
Test name
Test status
Simulation time 8294124964 ps
CPU time 130.78 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 688844 kb
Host smart-f8eb1b5c-e09f-4408-8fdd-1d344e06c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509712746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3509712746
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.2278408167
Short name T792
Test name
Test status
Simulation time 311459057 ps
CPU time 4.62 seconds
Started May 14 12:47:29 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 204656 kb
Host smart-040345c2-11fb-4eba-aefb-9776ddc5cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278408167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2278408167
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3945622010
Short name T1062
Test name
Test status
Simulation time 1696930015 ps
CPU time 35.63 seconds
Started May 14 12:47:35 PM PDT 24
Finished May 14 12:48:12 PM PDT 24
Peak memory 366000 kb
Host smart-4b4b15e4-b5bb-434f-9174-f0070ff8897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945622010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3945622010
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.185052481
Short name T1314
Test name
Test status
Simulation time 25314541 ps
CPU time 0.63 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 203928 kb
Host smart-9e193076-805c-41bf-9625-29e7d1f8cf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185052481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.185052481
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.814618593
Short name T210
Test name
Test status
Simulation time 26432859905 ps
CPU time 1531.52 seconds
Started May 14 12:47:42 PM PDT 24
Finished May 14 01:13:15 PM PDT 24
Peak memory 3610320 kb
Host smart-acee514b-1fb7-449c-a43d-c4e7cb1bc4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814618593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.814618593
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3294514741
Short name T702
Test name
Test status
Simulation time 6142146538 ps
CPU time 75.4 seconds
Started May 14 12:47:21 PM PDT 24
Finished May 14 12:48:38 PM PDT 24
Peak memory 383728 kb
Host smart-0e9f8796-3549-4685-a31a-a86324ecbf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294514741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3294514741
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2642300256
Short name T1189
Test name
Test status
Simulation time 8932917041 ps
CPU time 654.78 seconds
Started May 14 12:47:41 PM PDT 24
Finished May 14 12:58:37 PM PDT 24
Peak memory 815208 kb
Host smart-e9bbcd38-b50c-477e-844d-9ebac6cd463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642300256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2642300256
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.599436137
Short name T239
Test name
Test status
Simulation time 2556817960 ps
CPU time 12.34 seconds
Started May 14 12:47:43 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 219916 kb
Host smart-4cef4a24-9ab6-4ee7-b109-99b6b3faea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599436137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.599436137
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.842975369
Short name T30
Test name
Test status
Simulation time 3765989469 ps
CPU time 5.03 seconds
Started May 14 12:47:29 PM PDT 24
Finished May 14 12:47:35 PM PDT 24
Peak memory 212664 kb
Host smart-c83501c1-eb01-40a4-9e17-a20385b4d30d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842975369 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.842975369
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.4232655396
Short name T1365
Test name
Test status
Simulation time 10534211707 ps
CPU time 9.4 seconds
Started May 14 12:47:44 PM PDT 24
Finished May 14 12:47:54 PM PDT 24
Peak memory 235220 kb
Host smart-17bd1a31-72ce-4b86-9979-fdbe452a1fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232655396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.4232655396
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3802518980
Short name T973
Test name
Test status
Simulation time 10078441078 ps
CPU time 79.47 seconds
Started May 14 12:47:26 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 459112 kb
Host smart-996a9ab1-11ae-4ec3-96bd-34b5f2fb90f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802518980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3802518980
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2917481738
Short name T22
Test name
Test status
Simulation time 1473613564 ps
CPU time 2.67 seconds
Started May 14 12:47:29 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 204368 kb
Host smart-b37a06f7-dd7a-4726-87a8-bc19e5f0ee1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917481738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2917481738
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.551797634
Short name T850
Test name
Test status
Simulation time 875447325 ps
CPU time 5.06 seconds
Started May 14 12:47:36 PM PDT 24
Finished May 14 12:47:42 PM PDT 24
Peak memory 204436 kb
Host smart-bd2477fd-fbf8-4e07-bea2-3788b9c8489f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551797634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.551797634
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.577026162
Short name T540
Test name
Test status
Simulation time 13740757906 ps
CPU time 111.07 seconds
Started May 14 12:47:26 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 1763120 kb
Host smart-e3b11f77-afdd-4f43-ad33-be5779b63c49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577026162 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.577026162
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1334454636
Short name T345
Test name
Test status
Simulation time 651260083 ps
CPU time 26.48 seconds
Started May 14 12:47:48 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 204396 kb
Host smart-a7da260f-d700-45f1-9b69-45e17c77926d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334454636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1334454636
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3309081105
Short name T293
Test name
Test status
Simulation time 1023399954 ps
CPU time 10.02 seconds
Started May 14 12:47:30 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 204364 kb
Host smart-38af2a37-9317-4c3f-a59d-f0d9d940aef4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309081105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3309081105
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.97424489
Short name T966
Test name
Test status
Simulation time 45794030954 ps
CPU time 292.96 seconds
Started May 14 12:47:30 PM PDT 24
Finished May 14 12:52:24 PM PDT 24
Peak memory 3212688 kb
Host smart-43ebb035-7be0-4151-a363-849899e52ce0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97424489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stress_wr.97424489
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3023032597
Short name T839
Test name
Test status
Simulation time 30520207953 ps
CPU time 109.36 seconds
Started May 14 12:47:27 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 1150808 kb
Host smart-9dc33c49-2d3d-4626-89f3-54f03f71a3a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023032597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3023032597
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2735703812
Short name T961
Test name
Test status
Simulation time 1611439866 ps
CPU time 7.38 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:47:36 PM PDT 24
Peak memory 220684 kb
Host smart-6bd75ffa-ee60-4742-8604-067c7f256197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735703812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2735703812
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.4160035106
Short name T577
Test name
Test status
Simulation time 18858012 ps
CPU time 0.64 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:42 PM PDT 24
Peak memory 204124 kb
Host smart-7e22a46a-2a43-4d6b-857b-c897387c36c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160035106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4160035106
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2437965927
Short name T907
Test name
Test status
Simulation time 88070875 ps
CPU time 1.91 seconds
Started May 14 12:47:40 PM PDT 24
Finished May 14 12:47:44 PM PDT 24
Peak memory 212788 kb
Host smart-7a4b581a-7956-4c24-a2e2-09f6a70ff160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437965927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2437965927
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3929778445
Short name T1103
Test name
Test status
Simulation time 1097566648 ps
CPU time 14.35 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 259940 kb
Host smart-5638bb22-1636-4a9f-8391-3ba496fffdd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929778445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3929778445
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.11137776
Short name T834
Test name
Test status
Simulation time 1962028830 ps
CPU time 122.57 seconds
Started May 14 12:47:27 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 503872 kb
Host smart-09c60c4c-bc4c-4ee2-9491-3a14372b29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11137776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.11137776
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3535321870
Short name T1348
Test name
Test status
Simulation time 6431594233 ps
CPU time 115.03 seconds
Started May 14 12:47:32 PM PDT 24
Finished May 14 12:49:28 PM PDT 24
Peak memory 590360 kb
Host smart-eb267251-2078-47bb-9575-7473a6db0f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535321870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3535321870
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3777592688
Short name T671
Test name
Test status
Simulation time 579432593 ps
CPU time 1.03 seconds
Started May 14 12:47:29 PM PDT 24
Finished May 14 12:47:31 PM PDT 24
Peak memory 204384 kb
Host smart-6fd47ae4-da3a-4bba-a249-178ff6491942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777592688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3777592688
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1510569370
Short name T1118
Test name
Test status
Simulation time 320963627 ps
CPU time 8.65 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:50 PM PDT 24
Peak memory 204464 kb
Host smart-003bb849-ea88-437c-bc08-3df8dd44462c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510569370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1510569370
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1968835887
Short name T723
Test name
Test status
Simulation time 20126126673 ps
CPU time 122.4 seconds
Started May 14 12:47:30 PM PDT 24
Finished May 14 12:49:33 PM PDT 24
Peak memory 1205712 kb
Host smart-25724983-f0c1-430f-acd1-bf9a77bc09ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968835887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1968835887
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3678961747
Short name T1295
Test name
Test status
Simulation time 1506098600 ps
CPU time 4.75 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:45 PM PDT 24
Peak memory 204352 kb
Host smart-22fa78f8-455e-4ffb-801e-c6fe89af9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678961747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3678961747
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3235409743
Short name T529
Test name
Test status
Simulation time 6460682377 ps
CPU time 26.32 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 309356 kb
Host smart-940bb339-60a0-4043-b0f4-df1741855339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235409743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3235409743
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2268908204
Short name T1241
Test name
Test status
Simulation time 32238178 ps
CPU time 0.65 seconds
Started May 14 12:47:38 PM PDT 24
Finished May 14 12:47:40 PM PDT 24
Peak memory 204104 kb
Host smart-ba9f30e2-1d42-4fce-b46d-90bda3a00575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268908204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2268908204
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.542777000
Short name T72
Test name
Test status
Simulation time 2726901258 ps
CPU time 117.12 seconds
Started May 14 12:47:41 PM PDT 24
Finished May 14 12:49:40 PM PDT 24
Peak memory 229068 kb
Host smart-0861cd81-9772-4991-b9c1-f2ddd7da087c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542777000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.542777000
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2658311749
Short name T857
Test name
Test status
Simulation time 7684602705 ps
CPU time 34.54 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:48:03 PM PDT 24
Peak memory 334008 kb
Host smart-7c91b94b-e6c8-42ba-baa7-8e6444dabf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658311749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2658311749
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2893105735
Short name T104
Test name
Test status
Simulation time 39266816663 ps
CPU time 458.77 seconds
Started May 14 12:47:37 PM PDT 24
Finished May 14 12:55:17 PM PDT 24
Peak memory 1892208 kb
Host smart-2fd5b0b7-2a0f-4c1d-9261-aa07bff561cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893105735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2893105735
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2217688544
Short name T259
Test name
Test status
Simulation time 915573007 ps
CPU time 9.96 seconds
Started May 14 12:47:40 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 220888 kb
Host smart-b2c11393-8974-4325-9c4b-9d79182c8558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217688544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2217688544
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.928294937
Short name T514
Test name
Test status
Simulation time 5609614630 ps
CPU time 6.37 seconds
Started May 14 12:47:41 PM PDT 24
Finished May 14 12:47:49 PM PDT 24
Peak memory 213652 kb
Host smart-c45b1e63-c6c8-4f7a-9241-79c7df49936b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928294937 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.928294937
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3804095331
Short name T682
Test name
Test status
Simulation time 10069927905 ps
CPU time 93.42 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 598040 kb
Host smart-c3181642-fdc4-4e7a-ba7f-3f0265aff017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804095331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3804095331
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3683378737
Short name T1298
Test name
Test status
Simulation time 694470709 ps
CPU time 2.52 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:44 PM PDT 24
Peak memory 204364 kb
Host smart-91cd956a-e33d-411a-ad3b-380b93ac06be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683378737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3683378737
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2039357740
Short name T386
Test name
Test status
Simulation time 3585719738 ps
CPU time 4.81 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:47:34 PM PDT 24
Peak memory 206096 kb
Host smart-2abbf484-3b54-4bc4-96e3-1b97700f6f9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039357740 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2039357740
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.457866455
Short name T283
Test name
Test status
Simulation time 754340558 ps
CPU time 1.53 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:47:30 PM PDT 24
Peak memory 204224 kb
Host smart-5da9d8a8-5053-4531-8976-12565467e94d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457866455 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.457866455
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1394695590
Short name T108
Test name
Test status
Simulation time 3409513681 ps
CPU time 29.89 seconds
Started May 14 12:47:29 PM PDT 24
Finished May 14 12:48:00 PM PDT 24
Peak memory 204380 kb
Host smart-63b192d1-d37a-4317-8bcc-abc1f9ddbd30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394695590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1394695590
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2740663589
Short name T612
Test name
Test status
Simulation time 648240233 ps
CPU time 4.68 seconds
Started May 14 12:47:36 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 204488 kb
Host smart-336d7b9f-a768-4bfa-a16a-853c539b4ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740663589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2740663589
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2549818259
Short name T375
Test name
Test status
Simulation time 55046471230 ps
CPU time 89.09 seconds
Started May 14 12:47:47 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 1286556 kb
Host smart-06a9da43-d970-48d6-89b6-1d94ab741dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549818259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2549818259
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.4113238145
Short name T741
Test name
Test status
Simulation time 29700781520 ps
CPU time 51.17 seconds
Started May 14 12:47:28 PM PDT 24
Finished May 14 12:48:20 PM PDT 24
Peak memory 683840 kb
Host smart-c3ba300d-0562-441a-8f53-3504f6a1b8d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113238145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.4113238145
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.70802064
Short name T290
Test name
Test status
Simulation time 6718922570 ps
CPU time 7.1 seconds
Started May 14 12:47:30 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 220388 kb
Host smart-d651a4ef-adca-4f81-b3ce-96ba116abaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70802064 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_timeout.70802064
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1735654286
Short name T867
Test name
Test status
Simulation time 20417891 ps
CPU time 0.68 seconds
Started May 14 12:47:37 PM PDT 24
Finished May 14 12:47:39 PM PDT 24
Peak memory 204208 kb
Host smart-92d78191-149f-4754-9589-a2b2df1f6bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735654286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1735654286
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3456640890
Short name T474
Test name
Test status
Simulation time 90994339 ps
CPU time 1.27 seconds
Started May 14 12:47:47 PM PDT 24
Finished May 14 12:47:49 PM PDT 24
Peak memory 204568 kb
Host smart-86d0e0c6-2220-4f76-9cc1-29889a6d12dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456640890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3456640890
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1446078743
Short name T1221
Test name
Test status
Simulation time 199926928 ps
CPU time 3.82 seconds
Started May 14 12:47:40 PM PDT 24
Finished May 14 12:47:45 PM PDT 24
Peak memory 242760 kb
Host smart-5504a14d-73d6-45b6-85f3-081dfc03e9ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446078743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1446078743
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.235654251
Short name T1317
Test name
Test status
Simulation time 2322798330 ps
CPU time 29.97 seconds
Started May 14 12:47:43 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 451548 kb
Host smart-4b39eba8-bb0b-4c6b-8448-93dbd3f37976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235654251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.235654251
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.718159209
Short name T564
Test name
Test status
Simulation time 7384922814 ps
CPU time 66.86 seconds
Started May 14 12:47:42 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 738444 kb
Host smart-56b11875-ed0a-427d-8822-6b2f1557d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718159209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.718159209
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2813837694
Short name T1257
Test name
Test status
Simulation time 296220227 ps
CPU time 0.8 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:41 PM PDT 24
Peak memory 204128 kb
Host smart-acf9b781-676d-4950-bfb0-05ba37420988
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813837694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2813837694
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2854661702
Short name T1238
Test name
Test status
Simulation time 364712926 ps
CPU time 7.54 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 226912 kb
Host smart-b837becc-2a68-40a1-8cf2-d6512da7d19b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854661702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2854661702
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3507434931
Short name T535
Test name
Test status
Simulation time 11118957115 ps
CPU time 179.2 seconds
Started May 14 12:47:38 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 869268 kb
Host smart-847262cd-c5af-4d55-bb1d-46c8d112f70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507434931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3507434931
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.256371531
Short name T615
Test name
Test status
Simulation time 2341524345 ps
CPU time 113 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:49:40 PM PDT 24
Peak memory 365940 kb
Host smart-b303a9f9-df88-4980-8a09-c1e17ac13db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256371531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.256371531
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.287539950
Short name T703
Test name
Test status
Simulation time 48649841 ps
CPU time 0.63 seconds
Started May 14 12:47:37 PM PDT 24
Finished May 14 12:47:39 PM PDT 24
Peak memory 204068 kb
Host smart-348370a6-d1db-442c-9e3b-b3c3ad4f939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287539950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.287539950
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.637014796
Short name T909
Test name
Test status
Simulation time 18420740151 ps
CPU time 240.42 seconds
Started May 14 12:47:43 PM PDT 24
Finished May 14 12:51:45 PM PDT 24
Peak memory 204452 kb
Host smart-c1c8ccdf-be65-42e2-8f65-f62614dc5abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637014796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.637014796
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3133679051
Short name T555
Test name
Test status
Simulation time 1528758925 ps
CPU time 29.42 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:48:26 PM PDT 24
Peak memory 311428 kb
Host smart-0a258df7-d4af-4691-bdfb-7e3757485683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133679051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3133679051
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.4017581075
Short name T449
Test name
Test status
Simulation time 57678799502 ps
CPU time 251.19 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:51:59 PM PDT 24
Peak memory 1150728 kb
Host smart-92c204de-3592-4581-b8fd-60196f0861ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017581075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.4017581075
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.100425109
Short name T1092
Test name
Test status
Simulation time 561867351 ps
CPU time 10.85 seconds
Started May 14 12:47:42 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 214924 kb
Host smart-b6c998c2-ec64-470e-aad3-54015e05fc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100425109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.100425109
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3877127163
Short name T473
Test name
Test status
Simulation time 3429381233 ps
CPU time 4.29 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:47:45 PM PDT 24
Peak memory 204544 kb
Host smart-ef94854e-47f8-4f7c-b328-93850ce5097e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877127163 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3877127163
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3064098063
Short name T757
Test name
Test status
Simulation time 10097119453 ps
CPU time 29.89 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 349908 kb
Host smart-3768ffd1-aa79-41b8-8db7-c61970c92748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064098063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3064098063
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.719294899
Short name T1242
Test name
Test status
Simulation time 10282169227 ps
CPU time 9.42 seconds
Started May 14 12:47:38 PM PDT 24
Finished May 14 12:47:48 PM PDT 24
Peak memory 244340 kb
Host smart-f75678d6-1a09-49c7-81c8-acc70e410052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719294899 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.719294899
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1360975862
Short name T350
Test name
Test status
Simulation time 1826689359 ps
CPU time 2.74 seconds
Started May 14 12:47:38 PM PDT 24
Finished May 14 12:47:42 PM PDT 24
Peak memory 204424 kb
Host smart-b20a483b-ee75-465e-934f-f1ef10be25fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360975862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1360975862
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3348277436
Short name T937
Test name
Test status
Simulation time 1390487190 ps
CPU time 6.37 seconds
Started May 14 12:47:42 PM PDT 24
Finished May 14 12:47:50 PM PDT 24
Peak memory 212552 kb
Host smart-51fb8baf-3cfb-48a2-85f6-308ec2d872e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348277436 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3348277436
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1855225702
Short name T737
Test name
Test status
Simulation time 13054357598 ps
CPU time 35.9 seconds
Started May 14 12:47:47 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 793884 kb
Host smart-688f98cf-710e-40b2-b510-41e0a00f8ac2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855225702 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1855225702
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1876905408
Short name T489
Test name
Test status
Simulation time 4295975847 ps
CPU time 42.01 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:38 PM PDT 24
Peak memory 204284 kb
Host smart-db49923e-5b3f-4618-8d2d-3aa67e8040c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876905408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1876905408
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2804168110
Short name T583
Test name
Test status
Simulation time 1506589160 ps
CPU time 12.76 seconds
Started May 14 12:47:37 PM PDT 24
Finished May 14 12:47:50 PM PDT 24
Peak memory 204436 kb
Host smart-f0b8e201-9172-4c01-b5ef-2538abf01b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804168110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2804168110
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1987025719
Short name T693
Test name
Test status
Simulation time 53167167604 ps
CPU time 1164.31 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 7714968 kb
Host smart-6bca302a-a2cc-4eb4-95da-475b06b8187c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987025719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1987025719
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1517677350
Short name T366
Test name
Test status
Simulation time 21524217873 ps
CPU time 114.66 seconds
Started May 14 12:47:39 PM PDT 24
Finished May 14 12:49:36 PM PDT 24
Peak memory 516924 kb
Host smart-505d9f5e-a6c1-49e4-b3e5-b0f6b8a993ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517677350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1517677350
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3407596289
Short name T498
Test name
Test status
Simulation time 1940290917 ps
CPU time 7.7 seconds
Started May 14 12:47:42 PM PDT 24
Finished May 14 12:47:51 PM PDT 24
Peak memory 216920 kb
Host smart-6a8a555b-0e77-4c96-b8d0-1d549d7f5e23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407596289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3407596289
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1673592490
Short name T381
Test name
Test status
Simulation time 15742831 ps
CPU time 0.64 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 204188 kb
Host smart-af7406ef-63b3-4c56-92f0-76324e86c850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673592490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1673592490
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2736784608
Short name T415
Test name
Test status
Simulation time 110627506 ps
CPU time 1.61 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:47:49 PM PDT 24
Peak memory 212744 kb
Host smart-b6ddc0a4-e8f6-4540-a80f-d78b9076e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736784608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2736784608
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3262934169
Short name T759
Test name
Test status
Simulation time 363998461 ps
CPU time 4.06 seconds
Started May 14 12:47:44 PM PDT 24
Finished May 14 12:47:49 PM PDT 24
Peak memory 237068 kb
Host smart-07af1230-0b37-4934-bf66-c76cac556e73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262934169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3262934169
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3582400483
Short name T572
Test name
Test status
Simulation time 4421043430 ps
CPU time 23.78 seconds
Started May 14 12:47:55 PM PDT 24
Finished May 14 12:48:22 PM PDT 24
Peak memory 212728 kb
Host smart-32776bd7-c261-49b8-8808-541412091631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582400483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3582400483
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1584780984
Short name T456
Test name
Test status
Simulation time 1883076003 ps
CPU time 129.98 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:50:08 PM PDT 24
Peak memory 644524 kb
Host smart-e84f4882-e406-4ba7-a533-0cc39817f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584780984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1584780984
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.969790926
Short name T355
Test name
Test status
Simulation time 191073057 ps
CPU time 0.92 seconds
Started May 14 12:47:45 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 204200 kb
Host smart-01835c5b-7ed9-45f6-a852-fd06727e50a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969790926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.969790926
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2377585490
Short name T863
Test name
Test status
Simulation time 287931377 ps
CPU time 9.92 seconds
Started May 14 12:47:44 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 236548 kb
Host smart-63c7b38d-f0d9-4701-aa44-348af0cdf3fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377585490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2377585490
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.223919780
Short name T590
Test name
Test status
Simulation time 26014041891 ps
CPU time 123.28 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:49:55 PM PDT 24
Peak memory 1247728 kb
Host smart-e462147c-7e03-474c-ae55-81f2542e21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223919780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.223919780
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.4231054240
Short name T911
Test name
Test status
Simulation time 413121814 ps
CPU time 17.44 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 204416 kb
Host smart-5ac48332-b834-4760-866f-b7df59a46498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231054240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4231054240
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.232646652
Short name T1140
Test name
Test status
Simulation time 4465078367 ps
CPU time 14.37 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:10 PM PDT 24
Peak memory 243832 kb
Host smart-e4d305a3-9537-48f3-80a1-a89012ae62ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232646652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.232646652
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3239115679
Short name T142
Test name
Test status
Simulation time 93726680 ps
CPU time 0.66 seconds
Started May 14 12:47:45 PM PDT 24
Finished May 14 12:47:47 PM PDT 24
Peak memory 204068 kb
Host smart-99a8d9e0-a8ec-4961-8414-7a87868eccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239115679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3239115679
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3472094359
Short name T380
Test name
Test status
Simulation time 4928426432 ps
CPU time 32.26 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 215444 kb
Host smart-71ff3e52-3714-4474-9342-c2b00e013da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472094359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3472094359
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.611925888
Short name T821
Test name
Test status
Simulation time 1980670313 ps
CPU time 62.09 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 317848 kb
Host smart-9902e44a-65df-4be6-9b5e-ba4ead9c872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611925888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.611925888
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3338704990
Short name T1156
Test name
Test status
Simulation time 43173985001 ps
CPU time 968.45 seconds
Started May 14 12:47:45 PM PDT 24
Finished May 14 01:03:55 PM PDT 24
Peak memory 1902828 kb
Host smart-88c8493d-6c97-4548-831f-e58ee2ad54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338704990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3338704990
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2452603996
Short name T242
Test name
Test status
Simulation time 679456556 ps
CPU time 21.03 seconds
Started May 14 12:47:49 PM PDT 24
Finished May 14 12:48:12 PM PDT 24
Peak memory 212552 kb
Host smart-2a33cf32-d481-4da7-a446-8c37c4971e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452603996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2452603996
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2126293811
Short name T608
Test name
Test status
Simulation time 3425067576 ps
CPU time 4.12 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:02 PM PDT 24
Peak memory 212524 kb
Host smart-73e70f05-a8f1-4f25-af57-80bd9c77fb66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126293811 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2126293811
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3118542983
Short name T1203
Test name
Test status
Simulation time 10307115872 ps
CPU time 15.67 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:48:04 PM PDT 24
Peak memory 289032 kb
Host smart-bec019e6-f400-4d53-b290-27df0355882f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118542983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3118542983
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.501520323
Short name T1177
Test name
Test status
Simulation time 2387844410 ps
CPU time 3.07 seconds
Started May 14 12:47:49 PM PDT 24
Finished May 14 12:47:54 PM PDT 24
Peak memory 204524 kb
Host smart-07aabfc3-d658-4e5d-86c7-a3d29c2f3908
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501520323 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.501520323
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3899550019
Short name T1089
Test name
Test status
Simulation time 1521651033 ps
CPU time 7.88 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:48:05 PM PDT 24
Peak memory 220592 kb
Host smart-3886deb6-dcbf-4d34-a7f3-b061231cf110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899550019 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3899550019
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1420409824
Short name T422
Test name
Test status
Simulation time 3240123474 ps
CPU time 7.04 seconds
Started May 14 12:47:49 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 204492 kb
Host smart-62d84823-4e77-4830-a80c-1a4b9887306c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420409824 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1420409824
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1839840612
Short name T588
Test name
Test status
Simulation time 978976975 ps
CPU time 14.13 seconds
Started May 14 12:47:52 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 204332 kb
Host smart-984a7bb4-363c-4ddc-b7d4-3fd65b7812ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839840612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1839840612
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1232361184
Short name T1099
Test name
Test status
Simulation time 2922719746 ps
CPU time 31.43 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 204424 kb
Host smart-00bb5f6e-8ed5-4dcc-b033-7b9185c2dda4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232361184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1232361184
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.639371380
Short name T962
Test name
Test status
Simulation time 8552103922 ps
CPU time 9.41 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 204504 kb
Host smart-fe3f2b1e-8df4-42fa-9c97-d258a0e84df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639371380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.639371380
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.748516391
Short name T1008
Test name
Test status
Simulation time 27330682637 ps
CPU time 785.18 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 01:01:01 PM PDT 24
Peak memory 2063672 kb
Host smart-c929958c-356e-4390-ac2a-18b8b3417e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748516391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.748516391
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2693803418
Short name T808
Test name
Test status
Simulation time 7008972308 ps
CPU time 7.96 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 216296 kb
Host smart-c8d74542-b1ac-4091-905e-a4b103da5d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693803418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2693803418
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.93818756
Short name T352
Test name
Test status
Simulation time 91136899 ps
CPU time 0.6 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:38 PM PDT 24
Peak memory 204028 kb
Host smart-2a50dea4-87c4-46c5-9a85-7166e880f2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93818756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.93818756
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3999216913
Short name T364
Test name
Test status
Simulation time 231019279 ps
CPU time 1.35 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:43 PM PDT 24
Peak memory 212636 kb
Host smart-663b7e4e-6a63-4aae-8885-ac391e561581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999216913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3999216913
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2412267363
Short name T1176
Test name
Test status
Simulation time 1210295580 ps
CPU time 15.81 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:57 PM PDT 24
Peak memory 267060 kb
Host smart-63ce71d8-f53a-4e31-98df-90aa6f6a00ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412267363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2412267363
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2854543642
Short name T746
Test name
Test status
Simulation time 5868724512 ps
CPU time 48.36 seconds
Started May 14 12:45:33 PM PDT 24
Finished May 14 12:46:25 PM PDT 24
Peak memory 566956 kb
Host smart-77df66ac-ad10-4578-9b47-4141a8cd8f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854543642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2854543642
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.79404110
Short name T1151
Test name
Test status
Simulation time 19266411446 ps
CPU time 57.94 seconds
Started May 14 12:45:29 PM PDT 24
Finished May 14 12:46:28 PM PDT 24
Peak memory 610224 kb
Host smart-4d58ecd3-2634-46bf-ab8d-2431e44a1a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79404110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.79404110
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2762670731
Short name T1248
Test name
Test status
Simulation time 179591708 ps
CPU time 1.1 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 204148 kb
Host smart-2986ec20-3920-4d14-917f-9c763949db1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762670731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2762670731
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3104185893
Short name T394
Test name
Test status
Simulation time 2265757645 ps
CPU time 3.33 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 221616 kb
Host smart-55b4df1b-c514-42ac-8db7-e9ec59d731cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104185893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3104185893
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4108698449
Short name T1166
Test name
Test status
Simulation time 14345949440 ps
CPU time 285.49 seconds
Started May 14 12:45:31 PM PDT 24
Finished May 14 12:50:18 PM PDT 24
Peak memory 1140820 kb
Host smart-539bc2a2-fd90-4a51-b1ee-6c01299395d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108698449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4108698449
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.93392942
Short name T1165
Test name
Test status
Simulation time 507413508 ps
CPU time 5.35 seconds
Started May 14 12:45:40 PM PDT 24
Finished May 14 12:45:48 PM PDT 24
Peak memory 204380 kb
Host smart-07a8f090-013b-4924-8f00-820bdaf64699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93392942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.93392942
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2158607656
Short name T664
Test name
Test status
Simulation time 4782912464 ps
CPU time 23.43 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:46:00 PM PDT 24
Peak memory 283724 kb
Host smart-acd099c0-32df-4ec3-b158-18440fd8f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158607656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2158607656
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3874093837
Short name T866
Test name
Test status
Simulation time 46978444 ps
CPU time 0.64 seconds
Started May 14 12:45:40 PM PDT 24
Finished May 14 12:45:43 PM PDT 24
Peak memory 204060 kb
Host smart-1c83e852-287e-4530-9d4c-dbff13521275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874093837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3874093837
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.663953100
Short name T1153
Test name
Test status
Simulation time 5385421602 ps
CPU time 52.41 seconds
Started May 14 12:45:38 PM PDT 24
Finished May 14 12:46:32 PM PDT 24
Peak memory 229044 kb
Host smart-cb767c97-5e57-4ffa-b235-5e33c3ca56fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663953100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.663953100
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2097357682
Short name T312
Test name
Test status
Simulation time 8679422954 ps
CPU time 24.78 seconds
Started May 14 12:45:44 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 317760 kb
Host smart-502d3e7f-9c06-4b61-b349-5d4a7ef12244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097357682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2097357682
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.1655010209
Short name T1227
Test name
Test status
Simulation time 118234193272 ps
CPU time 549.55 seconds
Started May 14 12:45:57 PM PDT 24
Finished May 14 12:55:08 PM PDT 24
Peak memory 2272512 kb
Host smart-ab2858a6-9f8a-4682-a5e4-556927bb5fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655010209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.1655010209
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2272322254
Short name T650
Test name
Test status
Simulation time 1269034545 ps
CPU time 12.51 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 218680 kb
Host smart-95b1c46b-0b80-4bc4-b07a-854c9cd8ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272322254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2272322254
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.648017311
Short name T173
Test name
Test status
Simulation time 217236639 ps
CPU time 0.88 seconds
Started May 14 12:45:43 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 222392 kb
Host smart-f90338e0-d07d-47cb-9a01-12257c4b8ea8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648017311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.648017311
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3960034776
Short name T735
Test name
Test status
Simulation time 1569687340 ps
CPU time 4.14 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:55 PM PDT 24
Peak memory 212488 kb
Host smart-a8b15038-fc8d-48c6-b980-e0d30843977c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960034776 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3960034776
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.952833640
Short name T1231
Test name
Test status
Simulation time 10287808084 ps
CPU time 9.13 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:45:48 PM PDT 24
Peak memory 239496 kb
Host smart-e01ba37a-8087-4770-be48-b8e9fe2843f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952833640 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.952833640
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.122605009
Short name T1234
Test name
Test status
Simulation time 10379388633 ps
CPU time 29.98 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 375184 kb
Host smart-53954319-d88a-4e71-a2c0-202aa8bf52f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122605009 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.122605009
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3207477801
Short name T997
Test name
Test status
Simulation time 4993329362 ps
CPU time 2.5 seconds
Started May 14 12:45:34 PM PDT 24
Finished May 14 12:45:40 PM PDT 24
Peak memory 204476 kb
Host smart-ddf8ae09-32d3-4735-92ab-3ec768f03479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207477801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3207477801
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.218422098
Short name T402
Test name
Test status
Simulation time 1377032252 ps
CPU time 6.99 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 210568 kb
Host smart-73a5462c-747e-4737-bf80-6f87a798a5b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218422098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.218422098
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3147733018
Short name T833
Test name
Test status
Simulation time 17338581760 ps
CPU time 47.66 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:46:26 PM PDT 24
Peak memory 1010548 kb
Host smart-9032a55a-a084-4902-81c9-bb36ce589286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147733018 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3147733018
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.263722092
Short name T655
Test name
Test status
Simulation time 1374526098 ps
CPU time 19.19 seconds
Started May 14 12:45:38 PM PDT 24
Finished May 14 12:45:59 PM PDT 24
Peak memory 204480 kb
Host smart-d1255367-9eb8-4f57-965e-a1eea82e1775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263722092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.263722092
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2731670252
Short name T315
Test name
Test status
Simulation time 5343989003 ps
CPU time 53.01 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 207040 kb
Host smart-41b7b059-6585-48e3-8d2d-0fb63a2388be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731670252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2731670252
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3653328671
Short name T1020
Test name
Test status
Simulation time 8315644494 ps
CPU time 15.59 seconds
Started May 14 12:45:45 PM PDT 24
Finished May 14 12:46:03 PM PDT 24
Peak memory 204716 kb
Host smart-d3167ffb-5b18-4adb-afd9-770390f8216b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653328671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3653328671
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2213648708
Short name T921
Test name
Test status
Simulation time 5680336871 ps
CPU time 63.05 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:46:41 PM PDT 24
Peak memory 785788 kb
Host smart-d009d690-8283-41c5-9914-2ac4168e331e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213648708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2213648708
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2112036124
Short name T280
Test name
Test status
Simulation time 6164420372 ps
CPU time 7.91 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 219588 kb
Host smart-b4363a98-1ebf-40d9-ab9c-aa3338f9b980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112036124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2112036124
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.257715102
Short name T423
Test name
Test status
Simulation time 17607079 ps
CPU time 0.63 seconds
Started May 14 12:47:55 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 204128 kb
Host smart-9f337212-ea09-4843-9636-6950f144ef7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257715102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.257715102
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.726621109
Short name T1012
Test name
Test status
Simulation time 84275401 ps
CPU time 1.44 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 220876 kb
Host smart-44a04f44-63c4-49d1-b496-20cdbbe5be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726621109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.726621109
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1245504682
Short name T924
Test name
Test status
Simulation time 713221968 ps
CPU time 9.7 seconds
Started May 14 12:47:49 PM PDT 24
Finished May 14 12:48:01 PM PDT 24
Peak memory 240196 kb
Host smart-987a8c00-974f-4bcb-a486-a6a10aa6c15d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245504682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1245504682
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.119608686
Short name T68
Test name
Test status
Simulation time 3935305161 ps
CPU time 59.21 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:48:47 PM PDT 24
Peak memory 676724 kb
Host smart-2ec2bd7f-3f30-4bd4-97c7-3584d07b034a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119608686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.119608686
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3098788777
Short name T451
Test name
Test status
Simulation time 3835721649 ps
CPU time 61.65 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:48:53 PM PDT 24
Peak memory 641952 kb
Host smart-421853e5-c9c3-4416-bf5b-cc2fde1349a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098788777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3098788777
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.466898271
Short name T1299
Test name
Test status
Simulation time 303380619 ps
CPU time 0.77 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:47:52 PM PDT 24
Peak memory 204120 kb
Host smart-cefb7de4-aeac-4fc3-9778-015070130511
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466898271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.466898271
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1886029806
Short name T916
Test name
Test status
Simulation time 381090242 ps
CPU time 3.81 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:47:55 PM PDT 24
Peak memory 204384 kb
Host smart-6eaf0a9c-302a-45dd-b743-918222f890d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886029806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1886029806
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3694586197
Short name T341
Test name
Test status
Simulation time 54627795479 ps
CPU time 315.75 seconds
Started May 14 12:47:48 PM PDT 24
Finished May 14 12:53:05 PM PDT 24
Peak memory 1178720 kb
Host smart-e61f5d9b-94e9-402c-babc-bfbcb28d89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694586197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3694586197
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.612058245
Short name T695
Test name
Test status
Simulation time 249556086 ps
CPU time 3.86 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 204400 kb
Host smart-7305cb99-232e-469c-a38f-89a303ec093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612058245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.612058245
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.2066695571
Short name T1364
Test name
Test status
Simulation time 1114496657 ps
CPU time 23.36 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:22 PM PDT 24
Peak memory 312160 kb
Host smart-5aab35ba-0c5f-4ad4-aaa4-d6c27dcde97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066695571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2066695571
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3573471944
Short name T467
Test name
Test status
Simulation time 51855727 ps
CPU time 0.62 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:57 PM PDT 24
Peak memory 204056 kb
Host smart-2c8df146-42c4-4b1d-a59b-ef0d0889e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573471944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3573471944
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3466749691
Short name T491
Test name
Test status
Simulation time 2759562863 ps
CPU time 29.29 seconds
Started May 14 12:47:48 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 212780 kb
Host smart-b128fcf8-cb9e-4a02-b63e-fdaeee08c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466749691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3466749691
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3747720308
Short name T762
Test name
Test status
Simulation time 13089407332 ps
CPU time 25.58 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:48:18 PM PDT 24
Peak memory 337700 kb
Host smart-cf725b79-4e09-424e-b14a-9341b4963e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747720308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3747720308
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.1510101741
Short name T1096
Test name
Test status
Simulation time 47826639572 ps
CPU time 1679.81 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 2703728 kb
Host smart-145f1455-b9b0-44d6-b309-e59dc332b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510101741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1510101741
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1766410747
Short name T722
Test name
Test status
Simulation time 1915611139 ps
CPU time 7.89 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 212544 kb
Host smart-ebeda368-a6c8-44f9-837c-44312b6e9cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766410747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1766410747
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3370375519
Short name T575
Test name
Test status
Simulation time 1490297587 ps
CPU time 3.74 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:00 PM PDT 24
Peak memory 212544 kb
Host smart-3fed44fe-ad67-45a3-987b-50049f45810b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370375519 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3370375519
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.4277198517
Short name T550
Test name
Test status
Simulation time 10221939411 ps
CPU time 16.22 seconds
Started May 14 12:47:59 PM PDT 24
Finished May 14 12:48:17 PM PDT 24
Peak memory 277880 kb
Host smart-40c4e410-806f-44fe-81be-6cd176f84354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277198517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.4277198517
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2058268243
Short name T941
Test name
Test status
Simulation time 10666166949 ps
CPU time 10.3 seconds
Started May 14 12:47:52 PM PDT 24
Finished May 14 12:48:04 PM PDT 24
Peak memory 252444 kb
Host smart-ab5ac936-e603-44dd-8566-3b6d8f73d865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058268243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2058268243
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.631961402
Short name T726
Test name
Test status
Simulation time 339192622 ps
CPU time 2.31 seconds
Started May 14 12:47:58 PM PDT 24
Finished May 14 12:48:02 PM PDT 24
Peak memory 204340 kb
Host smart-a7924507-592f-4e19-860c-7cf4ea9401b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631961402 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.631961402
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.235704796
Short name T750
Test name
Test status
Simulation time 8453806674 ps
CPU time 7.66 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 212676 kb
Host smart-6d8dc3fe-650b-46ff-9284-889195374e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235704796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.235704796
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2027525508
Short name T1230
Test name
Test status
Simulation time 11782865814 ps
CPU time 197.88 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:51:11 PM PDT 24
Peak memory 2976928 kb
Host smart-93bfee80-1df6-4fe9-b7ae-87561f16f51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027525508 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2027525508
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1513715029
Short name T494
Test name
Test status
Simulation time 1706683501 ps
CPU time 12.44 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 204344 kb
Host smart-280a4b34-9b89-4e47-b71d-ccd8ad290dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513715029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1513715029
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1270878985
Short name T477
Test name
Test status
Simulation time 775513701 ps
CPU time 31.15 seconds
Started May 14 12:47:46 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 204616 kb
Host smart-bfab9443-c396-469a-9570-b71a60a80565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270878985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1270878985
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1479626066
Short name T346
Test name
Test status
Simulation time 13685638430 ps
CPU time 25.72 seconds
Started May 14 12:47:50 PM PDT 24
Finished May 14 12:48:17 PM PDT 24
Peak memory 204448 kb
Host smart-4a8d74dc-c5ac-4753-8ade-842343244a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479626066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1479626066
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1617559721
Short name T874
Test name
Test status
Simulation time 1309444349 ps
CPU time 6.51 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:48:04 PM PDT 24
Peak memory 204504 kb
Host smart-2803d905-1855-460b-9211-ac4628eb66aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617559721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1617559721
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.1459300815
Short name T1247
Test name
Test status
Simulation time 1004907928 ps
CPU time 6.21 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 215148 kb
Host smart-68be1920-df05-46c0-a45d-570159b605cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459300815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.1459300815
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2713526125
Short name T521
Test name
Test status
Simulation time 33170247 ps
CPU time 0.58 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:57 PM PDT 24
Peak memory 204144 kb
Host smart-836c30af-f80f-4531-9fa7-e06b1befbd09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713526125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2713526125
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2021775296
Short name T880
Test name
Test status
Simulation time 397641039 ps
CPU time 1.4 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 212632 kb
Host smart-bbaa3c23-37ab-434b-9cd5-749cc4309f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021775296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2021775296
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.314132062
Short name T1288
Test name
Test status
Simulation time 1088047865 ps
CPU time 5.07 seconds
Started May 14 12:47:52 PM PDT 24
Finished May 14 12:47:58 PM PDT 24
Peak memory 263360 kb
Host smart-ceca1777-565b-4d90-835a-275bbe6b29ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314132062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.314132062
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.70024007
Short name T153
Test name
Test status
Simulation time 1282702576 ps
CPU time 31.17 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 268284 kb
Host smart-dc8fa5e3-2b7a-49e7-8156-aefa0552226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70024007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.70024007
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3670566793
Short name T1362
Test name
Test status
Simulation time 1693401254 ps
CPU time 54.9 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:49:00 PM PDT 24
Peak memory 601796 kb
Host smart-d1cd96df-4ffa-460c-a10e-615890c8eaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670566793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3670566793
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.491992081
Short name T1260
Test name
Test status
Simulation time 388734660 ps
CPU time 4.85 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:48:10 PM PDT 24
Peak memory 204216 kb
Host smart-7e97b728-50d0-41f7-ae35-7091cedf6791
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491992081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
491992081
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2457154810
Short name T1179
Test name
Test status
Simulation time 2800234562 ps
CPU time 70.78 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 824020 kb
Host smart-84bdb43a-e5df-484d-bf2b-0c432633ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457154810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2457154810
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2352851130
Short name T835
Test name
Test status
Simulation time 992124218 ps
CPU time 3.47 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 204400 kb
Host smart-04863edf-d791-4a82-a615-07fc8a4bd6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352851130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2352851130
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.23157526
Short name T348
Test name
Test status
Simulation time 6068742219 ps
CPU time 29.5 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:28 PM PDT 24
Peak memory 332076 kb
Host smart-66d0dff7-3b26-4c01-af81-0c90d5490c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23157526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.23157526
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2116970737
Short name T137
Test name
Test status
Simulation time 55244897 ps
CPU time 0.68 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:47:56 PM PDT 24
Peak memory 204100 kb
Host smart-6e7ab191-49f8-4e6f-b552-7f7237d6de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116970737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2116970737
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1851769690
Short name T209
Test name
Test status
Simulation time 49459519457 ps
CPU time 1650.5 seconds
Started May 14 12:47:57 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 2901844 kb
Host smart-bd528d2d-a2a0-45c1-8d18-3e26b7bf885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851769690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1851769690
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.227023921
Short name T143
Test name
Test status
Simulation time 3857852117 ps
CPU time 31.01 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 355784 kb
Host smart-062dabe0-10ad-4711-a90c-d56586cbf9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227023921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.227023921
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2795556839
Short name T119
Test name
Test status
Simulation time 4802823217 ps
CPU time 145.24 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:50:20 PM PDT 24
Peak memory 884520 kb
Host smart-8d95c675-2f67-4700-b885-018d00a7dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795556839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2795556839
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1269668898
Short name T1188
Test name
Test status
Simulation time 664277745 ps
CPU time 11.03 seconds
Started May 14 12:47:58 PM PDT 24
Finished May 14 12:48:11 PM PDT 24
Peak memory 220696 kb
Host smart-d4468716-2a4d-46d1-9030-f1a5644580cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269668898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1269668898
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1546213528
Short name T925
Test name
Test status
Simulation time 794333548 ps
CPU time 3.06 seconds
Started May 14 12:48:03 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 204452 kb
Host smart-bff39fd5-c3ef-4af7-baf0-3b3e7bd96ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546213528 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1546213528
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.443956850
Short name T1071
Test name
Test status
Simulation time 10132213689 ps
CPU time 15.47 seconds
Started May 14 12:47:58 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 269528 kb
Host smart-22f1bf00-dcaf-4b8e-b49e-a0bac220ec8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443956850 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.443956850
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3248748658
Short name T548
Test name
Test status
Simulation time 10074264721 ps
CPU time 72.83 seconds
Started May 14 12:47:52 PM PDT 24
Finished May 14 12:49:06 PM PDT 24
Peak memory 541280 kb
Host smart-424076b2-bb5a-4e6d-bb1e-3fe23db125e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248748658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3248748658
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1730523081
Short name T1102
Test name
Test status
Simulation time 1890262752 ps
CPU time 2.91 seconds
Started May 14 12:47:57 PM PDT 24
Finished May 14 12:48:02 PM PDT 24
Peak memory 204416 kb
Host smart-4a0c290d-7d15-4314-bc8d-43e0bd9eccde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730523081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1730523081
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2446080563
Short name T914
Test name
Test status
Simulation time 811166895 ps
CPU time 4.51 seconds
Started May 14 12:47:52 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 204268 kb
Host smart-8e289fd7-0fb8-4608-b067-aa1ee7627a91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446080563 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2446080563
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3406310678
Short name T649
Test name
Test status
Simulation time 17741124912 ps
CPU time 247.72 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:52:05 PM PDT 24
Peak memory 2814716 kb
Host smart-59bd5c2c-e4a9-42fa-9f98-91c6001daa05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406310678 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3406310678
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.452759177
Short name T736
Test name
Test status
Simulation time 907217367 ps
CPU time 11.6 seconds
Started May 14 12:47:58 PM PDT 24
Finished May 14 12:48:11 PM PDT 24
Peak memory 204328 kb
Host smart-934774c1-6888-4888-982d-7adab29bb042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452759177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.452759177
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3073710820
Short name T818
Test name
Test status
Simulation time 3454906125 ps
CPU time 23.91 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:23 PM PDT 24
Peak memory 227648 kb
Host smart-efd6186c-b2ce-46e5-baea-a568501b12a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073710820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3073710820
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2134001976
Short name T772
Test name
Test status
Simulation time 20795942683 ps
CPU time 9.48 seconds
Started May 14 12:47:59 PM PDT 24
Finished May 14 12:48:10 PM PDT 24
Peak memory 204468 kb
Host smart-fc69384e-82b0-4e20-acf3-a742e195fc62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134001976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2134001976
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.5283789
Short name T786
Test name
Test status
Simulation time 7721293432 ps
CPU time 137.27 seconds
Started May 14 12:47:54 PM PDT 24
Finished May 14 12:50:14 PM PDT 24
Peak memory 736296 kb
Host smart-19d7ca4c-0870-47aa-a718-3c041a7f4d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5283789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_stretch.5283789
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3110833744
Short name T659
Test name
Test status
Simulation time 1103154391 ps
CPU time 6.7 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 215620 kb
Host smart-473064eb-910a-43af-9ed8-81b96573d216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110833744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3110833744
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2671929070
Short name T1345
Test name
Test status
Simulation time 19909148 ps
CPU time 0.66 seconds
Started May 14 12:48:05 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 204132 kb
Host smart-c5b1c92c-98a6-47ca-8859-6c26e4153465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671929070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2671929070
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1694064682
Short name T969
Test name
Test status
Simulation time 474601229 ps
CPU time 1.49 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:48:03 PM PDT 24
Peak memory 212664 kb
Host smart-9cf5675c-c264-48a6-bd7e-f4a95dac347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694064682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1694064682
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.564205409
Short name T935
Test name
Test status
Simulation time 944276267 ps
CPU time 3.97 seconds
Started May 14 12:47:51 PM PDT 24
Finished May 14 12:47:57 PM PDT 24
Peak memory 227892 kb
Host smart-1b9e7348-ec6b-46ca-8817-494b83a6ba8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564205409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.564205409
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.658545280
Short name T64
Test name
Test status
Simulation time 4011657614 ps
CPU time 68.49 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 657492 kb
Host smart-513225dc-e271-4bc7-83c9-f824051fab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658545280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.658545280
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2879364346
Short name T53
Test name
Test status
Simulation time 7204320398 ps
CPU time 63 seconds
Started May 14 12:47:59 PM PDT 24
Finished May 14 12:49:04 PM PDT 24
Peak memory 628440 kb
Host smart-279ea1ae-3fb6-4a9f-ab4b-8f0c69d2c7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879364346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2879364346
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2957276071
Short name T718
Test name
Test status
Simulation time 489199116 ps
CPU time 0.95 seconds
Started May 14 12:47:58 PM PDT 24
Finished May 14 12:48:01 PM PDT 24
Peak memory 204156 kb
Host smart-3b3bd265-4cce-4713-a4a7-b1030f943fa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957276071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2957276071
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.4097711547
Short name T889
Test name
Test status
Simulation time 124757943 ps
CPU time 2.92 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 204468 kb
Host smart-92415faa-294d-49b5-b23f-fe48eb2b7b01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097711547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.4097711547
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2517490152
Short name T1201
Test name
Test status
Simulation time 10987404185 ps
CPU time 157.93 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:50:39 PM PDT 24
Peak memory 804816 kb
Host smart-fe564b78-88f4-4cf7-accf-0dc7271b5cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517490152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2517490152
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3673022382
Short name T1333
Test name
Test status
Simulation time 3913984027 ps
CPU time 11.17 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 204308 kb
Host smart-e514b67d-d49b-49b3-8020-b3c6a8adc065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673022382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3673022382
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2662100624
Short name T388
Test name
Test status
Simulation time 4006855562 ps
CPU time 90.4 seconds
Started May 14 12:48:02 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 350272 kb
Host smart-4e49ddd8-9b09-4574-bd02-763d3a5116d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662100624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2662100624
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.4281174091
Short name T1355
Test name
Test status
Simulation time 74544854 ps
CPU time 0.64 seconds
Started May 14 12:47:56 PM PDT 24
Finished May 14 12:47:59 PM PDT 24
Peak memory 204068 kb
Host smart-fc4bcf22-67d4-48eb-9073-955f5cf0abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281174091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4281174091
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2526598077
Short name T36
Test name
Test status
Simulation time 2987537122 ps
CPU time 4.8 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 250800 kb
Host smart-9d644486-ad32-485d-afdf-c495ca2dca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526598077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2526598077
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4080025616
Short name T611
Test name
Test status
Simulation time 2361307641 ps
CPU time 17.88 seconds
Started May 14 12:47:53 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 310160 kb
Host smart-fbf1b7c0-9305-47ad-8be8-445dd85e3525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080025616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4080025616
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.271591283
Short name T604
Test name
Test status
Simulation time 2639709771 ps
CPU time 12.04 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 229864 kb
Host smart-a811d2f0-7693-4f6a-8623-0a194077b72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271591283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.271591283
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.898581539
Short name T861
Test name
Test status
Simulation time 3747925557 ps
CPU time 5.05 seconds
Started May 14 12:48:03 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 212616 kb
Host smart-d37a2945-3f68-47d9-8536-821254cc3d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898581539 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.898581539
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.775093500
Short name T823
Test name
Test status
Simulation time 10590571599 ps
CPU time 13.89 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 255404 kb
Host smart-71eccb25-8dd7-46ce-9bcf-a8762dcf2024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775093500 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.775093500
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.98271425
Short name T1078
Test name
Test status
Simulation time 10221504658 ps
CPU time 16.74 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:48:26 PM PDT 24
Peak memory 269096 kb
Host smart-1fe810f1-9022-4cf0-a9f3-2bf2639276af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98271425 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_fifo_reset_tx.98271425
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.735407677
Short name T27
Test name
Test status
Simulation time 1669520834 ps
CPU time 2.29 seconds
Started May 14 12:48:05 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 204360 kb
Host smart-3855b515-9c5c-4222-86dd-dc36b5878409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735407677 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.735407677
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3770659940
Short name T794
Test name
Test status
Simulation time 2687822805 ps
CPU time 4.28 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 204360 kb
Host smart-36c9bd92-4e66-4a80-a05e-a06744f750a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770659940 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3770659940
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1049091827
Short name T439
Test name
Test status
Simulation time 22021530972 ps
CPU time 6.97 seconds
Started May 14 12:48:02 PM PDT 24
Finished May 14 12:48:11 PM PDT 24
Peak memory 204368 kb
Host smart-b0322b66-081b-4124-9ae9-56281043ec5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049091827 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1049091827
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.315038983
Short name T675
Test name
Test status
Simulation time 576633976 ps
CPU time 18.9 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 204480 kb
Host smart-dc2542b7-883a-4083-a891-c14d814582a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315038983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.315038983
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.4029184702
Short name T752
Test name
Test status
Simulation time 4355244096 ps
CPU time 15.56 seconds
Started May 14 12:48:02 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 220296 kb
Host smart-b72a0cff-fb6f-4322-a288-6018fd01b4ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029184702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.4029184702
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3787561032
Short name T938
Test name
Test status
Simulation time 8211187335 ps
CPU time 8.62 seconds
Started May 14 12:47:59 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 204440 kb
Host smart-5b1c5c48-a836-4345-b250-0967caeadfed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787561032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3787561032
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.5276749
Short name T367
Test name
Test status
Simulation time 12205770175 ps
CPU time 37.76 seconds
Started May 14 12:48:03 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 621996 kb
Host smart-83f620f2-44b5-4ef9-9f3d-c3536dd7292a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5276749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_stretch.5276749
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.308187589
Short name T462
Test name
Test status
Simulation time 14981037882 ps
CPU time 7.18 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:48:08 PM PDT 24
Peak memory 218916 kb
Host smart-78bff566-1478-4c72-b77b-fd3dd238c486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308187589 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.308187589
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1721652457
Short name T1023
Test name
Test status
Simulation time 17284121 ps
CPU time 0.63 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 204124 kb
Host smart-595758b6-9338-40b0-8483-6bcb309e9e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721652457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1721652457
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.528963575
Short name T644
Test name
Test status
Simulation time 202122725 ps
CPU time 1.55 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:48:09 PM PDT 24
Peak memory 212744 kb
Host smart-2edc249f-23da-4a6e-aab2-d39c64d6cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528963575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.528963575
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1739537768
Short name T500
Test name
Test status
Simulation time 534162572 ps
CPU time 2.95 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 228508 kb
Host smart-98257af7-82db-4847-96bd-7eb9c0305789
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739537768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1739537768
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1497411824
Short name T1011
Test name
Test status
Simulation time 2608294346 ps
CPU time 146 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:50:29 PM PDT 24
Peak memory 685028 kb
Host smart-eaf667e2-3617-4912-b983-e77eeda1b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497411824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1497411824
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.868279110
Short name T1353
Test name
Test status
Simulation time 3769680879 ps
CPU time 142.41 seconds
Started May 14 12:48:02 PM PDT 24
Finished May 14 12:50:26 PM PDT 24
Peak memory 674432 kb
Host smart-b4de4fcf-16bf-462f-b8d3-b3264734d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868279110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.868279110
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.613459386
Short name T287
Test name
Test status
Simulation time 301955648 ps
CPU time 0.95 seconds
Started May 14 12:48:00 PM PDT 24
Finished May 14 12:48:03 PM PDT 24
Peak memory 204340 kb
Host smart-3e319972-e2bd-404f-bd93-5d155e7cee8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613459386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.613459386
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.680066099
Short name T1302
Test name
Test status
Simulation time 851197300 ps
CPU time 8.85 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:48:18 PM PDT 24
Peak memory 204360 kb
Host smart-75e5b9c5-f6e4-476f-bbfa-e05a5027aafa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680066099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
680066099
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.4178371777
Short name T1214
Test name
Test status
Simulation time 2190861653 ps
CPU time 138.67 seconds
Started May 14 12:48:04 PM PDT 24
Finished May 14 12:50:24 PM PDT 24
Peak memory 745932 kb
Host smart-f6915a36-86d2-4c42-9d86-f05ba8220919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178371777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.4178371777
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1574929525
Short name T628
Test name
Test status
Simulation time 709539842 ps
CPU time 6.37 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:48:13 PM PDT 24
Peak memory 204380 kb
Host smart-1a54b4a6-d044-4b86-8100-f4e79beb8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574929525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1574929525
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.2473193404
Short name T977
Test name
Test status
Simulation time 65654170 ps
CPU time 0.67 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:48:04 PM PDT 24
Peak memory 203996 kb
Host smart-c7f9c0ed-be3b-4226-a5bc-1e06d01b4322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473193404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2473193404
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3417026999
Short name T1329
Test name
Test status
Simulation time 5140248266 ps
CPU time 58.38 seconds
Started May 14 12:48:07 PM PDT 24
Finished May 14 12:49:07 PM PDT 24
Peak memory 204392 kb
Host smart-ad516608-f6a2-4a04-aa80-d084b0bbb042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417026999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3417026999
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2146089481
Short name T631
Test name
Test status
Simulation time 2744812486 ps
CPU time 64.74 seconds
Started May 14 12:48:01 PM PDT 24
Finished May 14 12:49:07 PM PDT 24
Peak memory 302188 kb
Host smart-251ebf07-f48b-4a6d-8d86-e03fbc666c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146089481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2146089481
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.587025821
Short name T1133
Test name
Test status
Simulation time 46057807249 ps
CPU time 673.68 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:59:21 PM PDT 24
Peak memory 2528356 kb
Host smart-9dbaff24-7d44-4b66-9514-0a984c9c140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587025821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.587025821
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.92832853
Short name T533
Test name
Test status
Simulation time 12924875548 ps
CPU time 31.04 seconds
Started May 14 12:48:07 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 212632 kb
Host smart-c5892a1e-b20b-4ff9-b54e-8202b9f4bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92832853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.92832853
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2771451665
Short name T875
Test name
Test status
Simulation time 3564295914 ps
CPU time 4.54 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 212724 kb
Host smart-65201def-7f23-463a-bff2-ca87d816fbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771451665 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2771451665
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2724249636
Short name T951
Test name
Test status
Simulation time 10550199177 ps
CPU time 13.28 seconds
Started May 14 12:48:09 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 257596 kb
Host smart-4b236c9c-fd88-4b5e-b2c5-a21c74ec8a1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724249636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2724249636
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.266866085
Short name T883
Test name
Test status
Simulation time 10108415865 ps
CPU time 14.18 seconds
Started May 14 12:48:05 PM PDT 24
Finished May 14 12:48:21 PM PDT 24
Peak memory 288296 kb
Host smart-4b4aa455-296f-4476-a52a-23a181d7e2ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266866085 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.266866085
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.614937044
Short name T1215
Test name
Test status
Simulation time 942996444 ps
CPU time 2.77 seconds
Started May 14 12:48:12 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 204280 kb
Host smart-0915b262-f9be-4af4-abf5-b62ea62ee3d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614937044 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.614937044
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.655424265
Short name T1325
Test name
Test status
Simulation time 2222484414 ps
CPU time 5.59 seconds
Started May 14 12:48:10 PM PDT 24
Finished May 14 12:48:17 PM PDT 24
Peak memory 204320 kb
Host smart-05252156-be37-44d8-b04e-10777b6d7df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655424265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.655424265
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.823056694
Short name T1301
Test name
Test status
Simulation time 19208693076 ps
CPU time 51.02 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:49:01 PM PDT 24
Peak memory 1159752 kb
Host smart-bc011186-80a2-4d9a-af40-b58719a5ec2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823056694 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.823056694
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3251079515
Short name T595
Test name
Test status
Simulation time 1750964832 ps
CPU time 15.33 seconds
Started May 14 12:48:11 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 204204 kb
Host smart-02605d29-8713-4264-8c4d-c1b3065ce918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251079515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3251079515
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.146189950
Short name T753
Test name
Test status
Simulation time 753697613 ps
CPU time 14.85 seconds
Started May 14 12:48:10 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 204344 kb
Host smart-6a6e5309-e271-4164-bfaa-45b0b0564160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146189950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.146189950
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.37041062
Short name T1035
Test name
Test status
Simulation time 51882559730 ps
CPU time 1440.83 seconds
Started May 14 12:48:12 PM PDT 24
Finished May 14 01:12:14 PM PDT 24
Peak memory 7995288 kb
Host smart-b5e8d2a5-d827-475b-918d-e36a50021067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stress_wr.37041062
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1757571689
Short name T565
Test name
Test status
Simulation time 6198827039 ps
CPU time 41.47 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:48:49 PM PDT 24
Peak memory 405244 kb
Host smart-68583c29-3a20-48be-ab93-e12f44a7ed9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757571689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1757571689
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1593502428
Short name T601
Test name
Test status
Simulation time 4679450215 ps
CPU time 6.49 seconds
Started May 14 12:48:07 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 220512 kb
Host smart-a36333f4-6377-470d-b3ed-80bcbe14914c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593502428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1593502428
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2692325426
Short name T292
Test name
Test status
Simulation time 18966867 ps
CPU time 0.64 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 204232 kb
Host smart-e031daa5-c854-4543-8e37-3359ba98ad4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692325426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2692325426
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3196485820
Short name T1273
Test name
Test status
Simulation time 178164042 ps
CPU time 1.7 seconds
Started May 14 12:48:18 PM PDT 24
Finished May 14 12:48:21 PM PDT 24
Peak memory 212964 kb
Host smart-c16baa43-47e3-4fb9-96b5-826c66283efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196485820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3196485820
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.394699853
Short name T1278
Test name
Test status
Simulation time 350099731 ps
CPU time 17.78 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:48:28 PM PDT 24
Peak memory 276320 kb
Host smart-0a72e108-9a9c-42c8-89c9-e3a372aa620a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394699853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.394699853
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3607543415
Short name T154
Test name
Test status
Simulation time 29668786799 ps
CPU time 95.83 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:49:45 PM PDT 24
Peak memory 798072 kb
Host smart-5015f9dd-a400-446e-836f-b631758d029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607543415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3607543415
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.211559676
Short name T684
Test name
Test status
Simulation time 1385315770 ps
CPU time 42.27 seconds
Started May 14 12:48:07 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 501840 kb
Host smart-714d1bc6-e12e-4a91-91f0-a137255e1dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211559676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.211559676
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.906807403
Short name T466
Test name
Test status
Simulation time 139549253 ps
CPU time 1.22 seconds
Started May 14 12:48:09 PM PDT 24
Finished May 14 12:48:12 PM PDT 24
Peak memory 204432 kb
Host smart-7594138b-a74c-4ec3-bc99-2f88591c5817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906807403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.906807403
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1307517205
Short name T1253
Test name
Test status
Simulation time 137940821 ps
CPU time 3.18 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:48:13 PM PDT 24
Peak memory 224028 kb
Host smart-033255d5-2479-4816-b185-18be082c9f1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307517205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1307517205
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3071362318
Short name T100
Test name
Test status
Simulation time 6224316419 ps
CPU time 61.35 seconds
Started May 14 12:48:08 PM PDT 24
Finished May 14 12:49:11 PM PDT 24
Peak memory 796716 kb
Host smart-a80d9d7b-c6a0-4561-9221-c37569373a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071362318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3071362318
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3417573148
Short name T993
Test name
Test status
Simulation time 1553349138 ps
CPU time 18.92 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:48:34 PM PDT 24
Peak memory 204404 kb
Host smart-0c0c3c95-eb88-4d8e-81a0-2d52e969f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417573148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3417573148
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4122832006
Short name T822
Test name
Test status
Simulation time 1495594656 ps
CPU time 71.8 seconds
Started May 14 12:48:18 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 342756 kb
Host smart-be82b481-a5f7-4a71-80e4-ffa4fb6726b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122832006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4122832006
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.2746626364
Short name T1274
Test name
Test status
Simulation time 21116450 ps
CPU time 0.67 seconds
Started May 14 12:48:06 PM PDT 24
Finished May 14 12:48:07 PM PDT 24
Peak memory 204100 kb
Host smart-b54c2a10-b159-49a2-a1e2-80ce38cbb57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746626364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2746626364
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2426018320
Short name T156
Test name
Test status
Simulation time 2643302014 ps
CPU time 112.59 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:50:08 PM PDT 24
Peak memory 256772 kb
Host smart-f1f25ead-03b5-46ce-94f0-7db460f572bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426018320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2426018320
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.4177241585
Short name T78
Test name
Test status
Simulation time 12082717142 ps
CPU time 29 seconds
Started May 14 12:48:12 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 325964 kb
Host smart-82235c74-6acd-4c14-84d2-b92388ca6529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177241585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.4177241585
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.256172546
Short name T251
Test name
Test status
Simulation time 3436093664 ps
CPU time 33.54 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 220836 kb
Host smart-f7ee0d0a-ddbf-4551-8448-eaf36682e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256172546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.256172546
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.518818237
Short name T744
Test name
Test status
Simulation time 1495285074 ps
CPU time 12.07 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 220808 kb
Host smart-454ae814-492d-48f0-9d79-245c07734f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518818237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.518818237
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.68306012
Short name T913
Test name
Test status
Simulation time 3453934792 ps
CPU time 4.35 seconds
Started May 14 12:48:13 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 212684 kb
Host smart-95b8c9d5-17da-48bc-9380-3f546e460a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68306012 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_bad_addr.68306012
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.523957185
Short name T528
Test name
Test status
Simulation time 10144251632 ps
CPU time 14.41 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:48:36 PM PDT 24
Peak memory 282756 kb
Host smart-b3c30464-2c5a-44e4-9da0-d1832945d7e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523957185 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.523957185
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.502040007
Short name T594
Test name
Test status
Simulation time 10240043721 ps
CPU time 13.87 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 12:48:31 PM PDT 24
Peak memory 278700 kb
Host smart-e915f9b2-2350-4954-b7b0-ff2c220a676d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502040007 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.502040007
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3774436272
Short name T1130
Test name
Test status
Simulation time 2124180050 ps
CPU time 2.14 seconds
Started May 14 12:48:18 PM PDT 24
Finished May 14 12:48:22 PM PDT 24
Peak memory 204388 kb
Host smart-fdcfa06b-56c8-4513-9b03-2009c25dfced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774436272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3774436272
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2676047181
Short name T1284
Test name
Test status
Simulation time 2234476736 ps
CPU time 5.2 seconds
Started May 14 12:48:13 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 212668 kb
Host smart-bc2cff41-44b6-44f5-87f4-6d33d1ecb497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676047181 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2676047181
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.197295133
Short name T1091
Test name
Test status
Simulation time 16285208193 ps
CPU time 44.46 seconds
Started May 14 12:48:13 PM PDT 24
Finished May 14 12:48:58 PM PDT 24
Peak memory 1096512 kb
Host smart-54156ff2-5ea4-4aa7-9d62-54ab8dcfb3eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197295133 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.197295133
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.333888093
Short name T437
Test name
Test status
Simulation time 962255501 ps
CPU time 12.8 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 204328 kb
Host smart-e5837ab4-ad2d-4997-a3a7-84452c567036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333888093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.333888093
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2526849668
Short name T1239
Test name
Test status
Simulation time 1360710675 ps
CPU time 56.14 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 206452 kb
Host smart-91d47745-591b-440d-bd2b-91a5688abab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526849668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2526849668
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3073487437
Short name T431
Test name
Test status
Simulation time 32834136809 ps
CPU time 104.97 seconds
Started May 14 12:48:17 PM PDT 24
Finished May 14 12:50:03 PM PDT 24
Peak memory 1609560 kb
Host smart-5de84b7c-8ca4-4273-97a1-b6fb7137b195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073487437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3073487437
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.467317837
Short name T721
Test name
Test status
Simulation time 28020161250 ps
CPU time 1342.42 seconds
Started May 14 12:48:18 PM PDT 24
Finished May 14 01:10:42 PM PDT 24
Peak memory 5387680 kb
Host smart-7adbf2ec-333a-4bd4-a5c5-302903e5a612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467317837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.467317837
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2935631972
Short name T419
Test name
Test status
Simulation time 1609482140 ps
CPU time 8.59 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 218072 kb
Host smart-2e7ca1cd-f235-4f86-9e56-8988bde978e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935631972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2935631972
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3853121157
Short name T1320
Test name
Test status
Simulation time 24033568 ps
CPU time 0.59 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:48:22 PM PDT 24
Peak memory 203988 kb
Host smart-470a025e-66d2-4a15-ab68-cd39dc9bd279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853121157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3853121157
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3893250142
Short name T700
Test name
Test status
Simulation time 73656422 ps
CPU time 1.19 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 215388 kb
Host smart-9774e69f-0927-4492-996c-1047dd252255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893250142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3893250142
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1238443241
Short name T860
Test name
Test status
Simulation time 445639860 ps
CPU time 23.54 seconds
Started May 14 12:48:13 PM PDT 24
Finished May 14 12:48:38 PM PDT 24
Peak memory 297788 kb
Host smart-79c3c884-58ad-4a48-b7b7-0e6fb305e6bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238443241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1238443241
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1042743576
Short name T578
Test name
Test status
Simulation time 2320190327 ps
CPU time 70.63 seconds
Started May 14 12:48:13 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 774816 kb
Host smart-95feabfa-10b6-4c51-80e5-75af40b16b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042743576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1042743576
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.4137050527
Short name T975
Test name
Test status
Simulation time 2234606825 ps
CPU time 66.81 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 693808 kb
Host smart-b1993ad2-fd09-4299-ab56-f056b3592bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137050527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.4137050527
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3841989964
Short name T445
Test name
Test status
Simulation time 495226124 ps
CPU time 0.99 seconds
Started May 14 12:48:12 PM PDT 24
Finished May 14 12:48:14 PM PDT 24
Peak memory 204208 kb
Host smart-4b888855-ce64-4d18-9507-d478d96151a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841989964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3841989964
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1622460932
Short name T1141
Test name
Test status
Simulation time 170609577 ps
CPU time 3.79 seconds
Started May 14 12:48:17 PM PDT 24
Finished May 14 12:48:22 PM PDT 24
Peak memory 204436 kb
Host smart-42e4132d-9179-4b8b-b346-e46e01b8a75f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622460932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1622460932
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1579403480
Short name T70
Test name
Test status
Simulation time 4392180817 ps
CPU time 335.6 seconds
Started May 14 12:48:17 PM PDT 24
Finished May 14 12:53:54 PM PDT 24
Peak memory 1264540 kb
Host smart-cd998fa6-5efb-444e-9b17-6d60977cc335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579403480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1579403480
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.536408679
Short name T1332
Test name
Test status
Simulation time 1194493772 ps
CPU time 12.22 seconds
Started May 14 12:48:22 PM PDT 24
Finished May 14 12:48:35 PM PDT 24
Peak memory 204388 kb
Host smart-4799654d-e1d4-4fd1-98de-20dcba96444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536408679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.536408679
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.216929062
Short name T845
Test name
Test status
Simulation time 2455409679 ps
CPU time 28.67 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:55 PM PDT 24
Peak memory 366628 kb
Host smart-caa988fe-dcc9-436a-bfaa-55cc8590b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216929062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.216929062
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2926084473
Short name T774
Test name
Test status
Simulation time 41787932 ps
CPU time 0.64 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:48:16 PM PDT 24
Peak memory 203968 kb
Host smart-b33fd5b2-fdbc-4828-8f8c-4baedccbed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926084473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2926084473
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3311602035
Short name T537
Test name
Test status
Simulation time 2906474851 ps
CPU time 71.59 seconds
Started May 14 12:48:14 PM PDT 24
Finished May 14 12:49:26 PM PDT 24
Peak memory 383524 kb
Host smart-fca14c5f-a292-4bb7-87e8-23cfab2a60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311602035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3311602035
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3788282028
Short name T245
Test name
Test status
Simulation time 9530368733 ps
CPU time 1101.33 seconds
Started May 14 12:48:15 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 1447880 kb
Host smart-d658a801-3ca2-42b2-9e53-d48c103a1168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788282028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3788282028
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.4091482315
Short name T1150
Test name
Test status
Simulation time 476835659 ps
CPU time 7.75 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:48:26 PM PDT 24
Peak memory 212564 kb
Host smart-04de12ea-e238-41e9-bec0-64fc60112d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091482315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4091482315
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.282191456
Short name T1195
Test name
Test status
Simulation time 3017263999 ps
CPU time 3.21 seconds
Started May 14 12:48:23 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 204396 kb
Host smart-1652eb85-c727-449e-9b1b-ec67c44ba1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282191456 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.282191456
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.204884411
Short name T1085
Test name
Test status
Simulation time 10597269540 ps
CPU time 15.19 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:41 PM PDT 24
Peak memory 262324 kb
Host smart-3666b216-33a8-42a6-aa1f-1cc3eee88a59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204884411 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.204884411
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1998790162
Short name T1294
Test name
Test status
Simulation time 11565154556 ps
CPU time 6.86 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 236720 kb
Host smart-af0efa16-1bab-4889-8c2d-341d47adfc97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998790162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1998790162
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2809090481
Short name T12
Test name
Test status
Simulation time 919996391 ps
CPU time 2.76 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 204444 kb
Host smart-72fadafb-f6b8-40b1-88d8-bbd882d4a205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809090481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2809090481
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3833775954
Short name T362
Test name
Test status
Simulation time 4941466811 ps
CPU time 6.01 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 219384 kb
Host smart-9e63a948-2090-4c6e-9293-658d68beb6c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833775954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3833775954
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.391204394
Short name T1120
Test name
Test status
Simulation time 23030404963 ps
CPU time 538.73 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:57:17 PM PDT 24
Peak memory 5722704 kb
Host smart-abfc4238-3eee-49dd-b9cb-fc01bb5b81ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391204394 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.391204394
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1377983975
Short name T739
Test name
Test status
Simulation time 1498964761 ps
CPU time 13.4 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:48:31 PM PDT 24
Peak memory 204236 kb
Host smart-0debb087-64e1-494c-8e51-d3b451a63787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377983975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1377983975
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2639422453
Short name T305
Test name
Test status
Simulation time 1458874059 ps
CPU time 24.57 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 217760 kb
Host smart-20b20b7c-2922-48c3-91f0-467d1560921f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639422453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2639422453
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1498890746
Short name T982
Test name
Test status
Simulation time 33685184987 ps
CPU time 42.08 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 857636 kb
Host smart-8f59d95a-eb0b-4400-a423-deaaf9c59c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498890746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1498890746
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2532714560
Short name T683
Test name
Test status
Simulation time 7180142960 ps
CPU time 667.02 seconds
Started May 14 12:48:16 PM PDT 24
Finished May 14 12:59:25 PM PDT 24
Peak memory 1875784 kb
Host smart-d60cf101-bf7b-4a19-becb-d684798a9467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532714560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2532714560
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.173911596
Short name T264
Test name
Test status
Simulation time 15259236692 ps
CPU time 7.46 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 220716 kb
Host smart-a876095f-cc6d-44b2-8607-b23a737bf48c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173911596 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.173911596
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3847749056
Short name T942
Test name
Test status
Simulation time 38667811 ps
CPU time 0.64 seconds
Started May 14 12:48:30 PM PDT 24
Finished May 14 12:48:32 PM PDT 24
Peak memory 204248 kb
Host smart-3ffcd63d-9ff5-4bba-a848-79e50533c7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847749056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3847749056
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2904159101
Short name T311
Test name
Test status
Simulation time 564986329 ps
CPU time 1.35 seconds
Started May 14 12:48:22 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 220864 kb
Host smart-42604965-0de0-40c0-afaf-29b979a57f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904159101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2904159101
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3090728356
Short name T1323
Test name
Test status
Simulation time 766017091 ps
CPU time 8.29 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:35 PM PDT 24
Peak memory 282164 kb
Host smart-06e6b8f9-dcc4-4aad-a3db-4042299c778a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090728356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3090728356
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2026890948
Short name T271
Test name
Test status
Simulation time 5282715776 ps
CPU time 46.25 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:49:09 PM PDT 24
Peak memory 518680 kb
Host smart-241f7019-a494-4721-a61e-607d1ef58d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026890948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2026890948
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1064587713
Short name T607
Test name
Test status
Simulation time 5315045728 ps
CPU time 31.27 seconds
Started May 14 12:48:23 PM PDT 24
Finished May 14 12:48:57 PM PDT 24
Peak memory 419360 kb
Host smart-e94c76e7-974e-4ee4-ba8c-e5fe89f55e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064587713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1064587713
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.565495268
Short name T218
Test name
Test status
Simulation time 117735139 ps
CPU time 1.11 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 204504 kb
Host smart-7aa271b0-40c9-41b6-8305-a6b6e731a862
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565495268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.565495268
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2953906204
Short name T294
Test name
Test status
Simulation time 163606173 ps
CPU time 3.38 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:48:24 PM PDT 24
Peak memory 224112 kb
Host smart-06a5c292-e58e-408a-bbab-5648fc79b7bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953906204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2953906204
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2283715249
Short name T522
Test name
Test status
Simulation time 16170204655 ps
CPU time 105.1 seconds
Started May 14 12:48:23 PM PDT 24
Finished May 14 12:50:10 PM PDT 24
Peak memory 1180644 kb
Host smart-e9605147-005d-40ed-9db5-c5fd8174aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283715249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2283715249
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.900623123
Short name T228
Test name
Test status
Simulation time 270373076 ps
CPU time 3.75 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:35 PM PDT 24
Peak memory 204368 kb
Host smart-2fa514fe-1647-4bb5-8bc3-75264b04343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900623123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.900623123
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1525463409
Short name T1209
Test name
Test status
Simulation time 3456266481 ps
CPU time 16.65 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:48 PM PDT 24
Peak memory 299928 kb
Host smart-fbcf0b24-de1c-4444-9a7b-1153366f80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525463409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1525463409
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1234674367
Short name T132
Test name
Test status
Simulation time 52256535 ps
CPU time 0.68 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:27 PM PDT 24
Peak memory 204148 kb
Host smart-a434a2a7-f75b-4f18-a9a3-96139caf5685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234674367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1234674367
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2714893304
Short name T669
Test name
Test status
Simulation time 18870667283 ps
CPU time 317.92 seconds
Started May 14 12:48:23 PM PDT 24
Finished May 14 12:53:43 PM PDT 24
Peak memory 1255868 kb
Host smart-933d8273-c05e-4571-a766-9ce01ddae811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714893304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2714893304
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1191590004
Short name T836
Test name
Test status
Simulation time 2392572743 ps
CPU time 21.07 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:47 PM PDT 24
Peak memory 329320 kb
Host smart-68ecfd33-5bf1-47fa-94d5-f64b3e2ab0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191590004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1191590004
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2619857950
Short name T554
Test name
Test status
Simulation time 9219526069 ps
CPU time 794.58 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 01:01:36 PM PDT 24
Peak memory 1832952 kb
Host smart-c84767af-4714-4462-9629-34e93a020373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619857950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2619857950
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3589306981
Short name T509
Test name
Test status
Simulation time 1283976636 ps
CPU time 12.36 seconds
Started May 14 12:48:22 PM PDT 24
Finished May 14 12:48:37 PM PDT 24
Peak memory 216448 kb
Host smart-d45742c0-54ee-4212-b638-092de82c82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589306981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3589306981
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1139339649
Short name T680
Test name
Test status
Simulation time 899610531 ps
CPU time 4.79 seconds
Started May 14 12:48:22 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 204380 kb
Host smart-55083bf8-e33a-4e17-913b-2d5c5b0ba9dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139339649 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1139339649
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1811854112
Short name T709
Test name
Test status
Simulation time 10332342480 ps
CPU time 12.82 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:48:34 PM PDT 24
Peak memory 252412 kb
Host smart-66e46a3a-e3e6-43b8-a596-31daede6bce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811854112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1811854112
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2343930715
Short name T893
Test name
Test status
Simulation time 10188936625 ps
CPU time 18.31 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 304392 kb
Host smart-ac547dba-3311-4f43-bfc5-63ac38d5bf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343930715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2343930715
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.784278114
Short name T1182
Test name
Test status
Simulation time 487246727 ps
CPU time 2.91 seconds
Started May 14 12:48:20 PM PDT 24
Finished May 14 12:48:25 PM PDT 24
Peak memory 204360 kb
Host smart-fd19a0ff-e073-4576-8112-3cf37af68814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784278114 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.784278114
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2804878795
Short name T323
Test name
Test status
Simulation time 2167507442 ps
CPU time 5.63 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:48:28 PM PDT 24
Peak memory 204924 kb
Host smart-5c2617f2-007f-4c12-8c74-395d743f961e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804878795 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2804878795
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1287618656
Short name T1070
Test name
Test status
Simulation time 8558156951 ps
CPU time 15.43 seconds
Started May 14 12:48:22 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 568248 kb
Host smart-01699b08-0bff-49bc-a009-05aae484d962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287618656 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1287618656
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1171520494
Short name T224
Test name
Test status
Simulation time 1467794606 ps
CPU time 12.05 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 204248 kb
Host smart-b15350c3-7554-4a12-bd28-7971797e576e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171520494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1171520494
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1982093555
Short name T809
Test name
Test status
Simulation time 5032345155 ps
CPU time 19.43 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 222008 kb
Host smart-035f07ee-24e3-478d-9230-f17812820af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982093555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1982093555
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1506164189
Short name T1157
Test name
Test status
Simulation time 39532302534 ps
CPU time 164.13 seconds
Started May 14 12:48:23 PM PDT 24
Finished May 14 12:51:09 PM PDT 24
Peak memory 2305468 kb
Host smart-8be3627d-fb3b-4fb5-b2c5-3900bf937589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506164189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1506164189
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3057005261
Short name T1100
Test name
Test status
Simulation time 10081684776 ps
CPU time 350.26 seconds
Started May 14 12:48:21 PM PDT 24
Finished May 14 12:54:13 PM PDT 24
Peak memory 2473072 kb
Host smart-550b86c3-47d4-49a8-bcf2-ed1eca6245c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057005261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3057005261
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2823096558
Short name T1206
Test name
Test status
Simulation time 4566561583 ps
CPU time 6.52 seconds
Started May 14 12:48:24 PM PDT 24
Finished May 14 12:48:32 PM PDT 24
Peak memory 212552 kb
Host smart-250d2216-5276-4906-8db8-2d859b3863e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823096558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2823096558
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.560154892
Short name T1088
Test name
Test status
Simulation time 26137930 ps
CPU time 0.62 seconds
Started May 14 12:48:40 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 204184 kb
Host smart-83e62bc6-0f0d-4a5d-b881-07e43b17ad37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560154892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.560154892
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2158661165
Short name T46
Test name
Test status
Simulation time 131813716 ps
CPU time 1.34 seconds
Started May 14 12:48:31 PM PDT 24
Finished May 14 12:48:34 PM PDT 24
Peak memory 215636 kb
Host smart-f1802b95-4629-4c2d-a830-1ab282b0a4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158661165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2158661165
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1761050309
Short name T1223
Test name
Test status
Simulation time 888586005 ps
CPU time 5.9 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:37 PM PDT 24
Peak memory 255100 kb
Host smart-601e3138-024b-4fe3-b516-0d648aa90c43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761050309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1761050309
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3790179561
Short name T1084
Test name
Test status
Simulation time 1399208489 ps
CPU time 46.46 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 545316 kb
Host smart-71865f03-1f40-4f53-9ad2-ca180bd32839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790179561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3790179561
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.4202422633
Short name T1312
Test name
Test status
Simulation time 8112669577 ps
CPU time 65 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:49:35 PM PDT 24
Peak memory 633552 kb
Host smart-2e950e0f-ead0-455f-8c55-f02b9851fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202422633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.4202422633
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4209767923
Short name T504
Test name
Test status
Simulation time 306740141 ps
CPU time 1.18 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:48:31 PM PDT 24
Peak memory 204652 kb
Host smart-2c346aaa-7184-4d69-827e-c0cdaa994a17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209767923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4209767923
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1255485003
Short name T281
Test name
Test status
Simulation time 293711665 ps
CPU time 6.55 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:37 PM PDT 24
Peak memory 204396 kb
Host smart-2dafb3ea-18a5-4389-9c94-b2b49abdf387
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255485003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1255485003
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1952698980
Short name T627
Test name
Test status
Simulation time 14392750059 ps
CPU time 121.88 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:50:31 PM PDT 24
Peak memory 1385560 kb
Host smart-44cce4a6-8fc8-49e8-bee1-8cb6f56946ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952698980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1952698980
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3898777065
Short name T1347
Test name
Test status
Simulation time 851401644 ps
CPU time 3.2 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:35 PM PDT 24
Peak memory 204356 kb
Host smart-b9a92489-bc13-4a42-9dab-b101c8805a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898777065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3898777065
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3861154892
Short name T668
Test name
Test status
Simulation time 1412182708 ps
CPU time 20.79 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 292840 kb
Host smart-0d2e51d7-86c0-48a2-b010-7b7cc4f4bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861154892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3861154892
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.973769248
Short name T1033
Test name
Test status
Simulation time 82659950 ps
CPU time 0.66 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 12:48:29 PM PDT 24
Peak memory 204108 kb
Host smart-fbcefb26-9848-4285-a665-b5805da34244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973769248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.973769248
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1884684188
Short name T720
Test name
Test status
Simulation time 12345143903 ps
CPU time 932.35 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 01:04:02 PM PDT 24
Peak memory 2928336 kb
Host smart-36e14e72-585e-4790-b0d2-e765541af752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884684188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1884684188
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.621075646
Short name T363
Test name
Test status
Simulation time 916834161 ps
CPU time 44.81 seconds
Started May 14 12:48:30 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 298020 kb
Host smart-db7e8a75-0718-4034-bba5-3cbf5cc7b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621075646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.621075646
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.4236957599
Short name T241
Test name
Test status
Simulation time 8963611392 ps
CPU time 439.9 seconds
Started May 14 12:48:30 PM PDT 24
Finished May 14 12:55:52 PM PDT 24
Peak memory 1537600 kb
Host smart-641e599e-cca0-4031-a5e8-c25e56b4e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236957599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.4236957599
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3808531045
Short name T1228
Test name
Test status
Simulation time 6565359286 ps
CPU time 28.19 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:48:59 PM PDT 24
Peak memory 212712 kb
Host smart-a15afc2a-770c-4bdb-9c41-2c9ccde54181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808531045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3808531045
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2758492756
Short name T1199
Test name
Test status
Simulation time 2079244092 ps
CPU time 3.08 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:48:33 PM PDT 24
Peak memory 204392 kb
Host smart-4595c453-e8ed-41a6-9244-1ceea61358f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758492756 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2758492756
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1568615073
Short name T1240
Test name
Test status
Simulation time 10331697982 ps
CPU time 16.84 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 267560 kb
Host smart-710baefa-f08f-4906-8968-33b841564422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568615073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1568615073
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3313658265
Short name T342
Test name
Test status
Simulation time 700913309 ps
CPU time 2.01 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 12:48:30 PM PDT 24
Peak memory 204444 kb
Host smart-0896d748-8292-4695-9c9f-474a45f8df08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313658265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3313658265
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3805697463
Short name T296
Test name
Test status
Simulation time 4524878025 ps
CPU time 6.44 seconds
Started May 14 12:48:30 PM PDT 24
Finished May 14 12:48:38 PM PDT 24
Peak memory 210652 kb
Host smart-8e48d8aa-d930-4fc3-b54b-eaac35412a6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805697463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3805697463
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3479900479
Short name T432
Test name
Test status
Simulation time 2296292819 ps
CPU time 7.82 seconds
Started May 14 12:48:31 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 435232 kb
Host smart-857d1c4a-2be3-4489-9df1-ac64ed2553ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479900479 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3479900479
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.4245326237
Short name T971
Test name
Test status
Simulation time 22739413724 ps
CPU time 44.45 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:49:15 PM PDT 24
Peak memory 204352 kb
Host smart-891e0305-2d9b-4f1c-90e6-9881ed4fe40d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245326237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.4245326237
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3103180884
Short name T231
Test name
Test status
Simulation time 1214630641 ps
CPU time 22.99 seconds
Started May 14 12:48:27 PM PDT 24
Finished May 14 12:48:52 PM PDT 24
Peak memory 221604 kb
Host smart-f1e34440-1232-46c9-aefe-d12e586e3d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103180884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3103180884
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4280997065
Short name T406
Test name
Test status
Simulation time 9845713039 ps
CPU time 19.21 seconds
Started May 14 12:48:28 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 204264 kb
Host smart-65d2db2e-4770-4d14-b780-112d27d8b6d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280997065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4280997065
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.165958082
Short name T811
Test name
Test status
Simulation time 27651489589 ps
CPU time 44.56 seconds
Started May 14 12:48:29 PM PDT 24
Finished May 14 12:49:16 PM PDT 24
Peak memory 575464 kb
Host smart-765a518f-a6ff-441e-b60c-c9eda15548ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165958082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.165958082
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.387025488
Short name T922
Test name
Test status
Simulation time 1570855529 ps
CPU time 8.03 seconds
Started May 14 12:48:30 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 220744 kb
Host smart-d8459f34-234f-4aa8-8f92-bb7e18409212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387025488 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.387025488
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1817621510
Short name T454
Test name
Test status
Simulation time 33301692 ps
CPU time 0.6 seconds
Started May 14 12:48:41 PM PDT 24
Finished May 14 12:48:43 PM PDT 24
Peak memory 204224 kb
Host smart-bc5382c9-4c84-4ad7-8b4e-f3f98bf4fd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817621510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1817621510
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1855803540
Short name T1067
Test name
Test status
Simulation time 151767209 ps
CPU time 1.02 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 212668 kb
Host smart-a32ebc37-4832-4fcb-a51c-60d7f33176c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855803540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1855803540
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.216468933
Short name T1015
Test name
Test status
Simulation time 714792808 ps
CPU time 9.29 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:48 PM PDT 24
Peak memory 238304 kb
Host smart-b35857f6-af31-4c69-a9a0-b1257873b410
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216468933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.216468933
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.46168358
Short name T55
Test name
Test status
Simulation time 1823323647 ps
CPU time 42.35 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:49:21 PM PDT 24
Peak memory 237556 kb
Host smart-ad9ff68e-099a-43e5-823d-abedb45cd595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46168358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.46168358
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.101898824
Short name T778
Test name
Test status
Simulation time 1501938609 ps
CPU time 46.17 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 574240 kb
Host smart-16d7967b-f775-4690-ba67-e484429270bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101898824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.101898824
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.269424323
Short name T665
Test name
Test status
Simulation time 352343474 ps
CPU time 0.9 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 204176 kb
Host smart-5e0b54d0-a286-4652-9613-7c661e3624c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269424323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.269424323
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3934991291
Short name T616
Test name
Test status
Simulation time 172091409 ps
CPU time 3.61 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 204304 kb
Host smart-a5eb38bf-2cbb-43d8-8b31-b60310b09038
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934991291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3934991291
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2952178473
Short name T1191
Test name
Test status
Simulation time 9565812268 ps
CPU time 111.69 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:50:31 PM PDT 24
Peak memory 1131176 kb
Host smart-c5577511-19ac-4964-8924-09b6ee80e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952178473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2952178473
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2490412295
Short name T234
Test name
Test status
Simulation time 281021070 ps
CPU time 3.99 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:43 PM PDT 24
Peak memory 204452 kb
Host smart-fd8c6e68-77a9-4c91-bb6b-c433ff2bc463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490412295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2490412295
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.839713879
Short name T34
Test name
Test status
Simulation time 2372085147 ps
CPU time 55.22 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 282056 kb
Host smart-8c96e6c1-e99f-4b76-bcda-b2ae05d35c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839713879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.839713879
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2267914947
Short name T1185
Test name
Test status
Simulation time 143509324 ps
CPU time 0.67 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:39 PM PDT 24
Peak memory 204028 kb
Host smart-5811d87d-0754-4bda-a887-b4af64fdcbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267914947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2267914947
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.369930029
Short name T455
Test name
Test status
Simulation time 446157796 ps
CPU time 5.01 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:48:42 PM PDT 24
Peak memory 214052 kb
Host smart-50741eea-240b-46c3-a101-74559a0d0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369930029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.369930029
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3517843971
Short name T756
Test name
Test status
Simulation time 928159525 ps
CPU time 43.53 seconds
Started May 14 12:48:35 PM PDT 24
Finished May 14 12:49:19 PM PDT 24
Peak memory 317808 kb
Host smart-d107e48f-21c4-441d-bb9d-15d2bdced8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517843971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3517843971
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2115322093
Short name T123
Test name
Test status
Simulation time 15961877150 ps
CPU time 554.97 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 1907476 kb
Host smart-9f821613-1ede-448a-a5e3-2d63f4d22ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115322093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2115322093
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.969772171
Short name T885
Test name
Test status
Simulation time 1286097706 ps
CPU time 15.47 seconds
Started May 14 12:48:47 PM PDT 24
Finished May 14 12:49:04 PM PDT 24
Peak memory 212624 kb
Host smart-0ba59b71-8130-4791-af72-1bff8580c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969772171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.969772171
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3916821034
Short name T1038
Test name
Test status
Simulation time 2533022813 ps
CPU time 2.71 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:43 PM PDT 24
Peak memory 204516 kb
Host smart-446d9741-7541-457a-a0d6-3e67a2e58e61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916821034 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3916821034
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3350359686
Short name T605
Test name
Test status
Simulation time 10156162930 ps
CPU time 33.6 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 364180 kb
Host smart-672d178d-1117-4096-a5f7-d0ee15a1e5a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350359686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3350359686
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.27690659
Short name T634
Test name
Test status
Simulation time 10317170197 ps
CPU time 17.46 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:57 PM PDT 24
Peak memory 303876 kb
Host smart-f921f62d-fae1-432d-bec7-e052ae003148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690659 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_fifo_reset_tx.27690659
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1459189280
Short name T652
Test name
Test status
Simulation time 623875280 ps
CPU time 2.13 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:43 PM PDT 24
Peak memory 204372 kb
Host smart-33836392-a796-465c-9d90-6cba8cebc351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459189280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1459189280
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3616298130
Short name T110
Test name
Test status
Simulation time 1601329475 ps
CPU time 4.57 seconds
Started May 14 12:48:35 PM PDT 24
Finished May 14 12:48:41 PM PDT 24
Peak memory 204392 kb
Host smart-829eb0ab-7892-45fd-972c-28214b5d44e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616298130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3616298130
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2927761842
Short name T272
Test name
Test status
Simulation time 10680053066 ps
CPU time 7.91 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:48 PM PDT 24
Peak memory 229972 kb
Host smart-02c00987-b674-43cf-8330-ed5f874b7e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927761842 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2927761842
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2552326759
Short name T1
Test name
Test status
Simulation time 14528430254 ps
CPU time 12.53 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 204440 kb
Host smart-26b11bc2-ca03-41e7-83e8-26347c497b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552326759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2552326759
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.315841085
Short name T542
Test name
Test status
Simulation time 12145351130 ps
CPU time 28.07 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 225260 kb
Host smart-87552e71-2b5f-4490-8853-f65e39a9277f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315841085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.315841085
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2679543865
Short name T1309
Test name
Test status
Simulation time 14800255125 ps
CPU time 10.5 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 204352 kb
Host smart-6c1c9feb-e7a7-4d53-a824-84ef1b0e8442
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679543865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2679543865
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2444755566
Short name T468
Test name
Test status
Simulation time 38949562653 ps
CPU time 271.07 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:53:08 PM PDT 24
Peak memory 1018600 kb
Host smart-87dcbfa0-c16d-4bc3-bb55-34eaf4022145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444755566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2444755566
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.786166379
Short name T9
Test name
Test status
Simulation time 6795661706 ps
CPU time 7.4 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:48:45 PM PDT 24
Peak memory 212748 kb
Host smart-e6536646-f2cf-4a4f-8d67-4f0d028d4d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786166379 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.786166379
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.3183209148
Short name T1351
Test name
Test status
Simulation time 2489672853 ps
CPU time 5.4 seconds
Started May 14 12:48:37 PM PDT 24
Finished May 14 12:48:44 PM PDT 24
Peak memory 204984 kb
Host smart-55500e8c-dbd8-4ef2-a5e6-11ec7ea522c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183209148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.3183209148
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3552974104
Short name T1251
Test name
Test status
Simulation time 21476611 ps
CPU time 0.61 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:48:56 PM PDT 24
Peak memory 204168 kb
Host smart-e5be98f0-87df-4c08-935d-4ac1aec3a272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552974104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3552974104
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2736429180
Short name T1216
Test name
Test status
Simulation time 200072821 ps
CPU time 1.56 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:48:43 PM PDT 24
Peak memory 212768 kb
Host smart-5167f8cb-34ba-4243-bc22-892020b8b962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736429180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2736429180
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1328660154
Short name T571
Test name
Test status
Simulation time 427385499 ps
CPU time 4.3 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:48:45 PM PDT 24
Peak memory 242436 kb
Host smart-6f2b1233-43cc-4414-b2c7-dc2f7e63a329
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328660154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1328660154
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3157282518
Short name T998
Test name
Test status
Simulation time 6361534630 ps
CPU time 106.04 seconds
Started May 14 12:48:41 PM PDT 24
Finished May 14 12:50:28 PM PDT 24
Peak memory 601516 kb
Host smart-4f66fdd2-4bcc-447c-ab9f-fedb658d931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157282518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3157282518
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.848813526
Short name T681
Test name
Test status
Simulation time 31412244889 ps
CPU time 63.85 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:49:41 PM PDT 24
Peak memory 672832 kb
Host smart-eb0a96d3-9d26-4eed-9d87-bec37ee930a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848813526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.848813526
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.549596162
Short name T336
Test name
Test status
Simulation time 341232694 ps
CPU time 1.12 seconds
Started May 14 12:48:36 PM PDT 24
Finished May 14 12:48:38 PM PDT 24
Peak memory 204388 kb
Host smart-c5871562-e787-4dc8-9204-04ee4c204249
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549596162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.549596162
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.762874314
Short name T151
Test name
Test status
Simulation time 318850811 ps
CPU time 4.04 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:44 PM PDT 24
Peak memory 231264 kb
Host smart-701023b1-4941-4a1a-9dee-986c97d8c957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762874314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
762874314
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1736763018
Short name T635
Test name
Test status
Simulation time 17154572185 ps
CPU time 105.03 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:50:26 PM PDT 24
Peak memory 1205588 kb
Host smart-353389bf-35fa-4222-9fcc-7319ec1bc764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736763018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1736763018
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2237963273
Short name T74
Test name
Test status
Simulation time 1382872439 ps
CPU time 15.04 seconds
Started May 14 12:48:47 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 204720 kb
Host smart-0436d924-5fb5-473f-8090-8132b4fd6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237963273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2237963273
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.995644255
Short name T1049
Test name
Test status
Simulation time 2322718564 ps
CPU time 20.29 seconds
Started May 14 12:48:48 PM PDT 24
Finished May 14 12:49:09 PM PDT 24
Peak memory 247632 kb
Host smart-1612cba2-a36b-4e89-9373-1a0fb12129f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995644255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.995644255
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2316238220
Short name T140
Test name
Test status
Simulation time 110324456 ps
CPU time 0.68 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:48:40 PM PDT 24
Peak memory 204156 kb
Host smart-4b2491d1-e9d3-4576-82c2-21cfd363c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316238220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2316238220
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.292895422
Short name T787
Test name
Test status
Simulation time 5410975250 ps
CPU time 28.98 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 511928 kb
Host smart-963d595e-dcf4-4b96-a874-fc16f405d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292895422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.292895422
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.702905166
Short name T300
Test name
Test status
Simulation time 1926287156 ps
CPU time 90.48 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:50:12 PM PDT 24
Peak memory 308884 kb
Host smart-84c1f395-a43e-42a7-8520-c5894fd45c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702905166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.702905166
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.552131370
Short name T584
Test name
Test status
Simulation time 1253912793 ps
CPU time 11.18 seconds
Started May 14 12:48:40 PM PDT 24
Finished May 14 12:48:53 PM PDT 24
Peak memory 213456 kb
Host smart-d46ddc75-2209-49e7-afb6-7fa07513bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552131370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.552131370
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.209952999
Short name T310
Test name
Test status
Simulation time 2863690497 ps
CPU time 2.66 seconds
Started May 14 12:48:47 PM PDT 24
Finished May 14 12:48:51 PM PDT 24
Peak memory 204508 kb
Host smart-af025456-bb2c-4262-8c26-5cbf4bf749c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209952999 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.209952999
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2166775690
Short name T1334
Test name
Test status
Simulation time 10135072189 ps
CPU time 74.72 seconds
Started May 14 12:48:46 PM PDT 24
Finished May 14 12:50:01 PM PDT 24
Peak memory 445428 kb
Host smart-fe437343-3bb1-442d-845c-f8aa7ab27e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166775690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2166775690
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.830352872
Short name T1137
Test name
Test status
Simulation time 10252268929 ps
CPU time 30.03 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:49:21 PM PDT 24
Peak memory 398192 kb
Host smart-29d0431e-5eaf-4396-9670-d1b7b69bce02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830352872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.830352872
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2963085845
Short name T1244
Test name
Test status
Simulation time 1053079293 ps
CPU time 2.08 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:48:54 PM PDT 24
Peak memory 204472 kb
Host smart-c9209b82-5ded-40dc-9b14-0da665aeff73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963085845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2963085845
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3105314873
Short name T840
Test name
Test status
Simulation time 4456612115 ps
CPU time 2.28 seconds
Started May 14 12:48:43 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 215156 kb
Host smart-349cd1f1-4e26-4c94-95b0-d4251c97b7a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105314873 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3105314873
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2502975239
Short name T1213
Test name
Test status
Simulation time 1287914932 ps
CPU time 49.73 seconds
Started May 14 12:48:38 PM PDT 24
Finished May 14 12:49:30 PM PDT 24
Peak memory 204364 kb
Host smart-5ed3645d-8ddd-4484-98f4-1d486a374174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502975239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2502975239
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2341645387
Short name T1031
Test name
Test status
Simulation time 1883281813 ps
CPU time 35.44 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 225724 kb
Host smart-f62b3e06-6c5e-42ba-b16a-5d53e62ee7ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341645387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2341645387
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2525897101
Short name T568
Test name
Test status
Simulation time 22600398547 ps
CPU time 29.27 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:49:11 PM PDT 24
Peak memory 405756 kb
Host smart-26bdd7e1-c5bb-49e3-b623-0e80dd9eadd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525897101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2525897101
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.921712320
Short name T8
Test name
Test status
Simulation time 4687592661 ps
CPU time 17.44 seconds
Started May 14 12:48:39 PM PDT 24
Finished May 14 12:48:58 PM PDT 24
Peak memory 414372 kb
Host smart-a04add8d-6378-4f21-bed1-d0b00e3b03eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921712320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.921712320
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3252752300
Short name T1014
Test name
Test status
Simulation time 4309406247 ps
CPU time 6.08 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:48:58 PM PDT 24
Peak memory 212600 kb
Host smart-0677c38a-c77f-4356-9a9a-40f11023b21c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252752300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3252752300
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2865441099
Short name T819
Test name
Test status
Simulation time 15976482 ps
CPU time 0.63 seconds
Started May 14 12:45:54 PM PDT 24
Finished May 14 12:45:55 PM PDT 24
Peak memory 204172 kb
Host smart-cd9a3ae8-391e-4c10-b8fd-784682d43198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865441099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2865441099
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1149437908
Short name T1163
Test name
Test status
Simulation time 82205215 ps
CPU time 1.94 seconds
Started May 14 12:45:47 PM PDT 24
Finished May 14 12:45:50 PM PDT 24
Peak memory 212768 kb
Host smart-43dad9a7-4cd2-4023-bd09-d2c1480e9bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149437908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1149437908
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.347106768
Short name T505
Test name
Test status
Simulation time 246165371 ps
CPU time 4.62 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:45:44 PM PDT 24
Peak memory 252352 kb
Host smart-6d48b163-45c3-4dc1-a67f-7ea36db58c97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347106768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.347106768
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.978318862
Short name T525
Test name
Test status
Simulation time 5305126601 ps
CPU time 72.88 seconds
Started May 14 12:45:33 PM PDT 24
Finished May 14 12:46:49 PM PDT 24
Peak memory 728220 kb
Host smart-75945f12-f8d0-4544-b722-a0e16f11f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978318862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.978318862
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3885028264
Short name T376
Test name
Test status
Simulation time 4629711018 ps
CPU time 77.05 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:46:57 PM PDT 24
Peak memory 482260 kb
Host smart-e3c38b42-f711-4c5f-a5b0-0b187ac29ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885028264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3885028264
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.309855633
Short name T617
Test name
Test status
Simulation time 199653435 ps
CPU time 0.99 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 204300 kb
Host smart-a6dca2b9-51c8-403a-a1d1-313690d7f41c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309855633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.309855633
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2383659714
Short name T212
Test name
Test status
Simulation time 110826411 ps
CPU time 3.06 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:41 PM PDT 24
Peak memory 204468 kb
Host smart-d2dc0c43-865f-437a-b084-5396d635b2a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383659714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2383659714
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1843516810
Short name T1342
Test name
Test status
Simulation time 4273738404 ps
CPU time 332.8 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:51:15 PM PDT 24
Peak memory 1228052 kb
Host smart-c9b09d97-a6d3-4dc2-855b-8ad97ef5aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843516810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1843516810
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2476036815
Short name T1146
Test name
Test status
Simulation time 746071806 ps
CPU time 6.62 seconds
Started May 14 12:45:53 PM PDT 24
Finished May 14 12:46:00 PM PDT 24
Peak memory 204456 kb
Host smart-0413fbfe-65e1-40a0-bbfc-54af9e143e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476036815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2476036815
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1048050041
Short name T598
Test name
Test status
Simulation time 10121585196 ps
CPU time 73.47 seconds
Started May 14 12:45:50 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 285560 kb
Host smart-1b148712-b2ee-43d8-9e5e-7fa454ee8a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048050041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1048050041
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.950722736
Short name T138
Test name
Test status
Simulation time 28641849 ps
CPU time 0.66 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:39 PM PDT 24
Peak memory 204024 kb
Host smart-56754585-2ae3-4826-9339-294d891d9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950722736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.950722736
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1613266571
Short name T761
Test name
Test status
Simulation time 73024141390 ps
CPU time 754.83 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:58:26 PM PDT 24
Peak memory 212676 kb
Host smart-9397d21a-63e0-42f5-a56f-c8f0fb6515bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613266571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1613266571
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1382123929
Short name T1000
Test name
Test status
Simulation time 4095778576 ps
CPU time 17.92 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:46:05 PM PDT 24
Peak memory 294116 kb
Host smart-754953a4-2204-4aa9-9bf1-79f1c564a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382123929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1382123929
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3280797064
Short name T106
Test name
Test status
Simulation time 51452851924 ps
CPU time 1799.54 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 4909020 kb
Host smart-604c2d12-d7bc-4577-b6d1-e313c415c03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280797064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3280797064
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3630050054
Short name T131
Test name
Test status
Simulation time 460288982 ps
CPU time 20.62 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:46:02 PM PDT 24
Peak memory 212532 kb
Host smart-19ec0d64-9b39-4ed1-9bd5-32e60b8f7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630050054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3630050054
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.653646574
Short name T170
Test name
Test status
Simulation time 141010154 ps
CPU time 0.91 seconds
Started May 14 12:45:37 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 221372 kb
Host smart-d3fbfc43-0cd2-4ba9-9799-ab46cc2399aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653646574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.653646574
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3608548563
Short name T820
Test name
Test status
Simulation time 1122210373 ps
CPU time 5.15 seconds
Started May 14 12:45:42 PM PDT 24
Finished May 14 12:45:50 PM PDT 24
Peak memory 204460 kb
Host smart-af860740-021a-4b50-85ba-ebd53f1d27d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608548563 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3608548563
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3494963442
Short name T1339
Test name
Test status
Simulation time 10098597727 ps
CPU time 34.42 seconds
Started May 14 12:45:57 PM PDT 24
Finished May 14 12:46:32 PM PDT 24
Peak memory 354808 kb
Host smart-f2359229-2b69-4528-99a5-d9761ac2f277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494963442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3494963442
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.151057051
Short name T278
Test name
Test status
Simulation time 10561960469 ps
CPU time 9.93 seconds
Started May 14 12:45:35 PM PDT 24
Finished May 14 12:45:48 PM PDT 24
Peak memory 254308 kb
Host smart-11369c49-f5dc-466f-b2d1-82d4746ce403
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151057051 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.151057051
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1778790744
Short name T1205
Test name
Test status
Simulation time 1317076155 ps
CPU time 2.43 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:45:41 PM PDT 24
Peak memory 204356 kb
Host smart-5361a0da-e0f9-4cfb-ad62-8dd42e4cc783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778790744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1778790744
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3704863763
Short name T701
Test name
Test status
Simulation time 15164488599 ps
CPU time 6.22 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:45:55 PM PDT 24
Peak memory 215900 kb
Host smart-eba6ff1a-aae4-4697-a490-b378964a540d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704863763 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3704863763
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2303971185
Short name T1081
Test name
Test status
Simulation time 11058992118 ps
CPU time 61.01 seconds
Started May 14 12:45:54 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 1077372 kb
Host smart-0e07dcfb-e2df-4cbe-acba-3bbf1d970788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303971185 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2303971185
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1709277802
Short name T864
Test name
Test status
Simulation time 968207725 ps
CPU time 14.12 seconds
Started May 14 12:45:38 PM PDT 24
Finished May 14 12:45:55 PM PDT 24
Peak memory 204404 kb
Host smart-dca0386d-55fd-466f-a0cc-192dba49f733
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709277802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1709277802
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3231502084
Short name T976
Test name
Test status
Simulation time 751896262 ps
CPU time 16.27 seconds
Started May 14 12:45:51 PM PDT 24
Finished May 14 12:46:08 PM PDT 24
Peak memory 204528 kb
Host smart-c9445d05-50eb-46d4-b5ef-6a98eb49f73f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231502084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3231502084
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1407643767
Short name T1321
Test name
Test status
Simulation time 59069646235 ps
CPU time 1693.35 seconds
Started May 14 12:45:46 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 9473444 kb
Host smart-fde82ede-dc07-437b-a595-c694f6e68361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407643767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1407643767
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3944704145
Short name T333
Test name
Test status
Simulation time 26392559637 ps
CPU time 503.87 seconds
Started May 14 12:45:50 PM PDT 24
Finished May 14 12:54:15 PM PDT 24
Peak memory 1527356 kb
Host smart-6288b2ee-597c-43b8-b108-af523d5289bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944704145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3944704145
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1169211681
Short name T523
Test name
Test status
Simulation time 1266292718 ps
CPU time 7.48 seconds
Started May 14 12:45:53 PM PDT 24
Finished May 14 12:46:01 PM PDT 24
Peak memory 219564 kb
Host smart-fb9ead4c-4d57-4380-a9d1-9a29f0b053cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169211681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1169211681
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.4273861927
Short name T1279
Test name
Test status
Simulation time 17592109 ps
CPU time 0.6 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:48:52 PM PDT 24
Peak memory 204180 kb
Host smart-afe6d08f-ed8a-44ae-b1d5-6c68b27af016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273861927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.4273861927
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3018507753
Short name T1109
Test name
Test status
Simulation time 36851879 ps
CPU time 1.22 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:48:52 PM PDT 24
Peak memory 212820 kb
Host smart-71dbad74-59d5-43d2-ac77-38ba328525af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018507753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3018507753
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4014905149
Short name T1282
Test name
Test status
Simulation time 663857053 ps
CPU time 4.06 seconds
Started May 14 12:48:43 PM PDT 24
Finished May 14 12:48:48 PM PDT 24
Peak memory 237408 kb
Host smart-8a3ffc98-04cd-4b37-bcae-a5efa5235895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014905149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.4014905149
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2952161333
Short name T1319
Test name
Test status
Simulation time 1648228227 ps
CPU time 48.51 seconds
Started May 14 12:48:43 PM PDT 24
Finished May 14 12:49:32 PM PDT 24
Peak memory 602892 kb
Host smart-96e5b5b1-5212-469f-a2ba-a66dc326c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952161333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2952161333
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.113975536
Short name T424
Test name
Test status
Simulation time 3882070229 ps
CPU time 58.92 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:49:52 PM PDT 24
Peak memory 688656 kb
Host smart-ca9b500d-5fe7-4e2f-aaad-9be784f0d857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113975536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.113975536
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2476389758
Short name T538
Test name
Test status
Simulation time 440494326 ps
CPU time 0.98 seconds
Started May 14 12:48:43 PM PDT 24
Finished May 14 12:48:45 PM PDT 24
Peak memory 204124 kb
Host smart-fde2a34e-076c-4961-8c3f-360258d52eac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476389758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2476389758
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.297188926
Short name T1010
Test name
Test status
Simulation time 130826099 ps
CPU time 3.32 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:48:53 PM PDT 24
Peak memory 225608 kb
Host smart-58ebb6d0-6353-4d7a-9de2-9c67d76cf1cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297188926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
297188926
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1724846577
Short name T418
Test name
Test status
Simulation time 13799975543 ps
CPU time 216.04 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:52:27 PM PDT 24
Peak memory 961000 kb
Host smart-be990b82-b32b-4a05-a0b7-0695c1479df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724846577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1724846577
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.422166814
Short name T1159
Test name
Test status
Simulation time 2249440626 ps
CPU time 8.8 seconds
Started May 14 12:48:48 PM PDT 24
Finished May 14 12:48:58 PM PDT 24
Peak memory 204380 kb
Host smart-0c70dac6-18d0-4786-99cf-7613a3182420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422166814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.422166814
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3435356875
Short name T1226
Test name
Test status
Simulation time 14096079583 ps
CPU time 18.7 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 279672 kb
Host smart-63faeb4e-13a4-48ec-a3a8-c50d111b3e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435356875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3435356875
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3236741403
Short name T645
Test name
Test status
Simulation time 19742280 ps
CPU time 0.65 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:48:54 PM PDT 24
Peak memory 204048 kb
Host smart-9ba6a6bb-4e5a-4ca8-86d4-0e1472f58571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236741403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3236741403
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1202206085
Short name T917
Test name
Test status
Simulation time 30697887061 ps
CPU time 173.21 seconds
Started May 14 12:48:47 PM PDT 24
Finished May 14 12:51:41 PM PDT 24
Peak memory 291152 kb
Host smart-0c5511e0-92fc-45fd-b4c5-4e87ec1f8260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202206085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1202206085
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1946116000
Short name T1265
Test name
Test status
Simulation time 5235464475 ps
CPU time 27 seconds
Started May 14 12:48:46 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 334404 kb
Host smart-d95e34b7-e714-41c1-9289-a6d7441b57a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946116000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1946116000
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1815581511
Short name T868
Test name
Test status
Simulation time 10697185888 ps
CPU time 1682.35 seconds
Started May 14 12:48:48 PM PDT 24
Finished May 14 01:16:52 PM PDT 24
Peak memory 2842528 kb
Host smart-0a6215a0-4ad5-4a98-92ae-fb9ae77c8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815581511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1815581511
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.323365242
Short name T148
Test name
Test status
Simulation time 512431640 ps
CPU time 23.69 seconds
Started May 14 12:48:47 PM PDT 24
Finished May 14 12:49:12 PM PDT 24
Peak memory 212656 kb
Host smart-19fb6d6f-a8fc-4773-a0e7-7f3c35c09925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323365242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.323365242
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3720513201
Short name T28
Test name
Test status
Simulation time 1176012338 ps
CPU time 4.97 seconds
Started May 14 12:48:44 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 212660 kb
Host smart-6409a4ba-56fc-4fe9-a5ca-2d9aa5c91263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720513201 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3720513201
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3787501688
Short name T953
Test name
Test status
Simulation time 10236945942 ps
CPU time 17.07 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:49:12 PM PDT 24
Peak memory 260408 kb
Host smart-4ffe506a-e91a-423a-9542-766b6ae4d373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787501688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3787501688
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1567162750
Short name T67
Test name
Test status
Simulation time 10147368377 ps
CPU time 41.43 seconds
Started May 14 12:48:44 PM PDT 24
Finished May 14 12:49:26 PM PDT 24
Peak memory 375980 kb
Host smart-2f4fdef4-13d2-45b3-814d-2091acb4cb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567162750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1567162750
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2762988303
Short name T26
Test name
Test status
Simulation time 461327642 ps
CPU time 2.69 seconds
Started May 14 12:48:45 PM PDT 24
Finished May 14 12:48:49 PM PDT 24
Peak memory 204372 kb
Host smart-47cb3386-82f3-4b93-9621-83f12e1c809f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762988303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2762988303
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3349881768
Short name T807
Test name
Test status
Simulation time 2883055306 ps
CPU time 4.09 seconds
Started May 14 12:48:43 PM PDT 24
Finished May 14 12:48:48 PM PDT 24
Peak memory 204460 kb
Host smart-9e31b758-f92e-406c-88a3-0d838bb69342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349881768 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3349881768
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2587306600
Short name T313
Test name
Test status
Simulation time 20672828462 ps
CPU time 23.06 seconds
Started May 14 12:48:46 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 646572 kb
Host smart-2679c136-4f87-4341-ba9a-f5b929ace582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587306600 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2587306600
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.231156064
Short name T329
Test name
Test status
Simulation time 1022454725 ps
CPU time 16.95 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:49:07 PM PDT 24
Peak memory 204236 kb
Host smart-695152e4-c97f-4810-837c-a1ca38e24976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231156064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.231156064
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3215399359
Short name T1311
Test name
Test status
Simulation time 475942372 ps
CPU time 20.26 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:49:11 PM PDT 24
Peak memory 204456 kb
Host smart-423ef413-3aa8-45a7-8db2-fe7d7238258e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215399359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3215399359
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3556766714
Short name T443
Test name
Test status
Simulation time 40348525243 ps
CPU time 605.17 seconds
Started May 14 12:48:48 PM PDT 24
Finished May 14 12:58:54 PM PDT 24
Peak memory 4965880 kb
Host smart-1ec4eb96-3de6-47ec-8f6d-0b671ed592a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556766714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3556766714
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2751643931
Short name T464
Test name
Test status
Simulation time 2570204948 ps
CPU time 7.08 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:48:57 PM PDT 24
Peak memory 217220 kb
Host smart-982153ca-58d1-4b58-9828-3c021b1b59e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751643931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2751643931
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.836073170
Short name T657
Test name
Test status
Simulation time 18192755 ps
CPU time 0.63 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:48:55 PM PDT 24
Peak memory 204068 kb
Host smart-bef488b5-843b-495d-9271-cab2cd06ae76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836073170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.836073170
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3419763269
Short name T844
Test name
Test status
Simulation time 208331220 ps
CPU time 1.35 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:48:56 PM PDT 24
Peak memory 212740 kb
Host smart-120a38af-e89e-4b35-a393-c6e4ce068344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419763269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3419763269
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2181514660
Short name T351
Test name
Test status
Simulation time 323489190 ps
CPU time 5.83 seconds
Started May 14 12:48:45 PM PDT 24
Finished May 14 12:48:52 PM PDT 24
Peak memory 258928 kb
Host smart-767f4c02-5402-4d9b-a036-ddf4ad5f25f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181514660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2181514660
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2377096790
Short name T1053
Test name
Test status
Simulation time 1479745970 ps
CPU time 98.49 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:50:33 PM PDT 24
Peak memory 549724 kb
Host smart-a6b35aad-aeac-4468-89c4-0a29e7f1d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377096790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2377096790
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3650856965
Short name T561
Test name
Test status
Simulation time 25705392709 ps
CPU time 63.02 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:49:55 PM PDT 24
Peak memory 654012 kb
Host smart-17d772f4-322b-4f23-a669-a4de5fca8443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650856965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3650856965
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.459902078
Short name T1114
Test name
Test status
Simulation time 527836217 ps
CPU time 1.26 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:48:54 PM PDT 24
Peak memory 204464 kb
Host smart-5bd93751-e8f5-4354-a7b0-747b838c8913
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459902078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.459902078
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1885321251
Short name T1305
Test name
Test status
Simulation time 1536398704 ps
CPU time 4.09 seconds
Started May 14 12:48:44 PM PDT 24
Finished May 14 12:48:50 PM PDT 24
Peak memory 204404 kb
Host smart-af6e699c-b15d-457d-8fb3-d68690e2f4b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885321251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1885321251
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.235063936
Short name T906
Test name
Test status
Simulation time 19530130338 ps
CPU time 117.59 seconds
Started May 14 12:48:50 PM PDT 24
Finished May 14 12:50:50 PM PDT 24
Peak memory 1297836 kb
Host smart-dceae413-d4e7-4e42-9834-b24c45af7bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235063936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.235063936
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3387618979
Short name T640
Test name
Test status
Simulation time 5968422946 ps
CPU time 7.22 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 204372 kb
Host smart-f9e7be03-a363-40de-91e3-e5e1db1a0448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387618979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3387618979
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.2146185078
Short name T576
Test name
Test status
Simulation time 47193889 ps
CPU time 0.66 seconds
Started May 14 12:48:44 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 204148 kb
Host smart-11112cfa-fa13-4b68-b971-72f72d2fba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146185078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2146185078
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3050951726
Short name T484
Test name
Test status
Simulation time 4944901333 ps
CPU time 195.64 seconds
Started May 14 12:48:44 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 226576 kb
Host smart-dd2fef5d-c193-44a0-9788-c7a6bcb322a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050951726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3050951726
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3515764252
Short name T983
Test name
Test status
Simulation time 5028476576 ps
CPU time 59.53 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:49:50 PM PDT 24
Peak memory 310688 kb
Host smart-51468b65-55cf-4ae8-96b4-7cd93939463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515764252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3515764252
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.23887210
Short name T347
Test name
Test status
Simulation time 743511391 ps
CPU time 12.43 seconds
Started May 14 12:48:49 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 220700 kb
Host smart-3513f686-288e-4ab8-a7a2-fa19aa4def29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23887210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.23887210
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3456731180
Short name T712
Test name
Test status
Simulation time 1899029531 ps
CPU time 4.62 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:49:00 PM PDT 24
Peak memory 204284 kb
Host smart-d52576a7-ca8e-4f07-9fda-0031d4e0b7f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456731180 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3456731180
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.4170998551
Short name T410
Test name
Test status
Simulation time 10159533774 ps
CPU time 14.06 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:12 PM PDT 24
Peak memory 253692 kb
Host smart-309838dc-2160-423c-b075-dd28c1cfe8af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170998551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.4170998551
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.355475931
Short name T1264
Test name
Test status
Simulation time 10045898156 ps
CPU time 82.11 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:50:19 PM PDT 24
Peak memory 560140 kb
Host smart-93bdd142-986c-4814-a8d8-36e75fb88d1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355475931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.355475931
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1230446859
Short name T887
Test name
Test status
Simulation time 364775135 ps
CPU time 2.19 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:00 PM PDT 24
Peak memory 204360 kb
Host smart-415f3469-39f8-4de4-b935-c1ac9cb557e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230446859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1230446859
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3185592057
Short name T1006
Test name
Test status
Simulation time 8449903042 ps
CPU time 7.5 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:05 PM PDT 24
Peak memory 204328 kb
Host smart-a9e06d73-97ac-4970-93aa-93922917dd93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185592057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3185592057
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2788966956
Short name T780
Test name
Test status
Simulation time 12760231874 ps
CPU time 79.37 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:50:15 PM PDT 24
Peak memory 1318628 kb
Host smart-0e1bd1f3-3ab5-4d5b-8464-b852e0358561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788966956 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2788966956
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2276258440
Short name T896
Test name
Test status
Simulation time 963980304 ps
CPU time 37.91 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:35 PM PDT 24
Peak memory 204348 kb
Host smart-0bfa933d-390c-4c2b-948f-8645b4658a1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276258440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2276258440
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.177537947
Short name T894
Test name
Test status
Simulation time 3487379306 ps
CPU time 9.7 seconds
Started May 14 12:48:53 PM PDT 24
Finished May 14 12:49:06 PM PDT 24
Peak memory 210468 kb
Host smart-5c6878da-9e27-4722-87fa-1985bc393354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177537947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.177537947
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.984941221
Short name T587
Test name
Test status
Simulation time 44989516387 ps
CPU time 130.49 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:51:06 PM PDT 24
Peak memory 1691136 kb
Host smart-e2ffd425-65fc-4cff-8e34-5ba0aa732342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984941221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.984941221
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3439449627
Short name T232
Test name
Test status
Simulation time 33361206304 ps
CPU time 714.33 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 01:01:05 PM PDT 24
Peak memory 3973632 kb
Host smart-1a48c31e-e74d-4d73-9bc7-45748ace1f76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439449627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3439449627
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2031508152
Short name T458
Test name
Test status
Simulation time 5143342337 ps
CPU time 7.47 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 220780 kb
Host smart-b4442473-fe2d-41ee-8a0f-f720e473d2da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031508152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2031508152
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.997836227
Short name T842
Test name
Test status
Simulation time 38180174 ps
CPU time 0.59 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 204180 kb
Host smart-3ad200ee-16d9-4dff-b182-b9ba5aa80998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997836227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.997836227
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3801606516
Short name T1190
Test name
Test status
Simulation time 63020049 ps
CPU time 1.28 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:48:59 PM PDT 24
Peak memory 212568 kb
Host smart-2bde6fe7-433d-4a35-a335-91955ef2df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801606516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3801606516
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3782682669
Short name T1060
Test name
Test status
Simulation time 2139606340 ps
CPU time 12.79 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 243564 kb
Host smart-e9595538-d998-4ccc-b381-22b6b6bde5c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782682669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3782682669
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2010284245
Short name T1341
Test name
Test status
Simulation time 3278453429 ps
CPU time 50.5 seconds
Started May 14 12:48:56 PM PDT 24
Finished May 14 12:49:49 PM PDT 24
Peak memory 573276 kb
Host smart-1183a570-9015-46ff-891b-b4941ba32c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010284245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2010284245
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1559260792
Short name T813
Test name
Test status
Simulation time 1786594345 ps
CPU time 60.83 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:49:57 PM PDT 24
Peak memory 637232 kb
Host smart-5ea0de51-273f-4f1f-8f8f-d974f7bbb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559260792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1559260792
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2636143770
Short name T217
Test name
Test status
Simulation time 104446085 ps
CPU time 1.2 seconds
Started May 14 12:48:59 PM PDT 24
Finished May 14 12:49:02 PM PDT 24
Peak memory 204156 kb
Host smart-bc389e28-01b9-4f58-9a4b-19e419239dd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636143770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2636143770
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1749178485
Short name T1281
Test name
Test status
Simulation time 367056637 ps
CPU time 4.56 seconds
Started May 14 12:48:53 PM PDT 24
Finished May 14 12:49:01 PM PDT 24
Peak memory 204420 kb
Host smart-284f6285-8ea9-45ef-a5ac-ecd67c85453f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749178485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1749178485
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.396507619
Short name T86
Test name
Test status
Simulation time 2557812066 ps
CPU time 66.17 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:50:01 PM PDT 24
Peak memory 818520 kb
Host smart-8c3097a6-835c-4fcd-9c69-676cec3337f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396507619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.396507619
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2005576078
Short name T812
Test name
Test status
Simulation time 741810491 ps
CPU time 4.88 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:11 PM PDT 24
Peak memory 204416 kb
Host smart-01c5408f-002a-4929-a08c-a86d65d22077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005576078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2005576078
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.936399945
Short name T85
Test name
Test status
Simulation time 951562585 ps
CPU time 15.34 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:20 PM PDT 24
Peak memory 306744 kb
Host smart-5ba66cb8-d322-4ef4-b932-f81e73c4ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936399945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.936399945
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2911403012
Short name T919
Test name
Test status
Simulation time 58012176 ps
CPU time 0.65 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:48:55 PM PDT 24
Peak memory 204048 kb
Host smart-3bdeeb35-98f2-40ae-a341-1b44658a6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911403012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2911403012
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2098041791
Short name T518
Test name
Test status
Simulation time 1041110445 ps
CPU time 15.58 seconds
Started May 14 12:48:55 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 263484 kb
Host smart-a8be4d43-2959-49b4-8661-f80a05f24041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098041791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2098041791
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4207342011
Short name T689
Test name
Test status
Simulation time 1708468173 ps
CPU time 93.15 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:50:27 PM PDT 24
Peak memory 445316 kb
Host smart-d73153dc-7b5f-4455-80b0-feee59e100fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207342011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4207342011
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1071759866
Short name T629
Test name
Test status
Simulation time 982403605 ps
CPU time 10.82 seconds
Started May 14 12:48:51 PM PDT 24
Finished May 14 12:49:06 PM PDT 24
Peak memory 219560 kb
Host smart-fa39fed8-eace-4bdc-b268-df2df7e51d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071759866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1071759866
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1707373325
Short name T856
Test name
Test status
Simulation time 1176938270 ps
CPU time 5.36 seconds
Started May 14 12:48:59 PM PDT 24
Finished May 14 12:49:05 PM PDT 24
Peak memory 212616 kb
Host smart-1c8990d9-e32b-4f26-9817-bad49974913e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707373325 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1707373325
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1118867261
Short name T877
Test name
Test status
Simulation time 10127277298 ps
CPU time 27.88 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:33 PM PDT 24
Peak memory 334656 kb
Host smart-2817dd62-23c5-43ae-affa-bade5ba04459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118867261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1118867261
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.813616924
Short name T865
Test name
Test status
Simulation time 10377945065 ps
CPU time 15.85 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:20 PM PDT 24
Peak memory 301756 kb
Host smart-cc158d1f-6dcc-4a3e-8ccd-eeaa33d2d66e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813616924 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.813616924
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.969770687
Short name T1122
Test name
Test status
Simulation time 6999721893 ps
CPU time 2.85 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:04 PM PDT 24
Peak memory 204468 kb
Host smart-e595dfe0-1ba3-4b44-82cb-e3c50141a04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969770687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.969770687
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2411441062
Short name T968
Test name
Test status
Simulation time 2535276865 ps
CPU time 7.11 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:04 PM PDT 24
Peak memory 212684 kb
Host smart-670c2b79-5ac0-4909-b18d-59b4ff0df150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411441062 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2411441062
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2651019155
Short name T643
Test name
Test status
Simulation time 20141424208 ps
CPU time 13.91 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:12 PM PDT 24
Peak memory 340488 kb
Host smart-80135d6a-2a43-4452-b32f-eb25b07dd761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651019155 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2651019155
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.710365110
Short name T298
Test name
Test status
Simulation time 1841395105 ps
CPU time 7.18 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:49:05 PM PDT 24
Peak memory 204392 kb
Host smart-4652e24e-ad23-4d54-bfd0-752160ba2fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710365110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.710365110
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2579923376
Short name T903
Test name
Test status
Simulation time 7706909883 ps
CPU time 77.47 seconds
Started May 14 12:48:54 PM PDT 24
Finished May 14 12:50:15 PM PDT 24
Peak memory 209664 kb
Host smart-32e7191f-3aec-4f80-a3b8-e54ba91da8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579923376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2579923376
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3958744023
Short name T1208
Test name
Test status
Simulation time 32720373459 ps
CPU time 279.8 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:53:35 PM PDT 24
Peak memory 3085940 kb
Host smart-9f2d94a7-7ed6-4075-be28-9a6540012176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958744023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3958744023
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.768713253
Short name T531
Test name
Test status
Simulation time 19135351980 ps
CPU time 312.57 seconds
Started May 14 12:48:52 PM PDT 24
Finished May 14 12:54:08 PM PDT 24
Peak memory 2324424 kb
Host smart-c83277f8-efc3-4a66-adba-6f77c48f7f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768713253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.768713253
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.890407502
Short name T452
Test name
Test status
Simulation time 7207347313 ps
CPU time 6.6 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 212648 kb
Host smart-4ccb1900-509f-4ad2-8e8f-48802fe6f3ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890407502 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.890407502
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1490582925
Short name T167
Test name
Test status
Simulation time 23434978 ps
CPU time 0.62 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:01 PM PDT 24
Peak memory 204204 kb
Host smart-4381c8d4-2ec3-40a5-8688-8d24443b1294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490582925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1490582925
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1905152253
Short name T1180
Test name
Test status
Simulation time 104423231 ps
CPU time 1.64 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 221164 kb
Host smart-643a1457-6be9-4fa3-8e70-a904db9851e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905152253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1905152253
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2618315406
Short name T485
Test name
Test status
Simulation time 256144560 ps
CPU time 4.55 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 251452 kb
Host smart-f7adeb99-22b1-4d10-80b6-11d9ac37d083
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618315406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2618315406
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.2495995788
Short name T152
Test name
Test status
Simulation time 42472850680 ps
CPU time 77.1 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:50:18 PM PDT 24
Peak memory 732740 kb
Host smart-0fe5d336-19a4-4648-b4df-cda5fe6b392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495995788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2495995788
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1863403185
Short name T369
Test name
Test status
Simulation time 4158851673 ps
CPU time 72.77 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:50:18 PM PDT 24
Peak memory 691368 kb
Host smart-c3d905c8-7f15-47db-8b99-e849bb982d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863403185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1863403185
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.849256380
Short name T263
Test name
Test status
Simulation time 457413245 ps
CPU time 0.93 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:02 PM PDT 24
Peak memory 204132 kb
Host smart-0173c74a-243f-40ae-af8f-4e76a7848341
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849256380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.849256380
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2210739960
Short name T1246
Test name
Test status
Simulation time 423060167 ps
CPU time 2.94 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 204388 kb
Host smart-e66b1e01-62e8-4b2f-9503-4b2e619d9909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210739960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2210739960
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.4046865590
Short name T886
Test name
Test status
Simulation time 17443113912 ps
CPU time 153.99 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:51:39 PM PDT 24
Peak memory 1332272 kb
Host smart-55890ca2-e937-45ab-b4bd-b6669b8b5378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046865590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.4046865590
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2024253149
Short name T1290
Test name
Test status
Simulation time 578036586 ps
CPU time 23.21 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 204484 kb
Host smart-e1aac149-71f0-4813-bb0c-97cab40d3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024253149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2024253149
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1015227968
Short name T729
Test name
Test status
Simulation time 1966598365 ps
CPU time 17.79 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:19 PM PDT 24
Peak memory 253300 kb
Host smart-049f6a2d-c143-4862-a5e4-01611e9fb702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015227968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1015227968
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1027458067
Short name T686
Test name
Test status
Simulation time 28824858 ps
CPU time 0.64 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:03 PM PDT 24
Peak memory 204068 kb
Host smart-723a5264-d110-4aea-8ab0-c6c07b997f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027458067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1027458067
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.555999132
Short name T699
Test name
Test status
Simulation time 12113219447 ps
CPU time 44.13 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:48 PM PDT 24
Peak memory 505028 kb
Host smart-8cced978-a84a-4c98-9898-3abad0983bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555999132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.555999132
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2665370927
Short name T309
Test name
Test status
Simulation time 1406779668 ps
CPU time 27.18 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 301968 kb
Host smart-6b16c00d-16f7-4d59-8fde-f2ac3296c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665370927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2665370927
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3542093064
Short name T1054
Test name
Test status
Simulation time 665754070 ps
CPU time 11.3 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 228908 kb
Host smart-0ec5966a-7b4c-4486-9088-61c5e1a4608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542093064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3542093064
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1704987141
Short name T892
Test name
Test status
Simulation time 2807172391 ps
CPU time 4.08 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:09 PM PDT 24
Peak memory 212712 kb
Host smart-16472bd6-46a5-4b6f-8140-04b788957263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704987141 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1704987141
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.4101245303
Short name T297
Test name
Test status
Simulation time 10277376371 ps
CPU time 30.58 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:49:40 PM PDT 24
Peak memory 372816 kb
Host smart-f0f85000-c983-430f-8e33-5bee40659040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101245303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.4101245303
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2946452861
Short name T646
Test name
Test status
Simulation time 10100343901 ps
CPU time 12.32 seconds
Started May 14 12:49:04 PM PDT 24
Finished May 14 12:49:19 PM PDT 24
Peak memory 283968 kb
Host smart-6700bdb3-7286-491c-ba3f-a3476de07852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946452861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2946452861
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.520229190
Short name T134
Test name
Test status
Simulation time 2058021850 ps
CPU time 2.72 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:04 PM PDT 24
Peak memory 204404 kb
Host smart-185d3286-e7c2-400d-b61e-0bd8f58556ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520229190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.520229190
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1486074629
Short name T426
Test name
Test status
Simulation time 2235388199 ps
CPU time 3.3 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:06 PM PDT 24
Peak memory 204524 kb
Host smart-c60f35fd-b246-4b61-8ca2-1549119a448b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486074629 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1486074629
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1975924373
Short name T1181
Test name
Test status
Simulation time 10329680587 ps
CPU time 21.14 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:49:28 PM PDT 24
Peak memory 689440 kb
Host smart-26415226-f377-476c-952f-c48553055dda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975924373 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1975924373
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2380095583
Short name T705
Test name
Test status
Simulation time 2299076056 ps
CPU time 9.6 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:12 PM PDT 24
Peak memory 204432 kb
Host smart-20931bb3-c8aa-40c5-9d49-34be12472804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380095583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2380095583
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.55779333
Short name T373
Test name
Test status
Simulation time 2680700211 ps
CPU time 28.57 seconds
Started May 14 12:49:01 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 204516 kb
Host smart-033d0ec3-f482-4235-ba0b-b99267e6ba40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55779333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stress_rd.55779333
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2510073898
Short name T371
Test name
Test status
Simulation time 31425472354 ps
CPU time 6.82 seconds
Started May 14 12:49:00 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 204364 kb
Host smart-c70d6891-efb8-464f-b491-8eb027a4821d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510073898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2510073898
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1568257878
Short name T447
Test name
Test status
Simulation time 6679878878 ps
CPU time 152.93 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:51:39 PM PDT 24
Peak memory 1757292 kb
Host smart-0a623ae3-a54c-4903-9e9c-05e0630053fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568257878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1568257878
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1171011762
Short name T566
Test name
Test status
Simulation time 2212182146 ps
CPU time 7.85 seconds
Started May 14 12:49:04 PM PDT 24
Finished May 14 12:49:16 PM PDT 24
Peak memory 210820 kb
Host smart-acff4bcb-8df9-4c62-8500-df2975c6c73e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171011762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1171011762
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2941642022
Short name T513
Test name
Test status
Simulation time 17628660 ps
CPU time 0.62 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 204024 kb
Host smart-aca93fb8-88ad-46cb-90f3-370916f2ef8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941642022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2941642022
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2123137544
Short name T527
Test name
Test status
Simulation time 178744350 ps
CPU time 1.28 seconds
Started May 14 12:49:10 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 212624 kb
Host smart-96acd4da-2849-4960-a497-90542fcdef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123137544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2123137544
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.76334061
Short name T637
Test name
Test status
Simulation time 1867268014 ps
CPU time 25.05 seconds
Started May 14 12:49:17 PM PDT 24
Finished May 14 12:49:44 PM PDT 24
Peak memory 285996 kb
Host smart-d0016b1e-f62e-44ee-88dd-1a82f69230d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76334061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty
.76334061
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2239487894
Short name T282
Test name
Test status
Simulation time 2560234091 ps
CPU time 180.34 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:52:10 PM PDT 24
Peak memory 751496 kb
Host smart-4f0ca38e-c3e5-4e02-847a-498880bca604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239487894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2239487894
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.71414480
Short name T308
Test name
Test status
Simulation time 4563188782 ps
CPU time 65.37 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:50:12 PM PDT 24
Peak memory 685856 kb
Host smart-88f41655-9918-4f82-bdf0-c52c0d803c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71414480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.71414480
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2761797321
Short name T288
Test name
Test status
Simulation time 234330968 ps
CPU time 0.88 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:09 PM PDT 24
Peak memory 204428 kb
Host smart-a038c681-63b9-42cd-aab8-f61618b0c4b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761797321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2761797321
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1798564610
Short name T551
Test name
Test status
Simulation time 603908241 ps
CPU time 3.19 seconds
Started May 14 12:49:04 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 204480 kb
Host smart-d63182ac-956d-43d8-9738-b5717b2edb85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798564610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1798564610
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1551868218
Short name T1197
Test name
Test status
Simulation time 3644697141 ps
CPU time 255.24 seconds
Started May 14 12:49:03 PM PDT 24
Finished May 14 12:53:22 PM PDT 24
Peak memory 1039196 kb
Host smart-c9742346-5411-45cc-a98b-a5d4e127aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551868218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1551868218
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1332443668
Short name T75
Test name
Test status
Simulation time 577819136 ps
CPU time 23.46 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:49:33 PM PDT 24
Peak memory 204680 kb
Host smart-46b9edfe-ec21-4922-9504-ae95921664f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332443668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1332443668
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2383916481
Short name T510
Test name
Test status
Simulation time 1614260749 ps
CPU time 23.76 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 277548 kb
Host smart-d226660d-b14c-4a70-bedd-7568ab9eb657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383916481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2383916481
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3384449611
Short name T279
Test name
Test status
Simulation time 16613341 ps
CPU time 0.65 seconds
Started May 14 12:49:04 PM PDT 24
Finished May 14 12:49:08 PM PDT 24
Peak memory 204208 kb
Host smart-4fadd8bf-4e91-47a1-840a-01a18af1e784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384449611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3384449611
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2304586169
Short name T1160
Test name
Test status
Simulation time 7073106449 ps
CPU time 39.74 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:49:49 PM PDT 24
Peak memory 582808 kb
Host smart-320101d1-9e26-4143-a567-ea12f81e7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304586169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2304586169
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2667406745
Short name T1171
Test name
Test status
Simulation time 5599536323 ps
CPU time 30.94 seconds
Started May 14 12:49:02 PM PDT 24
Finished May 14 12:49:35 PM PDT 24
Peak memory 434544 kb
Host smart-1b3bd1cd-c770-4009-a5cb-78a16f272a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667406745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2667406745
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3994088871
Short name T121
Test name
Test status
Simulation time 26905859232 ps
CPU time 158.23 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:51:58 PM PDT 24
Peak memory 679232 kb
Host smart-adf91001-871f-40e2-b4df-3c024154c9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994088871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3994088871
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2499201260
Short name T337
Test name
Test status
Simulation time 946251404 ps
CPU time 8.81 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 12:49:20 PM PDT 24
Peak memory 214092 kb
Host smart-77680887-c84a-4144-9d65-a39506d4725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499201260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2499201260
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1926948666
Short name T932
Test name
Test status
Simulation time 5264513529 ps
CPU time 4.47 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 204492 kb
Host smart-be6f015f-6298-42d3-b7ba-fead8fbfaae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926948666 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1926948666
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.183937746
Short name T1045
Test name
Test status
Simulation time 10082151380 ps
CPU time 51.06 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:50:00 PM PDT 24
Peak memory 373916 kb
Host smart-e38f2aa0-1698-44bf-8261-11b780ae273f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183937746 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.183937746
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1329484153
Short name T779
Test name
Test status
Simulation time 10020028504 ps
CPU time 75.91 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:50:26 PM PDT 24
Peak memory 469196 kb
Host smart-2e4ef4f7-ec00-4267-823b-c4baf4b4a5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329484153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1329484153
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2643743893
Short name T777
Test name
Test status
Simulation time 416016990 ps
CPU time 2.54 seconds
Started May 14 12:49:09 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 204412 kb
Host smart-d9211881-e872-466c-b1d5-540b2ca59e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643743893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2643743893
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.877559262
Short name T711
Test name
Test status
Simulation time 734209062 ps
CPU time 4.26 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:49:13 PM PDT 24
Peak memory 206116 kb
Host smart-4f229681-9e8e-43e2-b28d-479eb98ee306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877559262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.877559262
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1424629769
Short name T849
Test name
Test status
Simulation time 7145011702 ps
CPU time 74.17 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 1826260 kb
Host smart-afbe03d4-18ea-43e1-9d33-a7a0770df22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424629769 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1424629769
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.48248177
Short name T316
Test name
Test status
Simulation time 6936075861 ps
CPU time 19.24 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:49:28 PM PDT 24
Peak memory 204424 kb
Host smart-42c5da17-ac32-4900-aec9-e478e9c57cca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48248177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_targ
et_smoke.48248177
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2556034466
Short name T405
Test name
Test status
Simulation time 979536037 ps
CPU time 15.18 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:49:35 PM PDT 24
Peak memory 216680 kb
Host smart-4f90126a-416c-4a3b-9a13-35175b36a6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556034466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2556034466
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1003815907
Short name T992
Test name
Test status
Simulation time 30521811537 ps
CPU time 16.58 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 12:49:28 PM PDT 24
Peak memory 428928 kb
Host smart-15b82116-af10-4fce-9a8b-cc5bd7e91c2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003815907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1003815907
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1104893785
Short name T586
Test name
Test status
Simulation time 34221372928 ps
CPU time 266.87 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:53:36 PM PDT 24
Peak memory 1849664 kb
Host smart-6fba6ddc-1128-4968-9496-525503cd2da9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104893785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1104893785
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3891792113
Short name T1270
Test name
Test status
Simulation time 4411429756 ps
CPU time 6.17 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:15 PM PDT 24
Peak memory 212520 kb
Host smart-27a575cb-4150-421e-80d6-c878ae82a224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891792113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3891792113
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2778730930
Short name T614
Test name
Test status
Simulation time 46560949 ps
CPU time 0.63 seconds
Started May 14 12:49:16 PM PDT 24
Finished May 14 12:49:19 PM PDT 24
Peak memory 204048 kb
Host smart-46f1c618-fed4-4926-969e-52ea11e8b440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778730930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2778730930
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.915085577
Short name T1250
Test name
Test status
Simulation time 449807533 ps
CPU time 1.41 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:49:21 PM PDT 24
Peak memory 212720 kb
Host smart-7f44b567-972c-4955-b903-8e65c6a35ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915085577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.915085577
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2837071968
Short name T853
Test name
Test status
Simulation time 5494977926 ps
CPU time 5.55 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 12:49:16 PM PDT 24
Peak memory 263028 kb
Host smart-926e9712-52e9-4675-9dbc-316f6667d3d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837071968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2837071968
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3297424307
Short name T63
Test name
Test status
Simulation time 1439774585 ps
CPU time 81.77 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 12:50:33 PM PDT 24
Peak memory 414120 kb
Host smart-3057fd90-e063-4ab0-9e20-11aa95fcc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297424307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3297424307
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1807952158
Short name T1128
Test name
Test status
Simulation time 7145720547 ps
CPU time 121.38 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:51:10 PM PDT 24
Peak memory 599288 kb
Host smart-a1bef9fb-3334-48a2-8ced-9ac38d5be604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807952158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1807952158
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.4278463757
Short name T343
Test name
Test status
Simulation time 355407927 ps
CPU time 1.18 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:49:09 PM PDT 24
Peak memory 204336 kb
Host smart-96d9238f-58ca-419b-b4ef-c1bf4f27ba60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278463757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.4278463757
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1585465128
Short name T775
Test name
Test status
Simulation time 223472205 ps
CPU time 6.47 seconds
Started May 14 12:49:08 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 221696 kb
Host smart-60447368-0449-41b9-9803-4c890c46a930
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585465128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1585465128
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1216129447
Short name T436
Test name
Test status
Simulation time 73419586354 ps
CPU time 111.04 seconds
Started May 14 12:49:05 PM PDT 24
Finished May 14 12:50:59 PM PDT 24
Peak memory 1117384 kb
Host smart-8d18deff-327f-497a-bf2d-ade990973617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216129447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1216129447
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1697414491
Short name T776
Test name
Test status
Simulation time 779075824 ps
CPU time 11.14 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 204396 kb
Host smart-15bad538-c85c-49b7-942a-c2feacadea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697414491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1697414491
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.1206874227
Short name T1065
Test name
Test status
Simulation time 2027631178 ps
CPU time 49.8 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:50:10 PM PDT 24
Peak memory 491792 kb
Host smart-764ffa7b-005d-42b1-aa36-21c9924e0bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206874227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.1206874227
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1482536645
Short name T1034
Test name
Test status
Simulation time 51321194 ps
CPU time 0.65 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:49:11 PM PDT 24
Peak memory 204048 kb
Host smart-e68250b4-6b2f-4136-8beb-2cb129654725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482536645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1482536645
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.920486896
Short name T1164
Test name
Test status
Simulation time 12396527454 ps
CPU time 346.19 seconds
Started May 14 12:49:09 PM PDT 24
Finished May 14 12:54:58 PM PDT 24
Peak memory 1589972 kb
Host smart-2747ed16-41c2-47d9-aeae-4757e6399c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920486896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.920486896
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2317809138
Short name T981
Test name
Test status
Simulation time 4624116322 ps
CPU time 52.29 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:50:01 PM PDT 24
Peak memory 250964 kb
Host smart-598e75c4-5c66-4b92-aa58-85096fb7be62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317809138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2317809138
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.524750907
Short name T248
Test name
Test status
Simulation time 4101418857 ps
CPU time 350.6 seconds
Started May 14 12:49:07 PM PDT 24
Finished May 14 12:55:00 PM PDT 24
Peak memory 998276 kb
Host smart-9165893f-593a-4149-9024-03cc8f2bb55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524750907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.524750907
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4282199312
Short name T493
Test name
Test status
Simulation time 1605498076 ps
CPU time 7.16 seconds
Started May 14 12:49:18 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 212632 kb
Host smart-e9bd4d2b-1122-42e9-b710-4f28f518f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282199312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4282199312
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3083193701
Short name T673
Test name
Test status
Simulation time 1107274726 ps
CPU time 5.18 seconds
Started May 14 12:49:16 PM PDT 24
Finished May 14 12:49:24 PM PDT 24
Peak memory 212604 kb
Host smart-2197c556-aad6-4a18-811b-c326c86c64c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083193701 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3083193701
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.453482840
Short name T59
Test name
Test status
Simulation time 10043662998 ps
CPU time 71.9 seconds
Started May 14 12:49:13 PM PDT 24
Finished May 14 12:50:27 PM PDT 24
Peak memory 482256 kb
Host smart-9aa62d83-b9fe-42f6-8e9f-054686985256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453482840 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.453482840
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2722342825
Short name T897
Test name
Test status
Simulation time 10107853273 ps
CPU time 31.68 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:49:48 PM PDT 24
Peak memory 307300 kb
Host smart-1e469b27-8872-42cb-ab53-722474150f9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722342825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2722342825
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1022739732
Short name T789
Test name
Test status
Simulation time 594705624 ps
CPU time 2.3 seconds
Started May 14 12:49:13 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 204436 kb
Host smart-555d5284-0886-47e8-9916-e1fd0a78dfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022739732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1022739732
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1015362122
Short name T262
Test name
Test status
Simulation time 7486586057 ps
CPU time 6.98 seconds
Started May 14 12:49:15 PM PDT 24
Finished May 14 12:49:24 PM PDT 24
Peak memory 220736 kb
Host smart-12b85ab5-abdf-444b-8686-3d187d9a49f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015362122 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1015362122
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2946386535
Short name T593
Test name
Test status
Simulation time 28251931098 ps
CPU time 61.65 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:50:18 PM PDT 24
Peak memory 1182072 kb
Host smart-9b4d7b14-d14c-4c26-a7bc-e08e24adfa6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946386535 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2946386535
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.3644449909
Short name T1068
Test name
Test status
Simulation time 4314360681 ps
CPU time 12.82 seconds
Started May 14 12:49:11 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 204344 kb
Host smart-aafadd20-cedb-4762-84e5-8d186a94a71d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644449909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.3644449909
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1655263969
Short name T946
Test name
Test status
Simulation time 833899621 ps
CPU time 35.28 seconds
Started May 14 12:49:17 PM PDT 24
Finished May 14 12:49:54 PM PDT 24
Peak memory 204372 kb
Host smart-5371fe6c-9be8-4f8e-8dae-3cec669fe2f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655263969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1655263969
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.357896501
Short name T358
Test name
Test status
Simulation time 16269241634 ps
CPU time 4.77 seconds
Started May 14 12:49:06 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 204428 kb
Host smart-d51c5b72-ef06-4525-bb10-488a65d683d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357896501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.357896501
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1701583049
Short name T158
Test name
Test status
Simulation time 35082084250 ps
CPU time 3332.26 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 01:44:48 PM PDT 24
Peak memory 8051192 kb
Host smart-f1bed328-b665-46d7-80b6-e884db7f2b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701583049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1701583049
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.902867611
Short name T275
Test name
Test status
Simulation time 4467309275 ps
CPU time 6.96 seconds
Started May 14 12:49:13 PM PDT 24
Finished May 14 12:49:22 PM PDT 24
Peak memory 204488 kb
Host smart-c465b53c-0159-43ce-99cb-40589592c073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902867611 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.902867611
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3877154316
Short name T163
Test name
Test status
Simulation time 115021553 ps
CPU time 0.62 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 204024 kb
Host smart-7e0b6177-153e-4038-b838-55ad1626702a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877154316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3877154316
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.49231386
Short name T257
Test name
Test status
Simulation time 567596489 ps
CPU time 1.64 seconds
Started May 14 12:49:17 PM PDT 24
Finished May 14 12:49:21 PM PDT 24
Peak memory 212660 kb
Host smart-286f9dcd-623b-4cb0-9471-4a14057c78d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49231386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.49231386
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2870353085
Short name T760
Test name
Test status
Simulation time 283366978 ps
CPU time 14.65 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 246068 kb
Host smart-42991d3a-e4d8-4a51-a40c-dfd553f76590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870353085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2870353085
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.29719862
Short name T164
Test name
Test status
Simulation time 4932208963 ps
CPU time 80.9 seconds
Started May 14 12:49:12 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 500604 kb
Host smart-1ba041be-669a-475f-894c-752bb1d3ecc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29719862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.29719862
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3877422948
Short name T898
Test name
Test status
Simulation time 2983642946 ps
CPU time 40.07 seconds
Started May 14 12:49:16 PM PDT 24
Finished May 14 12:49:58 PM PDT 24
Peak memory 543188 kb
Host smart-bbf289f2-1eba-4691-bfb4-841d527dbc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877422948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3877422948
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3504000629
Short name T1261
Test name
Test status
Simulation time 409742503 ps
CPU time 1.01 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:49:17 PM PDT 24
Peak memory 204224 kb
Host smart-b05e1a6a-e073-436c-bc83-d23d8062e463
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504000629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3504000629
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2584354799
Short name T1183
Test name
Test status
Simulation time 354711127 ps
CPU time 5.34 seconds
Started May 14 12:49:16 PM PDT 24
Finished May 14 12:49:23 PM PDT 24
Peak memory 217200 kb
Host smart-04b4e0fb-b709-43d4-838e-96a042d068e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584354799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2584354799
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.659437832
Short name T349
Test name
Test status
Simulation time 14304781851 ps
CPU time 111.62 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:51:08 PM PDT 24
Peak memory 1069928 kb
Host smart-8bc68787-ccfb-4e01-bb1a-f880c7f1147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659437832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.659437832
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2929228873
Short name T972
Test name
Test status
Simulation time 222395314 ps
CPU time 9.02 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:32 PM PDT 24
Peak memory 204344 kb
Host smart-145d9986-480f-4050-b437-fa79096d433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929228873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2929228873
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.4010742270
Short name T1324
Test name
Test status
Simulation time 25831538 ps
CPU time 0.69 seconds
Started May 14 12:49:15 PM PDT 24
Finished May 14 12:49:18 PM PDT 24
Peak memory 204124 kb
Host smart-a7f24fcf-46ad-499d-981f-e96a2a3c24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010742270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.4010742270
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2433649535
Short name T1046
Test name
Test status
Simulation time 4710201427 ps
CPU time 17.43 seconds
Started May 14 12:49:13 PM PDT 24
Finished May 14 12:49:32 PM PDT 24
Peak memory 362392 kb
Host smart-add4750e-8111-4c9e-a69e-54f36598f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433649535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2433649535
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.316649301
Short name T289
Test name
Test status
Simulation time 3441982819 ps
CPU time 31.55 seconds
Started May 14 12:49:17 PM PDT 24
Finished May 14 12:49:51 PM PDT 24
Peak memory 372496 kb
Host smart-4e6784f5-f181-4803-bc18-ae411a0eb50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316649301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.316649301
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3623242143
Short name T848
Test name
Test status
Simulation time 395142869 ps
CPU time 7.25 seconds
Started May 14 12:49:14 PM PDT 24
Finished May 14 12:49:24 PM PDT 24
Peak memory 220792 kb
Host smart-1293fc45-4aa1-4f85-a5a0-50733e9c1601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623242143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3623242143
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.605362326
Short name T1237
Test name
Test status
Simulation time 747812238 ps
CPU time 3.32 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 204280 kb
Host smart-a30c82ba-03e5-4621-87e6-81e8017d63d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605362326 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.605362326
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2344562002
Short name T487
Test name
Test status
Simulation time 10152557644 ps
CPU time 28.34 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:50 PM PDT 24
Peak memory 358276 kb
Host smart-d8fa02cb-8c94-4dff-bbca-e483eea7784c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344562002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2344562002
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2745270525
Short name T661
Test name
Test status
Simulation time 10216756206 ps
CPU time 15.97 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:40 PM PDT 24
Peak memory 300900 kb
Host smart-1831f12e-481e-4751-b38b-59796645f10d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745270525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2745270525
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2768468235
Short name T784
Test name
Test status
Simulation time 2734215278 ps
CPU time 2.2 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:25 PM PDT 24
Peak memory 204472 kb
Host smart-b564b41a-346a-4b7d-b454-0b883b096930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768468235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2768468235
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2054597085
Short name T609
Test name
Test status
Simulation time 10413189944 ps
CPU time 7.75 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:30 PM PDT 24
Peak memory 211892 kb
Host smart-5909e383-2f04-45c6-b730-623559350415
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054597085 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2054597085
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2299259921
Short name T372
Test name
Test status
Simulation time 19834339405 ps
CPU time 474.34 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 4895268 kb
Host smart-d415e166-cf4a-432f-a919-4311f5ef5406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299259921 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2299259921
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1758367181
Short name T470
Test name
Test status
Simulation time 1296435112 ps
CPU time 47.51 seconds
Started May 14 12:49:16 PM PDT 24
Finished May 14 12:50:05 PM PDT 24
Peak memory 204476 kb
Host smart-d13c51f4-e1f4-4deb-b758-b6db5e026be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758367181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1758367181
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.924209212
Short name T1032
Test name
Test status
Simulation time 2759246430 ps
CPU time 9.54 seconds
Started May 14 12:49:15 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 209036 kb
Host smart-d41b2920-3cec-4975-8db0-2e04bbc73b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924209212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.924209212
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3451137568
Short name T1154
Test name
Test status
Simulation time 47984065587 ps
CPU time 54.34 seconds
Started May 14 12:49:12 PM PDT 24
Finished May 14 12:50:08 PM PDT 24
Peak memory 977628 kb
Host smart-ec9b4fa1-5b2a-4f0e-b33d-5736e5d17be7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451137568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3451137568
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3603395828
Short name T801
Test name
Test status
Simulation time 30725520284 ps
CPU time 1696.82 seconds
Started May 14 12:49:13 PM PDT 24
Finished May 14 01:17:33 PM PDT 24
Peak memory 6441148 kb
Host smart-e193a783-fe53-40fa-b578-c4d140d2cebd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603395828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3603395828
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3047992167
Short name T1255
Test name
Test status
Simulation time 5439429429 ps
CPU time 7.44 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:29 PM PDT 24
Peak memory 220748 kb
Host smart-8e9233b7-ffed-472f-81bc-4d4a6d886b0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047992167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3047992167
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.424308336
Short name T995
Test name
Test status
Simulation time 16526051 ps
CPU time 0.61 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:22 PM PDT 24
Peak memory 204140 kb
Host smart-5408f293-001c-48d6-9e2a-ec9b4c2c5631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424308336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.424308336
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2392574888
Short name T479
Test name
Test status
Simulation time 246884368 ps
CPU time 1.29 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:23 PM PDT 24
Peak memory 212688 kb
Host smart-e7a68ca8-2434-4cf4-8cd6-048630561209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392574888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2392574888
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3309639947
Short name T457
Test name
Test status
Simulation time 280648033 ps
CPU time 6 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:28 PM PDT 24
Peak memory 260480 kb
Host smart-3ab5e888-8f8b-4cae-8ce3-759ff8e090e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309639947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3309639947
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2470909161
Short name T1115
Test name
Test status
Simulation time 11386815355 ps
CPU time 63.42 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:50:27 PM PDT 24
Peak memory 688520 kb
Host smart-b6c73588-8166-41bd-a053-c264c73373b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470909161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2470909161
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3160664690
Short name T1300
Test name
Test status
Simulation time 10497341395 ps
CPU time 37.23 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:59 PM PDT 24
Peak memory 519156 kb
Host smart-40bedc2c-2928-4d39-ab7d-5b9cfe33e037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160664690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3160664690
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1578273534
Short name T306
Test name
Test status
Simulation time 90689050 ps
CPU time 1.04 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:49:26 PM PDT 24
Peak memory 204152 kb
Host smart-5dfaed6f-9b36-40ef-8c64-b5abb16c40a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578273534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1578273534
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1666051114
Short name T755
Test name
Test status
Simulation time 207489264 ps
CPU time 2.98 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 219716 kb
Host smart-766e8b00-170c-4c28-a634-937638485ac5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666051114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1666051114
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1437575559
Short name T1306
Test name
Test status
Simulation time 776649044 ps
CPU time 6.76 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 204464 kb
Host smart-385d5694-8a58-407b-a7cc-1a6927c715ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437575559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1437575559
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.248071427
Short name T73
Test name
Test status
Simulation time 4762559485 ps
CPU time 15.85 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:39 PM PDT 24
Peak memory 282240 kb
Host smart-7805b5a7-68f0-4c91-823d-f0cdadaf10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248071427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.248071427
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2752491872
Short name T444
Test name
Test status
Simulation time 16214132 ps
CPU time 0.72 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:23 PM PDT 24
Peak memory 204068 kb
Host smart-47f96401-60bb-491a-80c1-7094a7a1a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752491872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2752491872
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2432112713
Short name T516
Test name
Test status
Simulation time 7371621488 ps
CPU time 121.04 seconds
Started May 14 12:49:25 PM PDT 24
Finished May 14 12:51:27 PM PDT 24
Peak memory 652952 kb
Host smart-59c85b83-b8e9-4cd5-afe3-dae860c9c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432112713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2432112713
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2305608598
Short name T1048
Test name
Test status
Simulation time 1004886051 ps
CPU time 48.08 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:50:12 PM PDT 24
Peak memory 299904 kb
Host smart-2746d3ec-5f63-488e-8774-dd8d01bf805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305608598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2305608598
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.300683648
Short name T1132
Test name
Test status
Simulation time 73744438775 ps
CPU time 916.78 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 01:04:41 PM PDT 24
Peak memory 2921644 kb
Host smart-c64360f6-84b8-4387-8714-be2b4ff94c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300683648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.300683648
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1108887258
Short name T285
Test name
Test status
Simulation time 2877886644 ps
CPU time 11.96 seconds
Started May 14 12:49:19 PM PDT 24
Finished May 14 12:49:33 PM PDT 24
Peak memory 219692 kb
Host smart-5f9c9676-63be-4f46-88c7-185e983232f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108887258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1108887258
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3076701265
Short name T805
Test name
Test status
Simulation time 9052807478 ps
CPU time 3.11 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:26 PM PDT 24
Peak memory 204504 kb
Host smart-cfd2d64a-eb36-4f50-ab69-a77adcd3c776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076701265 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3076701265
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.4287372778
Short name T1108
Test name
Test status
Simulation time 10100599854 ps
CPU time 75.96 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:50:41 PM PDT 24
Peak memory 469964 kb
Host smart-66899344-5dec-4a60-8640-138697c1dece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287372778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.4287372778
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.172721260
Short name T771
Test name
Test status
Simulation time 10044536151 ps
CPU time 66.73 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:50:30 PM PDT 24
Peak memory 457336 kb
Host smart-922b7d15-ad13-4210-8add-c49431fe896b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172721260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.172721260
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2892942124
Short name T799
Test name
Test status
Simulation time 775513231 ps
CPU time 2.94 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 204368 kb
Host smart-46c3bfe6-52f4-4bff-9f61-e23359dc3157
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892942124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2892942124
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3401782995
Short name T620
Test name
Test status
Simulation time 1387823552 ps
CPU time 4.56 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:49:30 PM PDT 24
Peak memory 205184 kb
Host smart-46ff4e09-49fe-4110-b024-c4c6d8100975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401782995 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3401782995
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1378997758
Short name T901
Test name
Test status
Simulation time 3010218390 ps
CPU time 6.54 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:30 PM PDT 24
Peak memory 204468 kb
Host smart-b23a4f26-1f9f-430d-89d4-2e72852e6f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378997758 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1378997758
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1663295531
Short name T989
Test name
Test status
Simulation time 761734733 ps
CPU time 13.03 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:37 PM PDT 24
Peak memory 204428 kb
Host smart-a7826c90-ba89-419a-ae6b-bb9d241d339e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663295531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1663295531
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1298352584
Short name T688
Test name
Test status
Simulation time 1751085907 ps
CPU time 3.84 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:49:27 PM PDT 24
Peak memory 204372 kb
Host smart-cb66540e-f89c-4aca-a670-5052eb96625a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298352584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1298352584
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.822441360
Short name T411
Test name
Test status
Simulation time 15236593918 ps
CPU time 8.49 seconds
Started May 14 12:49:20 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 204504 kb
Host smart-63e78ad0-c859-477a-8646-7e8e042694f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822441360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.822441360
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1050752327
Short name T560
Test name
Test status
Simulation time 36256289776 ps
CPU time 96.22 seconds
Started May 14 12:49:21 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 860704 kb
Host smart-ed268f97-1cbc-474f-a7c5-4a999220d9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050752327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1050752327
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.119768270
Short name T954
Test name
Test status
Simulation time 1340752780 ps
CPU time 6.91 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 212576 kb
Host smart-d802fc79-b228-42ab-9977-aee064037ae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119768270 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.119768270
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.3302921721
Short name T1148
Test name
Test status
Simulation time 920251863 ps
CPU time 4.93 seconds
Started May 14 12:49:22 PM PDT 24
Finished May 14 12:49:29 PM PDT 24
Peak memory 204176 kb
Host smart-de6e9cfb-0d77-49a0-bd5c-e0d00041a857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302921721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.3302921721
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.719253245
Short name T947
Test name
Test status
Simulation time 58783210 ps
CPU time 0.65 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:31 PM PDT 24
Peak memory 204064 kb
Host smart-b3850979-fff3-4cf9-8db5-8f551d73829e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719253245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.719253245
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3049685731
Short name T582
Test name
Test status
Simulation time 848847111 ps
CPU time 1.35 seconds
Started May 14 12:49:27 PM PDT 24
Finished May 14 12:49:30 PM PDT 24
Peak memory 220936 kb
Host smart-cf0e4a09-68c6-4737-81fb-9d9e98686690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049685731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3049685731
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3810252138
Short name T302
Test name
Test status
Simulation time 1102957437 ps
CPU time 13.86 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:46 PM PDT 24
Peak memory 234460 kb
Host smart-a98dd95e-8405-433a-98a1-63855814d4e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810252138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3810252138
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2119007242
Short name T414
Test name
Test status
Simulation time 11148404298 ps
CPU time 31.32 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:50:03 PM PDT 24
Peak memory 480900 kb
Host smart-50bcf41c-be2d-48f9-9af1-890615cafd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119007242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2119007242
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3985417059
Short name T52
Test name
Test status
Simulation time 1796396662 ps
CPU time 59.62 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 12:50:28 PM PDT 24
Peak memory 642104 kb
Host smart-ad5e9b43-6004-4a6d-9109-8915c31a43ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985417059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3985417059
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2405260491
Short name T80
Test name
Test status
Simulation time 111315511 ps
CPU time 0.94 seconds
Started May 14 12:49:32 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 204208 kb
Host smart-5cf5ec24-83b4-4bc3-8ea9-10a565301d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405260491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2405260491
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1090784472
Short name T630
Test name
Test status
Simulation time 718884642 ps
CPU time 9.58 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:40 PM PDT 24
Peak memory 204416 kb
Host smart-debdb621-d87b-476f-9bf9-67bfcb81c884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090784472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1090784472
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.1572125206
Short name T1292
Test name
Test status
Simulation time 14656748541 ps
CPU time 55.51 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 12:50:25 PM PDT 24
Peak memory 789220 kb
Host smart-5ea6835c-d897-4adc-8a50-7b4faf6e8112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572125206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1572125206
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1940683532
Short name T1013
Test name
Test status
Simulation time 379373787 ps
CPU time 14.87 seconds
Started May 14 12:49:31 PM PDT 24
Finished May 14 12:49:48 PM PDT 24
Peak memory 204436 kb
Host smart-2e4aa1a7-c66c-45f1-ae44-80189df97662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940683532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1940683532
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.228844904
Short name T39
Test name
Test status
Simulation time 2767855260 ps
CPU time 28.33 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:50:00 PM PDT 24
Peak memory 340724 kb
Host smart-b2a4304d-5751-401c-b319-9d0e6455c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228844904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.228844904
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3699208945
Short name T48
Test name
Test status
Simulation time 80502574 ps
CPU time 0.64 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:32 PM PDT 24
Peak memory 204084 kb
Host smart-4eee52d7-c5e8-4f1c-a063-c24a6db1d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699208945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3699208945
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.830622156
Short name T987
Test name
Test status
Simulation time 1204826628 ps
CPU time 50.53 seconds
Started May 14 12:49:31 PM PDT 24
Finished May 14 12:50:24 PM PDT 24
Peak memory 313976 kb
Host smart-c77cd78f-d8f8-4b04-9fd6-f4629c3509bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830622156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.830622156
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.864769201
Short name T377
Test name
Test status
Simulation time 1351320137 ps
CPU time 69.03 seconds
Started May 14 12:49:23 PM PDT 24
Finished May 14 12:50:34 PM PDT 24
Peak memory 298968 kb
Host smart-140f9586-80aa-4456-b571-5b3b1835daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864769201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.864769201
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3691303159
Short name T103
Test name
Test status
Simulation time 11874679788 ps
CPU time 663.88 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 01:00:34 PM PDT 24
Peak memory 2716488 kb
Host smart-2fc3b472-8c9e-40a5-8268-73a639d63469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691303159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3691303159
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1979611912
Short name T1134
Test name
Test status
Simulation time 748680092 ps
CPU time 22.03 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 12:49:51 PM PDT 24
Peak memory 212624 kb
Host smart-75b60ff8-5c79-4801-ad11-f88211679944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979611912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1979611912
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1948011289
Short name T768
Test name
Test status
Simulation time 5201720089 ps
CPU time 4.73 seconds
Started May 14 12:49:32 PM PDT 24
Finished May 14 12:49:38 PM PDT 24
Peak memory 204492 kb
Host smart-359cc429-192f-4b9c-bed5-d04d3c7bf808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948011289 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1948011289
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2441386695
Short name T150
Test name
Test status
Simulation time 10326045033 ps
CPU time 14.25 seconds
Started May 14 12:49:33 PM PDT 24
Finished May 14 12:49:49 PM PDT 24
Peak memory 279180 kb
Host smart-6587dad1-5c94-4847-a601-c0079d534ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441386695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2441386695
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3528320010
Short name T769
Test name
Test status
Simulation time 10151508943 ps
CPU time 16.88 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 12:49:45 PM PDT 24
Peak memory 297928 kb
Host smart-a9e5914e-5ea5-4a4a-bd95-81f295703f31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528320010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3528320010
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3956429802
Short name T412
Test name
Test status
Simulation time 1572658182 ps
CPU time 2.13 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:33 PM PDT 24
Peak memory 204320 kb
Host smart-f3f61e74-ed42-4fb4-ad84-006de2bf184f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956429802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3956429802
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3638974040
Short name T307
Test name
Test status
Simulation time 2818777891 ps
CPU time 4.42 seconds
Started May 14 12:49:28 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 206372 kb
Host smart-58915da5-42c2-47ba-8fbe-ae371d2ec779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638974040 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3638974040
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2041967533
Short name T417
Test name
Test status
Simulation time 4659462125 ps
CPU time 3.47 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:36 PM PDT 24
Peak memory 204420 kb
Host smart-99dd5209-26dd-463b-b832-8c226eaf2fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041967533 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2041967533
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3226471017
Short name T830
Test name
Test status
Simulation time 989320812 ps
CPU time 16.26 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:49 PM PDT 24
Peak memory 204276 kb
Host smart-d23be86e-ccb3-4e8f-a9fc-f60386853518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226471017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3226471017
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.4170375606
Short name T633
Test name
Test status
Simulation time 1494218062 ps
CPU time 24.23 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:56 PM PDT 24
Peak memory 225808 kb
Host smart-b24d7d76-18e5-40e7-b106-67259f0af65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170375606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.4170375606
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.713020926
Short name T770
Test name
Test status
Simulation time 33790184303 ps
CPU time 48.9 seconds
Started May 14 12:49:31 PM PDT 24
Finished May 14 12:50:22 PM PDT 24
Peak memory 900120 kb
Host smart-a7027b05-3372-464a-8e65-6824c07adb9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713020926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.713020926
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1092802615
Short name T651
Test name
Test status
Simulation time 7134954676 ps
CPU time 70.52 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:50:43 PM PDT 24
Peak memory 922708 kb
Host smart-4177aa7f-98ca-4652-acfb-9582cd917c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092802615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1092802615
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2326082011
Short name T732
Test name
Test status
Simulation time 3876609609 ps
CPU time 6.64 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:37 PM PDT 24
Peak memory 219644 kb
Host smart-c06772b4-195d-4aef-a5a9-ce16c56ea857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326082011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2326082011
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.3508662436
Short name T698
Test name
Test status
Simulation time 5024134084 ps
CPU time 6.45 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:38 PM PDT 24
Peak memory 217168 kb
Host smart-b8690bb3-60a9-43e2-a337-5f3f92b11d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508662436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.3508662436
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2941003684
Short name T421
Test name
Test status
Simulation time 31684556 ps
CPU time 0.64 seconds
Started May 14 12:49:40 PM PDT 24
Finished May 14 12:49:42 PM PDT 24
Peak memory 204224 kb
Host smart-ec8b56bf-d17e-4f10-b724-9e8a42fe56dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941003684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2941003684
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3145937085
Short name T678
Test name
Test status
Simulation time 112935378 ps
CPU time 2.06 seconds
Started May 14 12:49:42 PM PDT 24
Finished May 14 12:49:46 PM PDT 24
Peak memory 220860 kb
Host smart-15c7ba47-88c2-467b-af2d-4e9ab1486057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145937085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3145937085
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3855563193
Short name T884
Test name
Test status
Simulation time 190581288 ps
CPU time 4.38 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:37 PM PDT 24
Peak memory 239172 kb
Host smart-ec8b8f82-304b-4ab5-8f6a-eb21f50b3566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855563193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3855563193
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3754408816
Short name T378
Test name
Test status
Simulation time 4059375378 ps
CPU time 150.05 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:52:01 PM PDT 24
Peak memory 689968 kb
Host smart-f051912e-b90f-4be1-b078-9dc390a85316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754408816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3754408816
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3442855945
Short name T1138
Test name
Test status
Simulation time 8855641011 ps
CPU time 161.69 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:52:12 PM PDT 24
Peak memory 707416 kb
Host smart-e1074927-96ef-4248-8d83-b55ca83bfd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442855945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3442855945
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3890915433
Short name T1219
Test name
Test status
Simulation time 102235195 ps
CPU time 1 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:32 PM PDT 24
Peak memory 204008 kb
Host smart-5bcca90e-38c6-4547-9efe-e05ecae916ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890915433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3890915433
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.507768910
Short name T870
Test name
Test status
Simulation time 441758948 ps
CPU time 3.08 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:34 PM PDT 24
Peak memory 221420 kb
Host smart-2b6e4b39-ed95-40d2-8930-82318d028585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507768910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
507768910
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.253765817
Short name T506
Test name
Test status
Simulation time 3376693200 ps
CPU time 78.71 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:50:49 PM PDT 24
Peak memory 1016636 kb
Host smart-5a8930aa-2f05-4cb2-afa2-c15aada4951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253765817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.253765817
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3518598197
Short name T1193
Test name
Test status
Simulation time 1393320746 ps
CPU time 14.99 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 12:49:59 PM PDT 24
Peak memory 204436 kb
Host smart-31a871ee-d3bc-48c5-afef-4477a2acdc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518598197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3518598197
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3200915160
Short name T1097
Test name
Test status
Simulation time 21291763869 ps
CPU time 80.22 seconds
Started May 14 12:49:39 PM PDT 24
Finished May 14 12:51:00 PM PDT 24
Peak memory 471560 kb
Host smart-f7078939-b0eb-422b-a8de-f1ec66fc1529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200915160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3200915160
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1854801337
Short name T229
Test name
Test status
Simulation time 43110944 ps
CPU time 0.63 seconds
Started May 14 12:49:32 PM PDT 24
Finished May 14 12:49:35 PM PDT 24
Peak memory 204136 kb
Host smart-f7ef2f73-beb6-4c1e-84ae-82faeda9009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854801337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1854801337
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3063385543
Short name T952
Test name
Test status
Simulation time 50123918026 ps
CPU time 301.19 seconds
Started May 14 12:49:32 PM PDT 24
Finished May 14 12:54:35 PM PDT 24
Peak memory 228872 kb
Host smart-8fddb42f-a82b-4831-a7d7-f9c8687b7646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063385543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3063385543
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3895921226
Short name T843
Test name
Test status
Simulation time 4264766558 ps
CPU time 19.36 seconds
Started May 14 12:49:30 PM PDT 24
Finished May 14 12:49:52 PM PDT 24
Peak memory 285556 kb
Host smart-200b6bdb-97dc-4f3c-8dc8-0029de842eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895921226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3895921226
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2491509714
Short name T1287
Test name
Test status
Simulation time 558197583 ps
CPU time 25.29 seconds
Started May 14 12:49:29 PM PDT 24
Finished May 14 12:49:57 PM PDT 24
Peak memory 212576 kb
Host smart-eda68bca-bada-41fd-9714-d6c70eda5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491509714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2491509714
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.361139954
Short name T1037
Test name
Test status
Simulation time 5003879440 ps
CPU time 4.06 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 12:49:48 PM PDT 24
Peak memory 204480 kb
Host smart-a4ca7ebb-831c-472b-a915-e52802153fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361139954 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.361139954
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.4075200107
Short name T908
Test name
Test status
Simulation time 11027618748 ps
CPU time 9.1 seconds
Started May 14 12:49:40 PM PDT 24
Finished May 14 12:49:50 PM PDT 24
Peak memory 240804 kb
Host smart-d136b366-ce6d-40ff-800c-971e44ae56a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075200107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.4075200107
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1697373914
Short name T802
Test name
Test status
Simulation time 10142748089 ps
CPU time 88.35 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 12:51:12 PM PDT 24
Peak memory 503620 kb
Host smart-94bb215e-7c40-4e68-b1a9-3bc9b78fd028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697373914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1697373914
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.291109424
Short name T11
Test name
Test status
Simulation time 323519235 ps
CPU time 2.31 seconds
Started May 14 12:49:40 PM PDT 24
Finished May 14 12:49:44 PM PDT 24
Peak memory 204444 kb
Host smart-0f4de055-4b38-44b5-b84d-718127d64e16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291109424 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.291109424
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1593259349
Short name T1258
Test name
Test status
Simulation time 1374009349 ps
CPU time 3.88 seconds
Started May 14 12:49:39 PM PDT 24
Finished May 14 12:49:44 PM PDT 24
Peak memory 204392 kb
Host smart-69054477-5092-4f20-95c5-f9491407f5c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593259349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1593259349
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2601264704
Short name T338
Test name
Test status
Simulation time 14850632406 ps
CPU time 148.89 seconds
Started May 14 12:49:39 PM PDT 24
Finished May 14 12:52:09 PM PDT 24
Peak memory 2001616 kb
Host smart-2867b045-027c-4023-b99f-c6aca13a958c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601264704 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2601264704
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.1179093893
Short name T515
Test name
Test status
Simulation time 2927575334 ps
CPU time 16.28 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 12:49:58 PM PDT 24
Peak memory 204308 kb
Host smart-36821d72-62c8-4b10-abb3-306c18e84e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179093893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.1179093893
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2386803292
Short name T656
Test name
Test status
Simulation time 1229933139 ps
CPU time 14.72 seconds
Started May 14 12:49:40 PM PDT 24
Finished May 14 12:49:56 PM PDT 24
Peak memory 214060 kb
Host smart-478828c9-e0a0-4a15-9c82-68837ca4a0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386803292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2386803292
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1886292038
Short name T806
Test name
Test status
Simulation time 19376856453 ps
CPU time 11.34 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 12:49:54 PM PDT 24
Peak memory 204424 kb
Host smart-563fd5d4-6129-401b-873d-cee6d2a35038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886292038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1886292038
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.539733350
Short name T324
Test name
Test status
Simulation time 13606891468 ps
CPU time 716.76 seconds
Started May 14 12:49:41 PM PDT 24
Finished May 14 01:01:40 PM PDT 24
Peak memory 3333168 kb
Host smart-d69b618c-37c0-4646-8a96-853b6fbb808e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539733350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.539733350
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1550706214
Short name T814
Test name
Test status
Simulation time 1290126546 ps
CPU time 6.58 seconds
Started May 14 12:49:40 PM PDT 24
Finished May 14 12:49:48 PM PDT 24
Peak memory 212600 kb
Host smart-bd475531-dde3-4f80-bf63-b3826b772dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550706214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1550706214
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.667068922
Short name T1158
Test name
Test status
Simulation time 54997810 ps
CPU time 0.64 seconds
Started May 14 12:45:43 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 204144 kb
Host smart-d8d211d9-f473-4f34-ada9-9082f5e6e12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667068922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.667068922
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.724893784
Short name T636
Test name
Test status
Simulation time 417725397 ps
CPU time 1.62 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 212712 kb
Host smart-fbd12646-9b8f-4421-b234-5ebe3d2549ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724893784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.724893784
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3142039981
Short name T1210
Test name
Test status
Simulation time 781025685 ps
CPU time 6.95 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:49 PM PDT 24
Peak memory 270924 kb
Host smart-63027802-c6d9-4b39-b1e1-9c816f616eea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142039981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3142039981
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.905967579
Short name T1271
Test name
Test status
Simulation time 6249324463 ps
CPU time 82.4 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:47:06 PM PDT 24
Peak memory 703796 kb
Host smart-5ab68ee3-3e63-433a-af7e-eae24b0daf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905967579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.905967579
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3130111949
Short name T597
Test name
Test status
Simulation time 1459373049 ps
CPU time 43.55 seconds
Started May 14 12:45:36 PM PDT 24
Finished May 14 12:46:22 PM PDT 24
Peak memory 506288 kb
Host smart-ba1d1e50-d92d-4fb7-8125-84b014ec09d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130111949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3130111949
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3226075357
Short name T1016
Test name
Test status
Simulation time 718370065 ps
CPU time 0.9 seconds
Started May 14 12:45:44 PM PDT 24
Finished May 14 12:45:47 PM PDT 24
Peak memory 204204 kb
Host smart-6fe221af-7c97-48cd-ae0b-7714023f6a75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226075357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3226075357
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.498884318
Short name T299
Test name
Test status
Simulation time 1254196379 ps
CPU time 8.68 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:51 PM PDT 24
Peak memory 204392 kb
Host smart-f78f3641-a4dc-4b53-a43b-c66862ebc6da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498884318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.498884318
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.4268486974
Short name T692
Test name
Test status
Simulation time 16655113273 ps
CPU time 310.68 seconds
Started May 14 12:45:40 PM PDT 24
Finished May 14 12:50:53 PM PDT 24
Peak memory 1174576 kb
Host smart-fe519e95-b3b6-4797-9004-a2e965613b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268486974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4268486974
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3920146474
Short name T949
Test name
Test status
Simulation time 328182717 ps
CPU time 13.66 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:56 PM PDT 24
Peak memory 204252 kb
Host smart-84bb8ce2-b1a5-4a93-a562-97c1c5b8e01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920146474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3920146474
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2425426411
Short name T38
Test name
Test status
Simulation time 3473964696 ps
CPU time 69.68 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:46:54 PM PDT 24
Peak memory 350068 kb
Host smart-4ef21fec-b556-414b-9a68-8daf496ebc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425426411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2425426411
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1345467547
Short name T676
Test name
Test status
Simulation time 30026664 ps
CPU time 0.68 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:08 PM PDT 24
Peak memory 204096 kb
Host smart-48cbec8a-e0f2-44de-892b-5363a118cc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345467547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1345467547
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1059010985
Short name T745
Test name
Test status
Simulation time 30745055491 ps
CPU time 190.88 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:48:55 PM PDT 24
Peak memory 1076880 kb
Host smart-9323491d-9dca-4311-8aee-f61f4724d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059010985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1059010985
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3546233663
Short name T111
Test name
Test status
Simulation time 1485356196 ps
CPU time 69.22 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:46:59 PM PDT 24
Peak memory 334252 kb
Host smart-799bd6b2-9218-4ce2-adc2-762c74e5390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546233663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3546233663
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.1446690715
Short name T169
Test name
Test status
Simulation time 9099815533 ps
CPU time 276.22 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:50:26 PM PDT 24
Peak memory 959084 kb
Host smart-f84781a3-54c4-4e99-a388-1eacd1776729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446690715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1446690715
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2463755653
Short name T685
Test name
Test status
Simulation time 560828286 ps
CPU time 24.27 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:46:13 PM PDT 24
Peak memory 212648 kb
Host smart-03e05a52-3c47-420e-a2fd-6d9796b9ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463755653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2463755653
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.134765833
Short name T1343
Test name
Test status
Simulation time 2898121130 ps
CPU time 4.09 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:48 PM PDT 24
Peak memory 212980 kb
Host smart-e60603c8-1ff6-4ed2-9174-6d6b5d187bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134765833 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.134765833
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.250007005
Short name T1276
Test name
Test status
Simulation time 10035586033 ps
CPU time 69.68 seconds
Started May 14 12:45:43 PM PDT 24
Finished May 14 12:46:55 PM PDT 24
Peak memory 509616 kb
Host smart-5412e79a-a2ad-405f-9138-29b90c88f332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250007005 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.250007005
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2719428863
Short name T838
Test name
Test status
Simulation time 10299191441 ps
CPU time 9.15 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:51 PM PDT 24
Peak memory 239712 kb
Host smart-89fccf02-4eb6-44cc-8a33-5a7a8452c822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719428863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2719428863
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1289923225
Short name T379
Test name
Test status
Simulation time 1146712046 ps
CPU time 2.99 seconds
Started May 14 12:45:52 PM PDT 24
Finished May 14 12:45:56 PM PDT 24
Peak memory 204376 kb
Host smart-a5a6d2d5-62c4-47bb-95f2-4948c833869d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289923225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1289923225
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2861037577
Short name T824
Test name
Test status
Simulation time 5559919754 ps
CPU time 6.25 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:48 PM PDT 24
Peak memory 204348 kb
Host smart-c68ed2a1-7e04-467d-8fe5-0546532a60d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861037577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2861037577
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.1322882666
Short name T900
Test name
Test status
Simulation time 22466045735 ps
CPU time 171.95 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:48:33 PM PDT 24
Peak memory 2610004 kb
Host smart-58a2cbdc-d458-492a-a8b9-d2e89b5d613b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322882666 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.1322882666
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2598228366
Short name T653
Test name
Test status
Simulation time 2183730315 ps
CPU time 44.45 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 204448 kb
Host smart-a8873366-5a44-4837-83dc-f255e7bd23e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598228366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2598228366
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.579794585
Short name T1083
Test name
Test status
Simulation time 351220767 ps
CPU time 5.13 seconds
Started May 14 12:45:47 PM PDT 24
Finished May 14 12:45:53 PM PDT 24
Peak memory 204476 kb
Host smart-5e3e7f5d-5766-4df7-b6d2-f5629d60f002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579794585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.579794585
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3879336129
Short name T383
Test name
Test status
Simulation time 19396738484 ps
CPU time 12.79 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:56 PM PDT 24
Peak memory 204476 kb
Host smart-b4b255e1-04f0-4fbd-8e8d-4b2909a88d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879336129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3879336129
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.693205591
Short name T573
Test name
Test status
Simulation time 21138393363 ps
CPU time 1184.13 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 2571504 kb
Host smart-ba24fdc6-164a-4dda-9bc5-bfe68bebe15e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693205591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_ta
rget_stretch.693205591
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1063253167
Short name T478
Test name
Test status
Simulation time 4294974409 ps
CPU time 6.68 seconds
Started May 14 12:45:43 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 220684 kb
Host smart-5892bc41-15ed-4e4e-aa36-02a39c1da208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063253167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1063253167
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3645993378
Short name T166
Test name
Test status
Simulation time 95121405 ps
CPU time 0.63 seconds
Started May 14 12:45:57 PM PDT 24
Finished May 14 12:45:59 PM PDT 24
Peak memory 204200 kb
Host smart-22a36f95-ac5c-4c3a-b4ea-70e30796ff51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645993378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3645993378
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3451947559
Short name T933
Test name
Test status
Simulation time 120429965 ps
CPU time 1.89 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:45:53 PM PDT 24
Peak memory 212696 kb
Host smart-45113a01-b1f0-4f3c-b4b4-9391a48132ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451947559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3451947559
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3361317351
Short name T1310
Test name
Test status
Simulation time 969818270 ps
CPU time 5.24 seconds
Started May 14 12:45:53 PM PDT 24
Finished May 14 12:45:59 PM PDT 24
Peak memory 246144 kb
Host smart-eb20510c-c03e-4905-9bfc-e7a9b8ddf43e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361317351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3361317351
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3856670624
Short name T58
Test name
Test status
Simulation time 6302296923 ps
CPU time 106.56 seconds
Started May 14 12:45:45 PM PDT 24
Finished May 14 12:47:33 PM PDT 24
Peak memory 594976 kb
Host smart-c6752940-2382-4934-ae70-d34dcf368a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856670624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3856670624
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3986670161
Short name T639
Test name
Test status
Simulation time 2001992852 ps
CPU time 147.46 seconds
Started May 14 12:45:51 PM PDT 24
Finished May 14 12:48:19 PM PDT 24
Peak memory 645832 kb
Host smart-a74c66ac-b737-4222-9446-d318857b19e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986670161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3986670161
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3743425893
Short name T825
Test name
Test status
Simulation time 1113059602 ps
CPU time 0.99 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:45:52 PM PDT 24
Peak memory 204204 kb
Host smart-173dd653-d24a-4543-ad98-f25c37c3e0fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743425893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3743425893
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1688371247
Short name T764
Test name
Test status
Simulation time 742664625 ps
CPU time 3.87 seconds
Started May 14 12:45:39 PM PDT 24
Finished May 14 12:45:46 PM PDT 24
Peak memory 204240 kb
Host smart-57f670c4-8681-4ac3-81f6-519b750adc3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688371247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1688371247
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2419211347
Short name T734
Test name
Test status
Simulation time 4331044272 ps
CPU time 104.97 seconds
Started May 14 12:45:51 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 1226116 kb
Host smart-5013a07c-89db-4833-9372-49baa31d19cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419211347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2419211347
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2369424446
Short name T220
Test name
Test status
Simulation time 623929470 ps
CPU time 6.53 seconds
Started May 14 12:46:01 PM PDT 24
Finished May 14 12:46:09 PM PDT 24
Peak memory 204664 kb
Host smart-fd8db1a9-be7e-45ec-8b27-a7f857fc1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369424446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2369424446
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3592820266
Short name T35
Test name
Test status
Simulation time 1431975537 ps
CPU time 70.24 seconds
Started May 14 12:45:50 PM PDT 24
Finished May 14 12:47:01 PM PDT 24
Peak memory 342484 kb
Host smart-a1c1585e-f507-444e-a6bc-ff3fff17b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592820266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3592820266
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.401678484
Short name T731
Test name
Test status
Simulation time 78915109 ps
CPU time 0.66 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:45:44 PM PDT 24
Peak memory 204084 kb
Host smart-f0b6a1cc-979f-4794-945d-a5af7926f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401678484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.401678484
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2689728915
Short name T1056
Test name
Test status
Simulation time 76706054176 ps
CPU time 645.68 seconds
Started May 14 12:45:57 PM PDT 24
Finished May 14 12:56:43 PM PDT 24
Peak memory 1562080 kb
Host smart-f418509d-3112-49b7-bce8-c0542fab8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689728915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2689728915
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1667982646
Short name T387
Test name
Test status
Simulation time 1160020192 ps
CPU time 54.35 seconds
Started May 14 12:45:41 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 301804 kb
Host smart-9f09a05f-8258-42be-81de-475f24aa8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667982646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1667982646
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2725725420
Short name T122
Test name
Test status
Simulation time 53312427032 ps
CPU time 1652.54 seconds
Started May 14 12:45:53 PM PDT 24
Finished May 14 01:13:26 PM PDT 24
Peak memory 4028952 kb
Host smart-0e9baaf8-3e32-4651-9314-51a5cc838ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725725420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2725725420
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3859949805
Short name T754
Test name
Test status
Simulation time 1191954826 ps
CPU time 26.84 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 212656 kb
Host smart-05193a6d-4e4f-4518-aa8a-a8d1a45bf053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859949805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3859949805
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1820640782
Short name T964
Test name
Test status
Simulation time 2844159063 ps
CPU time 3.39 seconds
Started May 14 12:45:58 PM PDT 24
Finished May 14 12:46:02 PM PDT 24
Peak memory 204424 kb
Host smart-49fc956c-7aa7-4b11-99c9-e0da7fd7adc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820640782 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1820640782
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2548971098
Short name T32
Test name
Test status
Simulation time 10172991448 ps
CPU time 15.11 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 257448 kb
Host smart-a0c0ae9c-5984-44cf-ae0d-223b38cbe15f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548971098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2548971098
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3429907750
Short name T569
Test name
Test status
Simulation time 10254553401 ps
CPU time 15.05 seconds
Started May 14 12:45:52 PM PDT 24
Finished May 14 12:46:08 PM PDT 24
Peak memory 298944 kb
Host smart-65859c82-1d91-4735-9203-b1fa057678ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429907750 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3429907750
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1120655934
Short name T1003
Test name
Test status
Simulation time 483903655 ps
CPU time 2.72 seconds
Started May 14 12:46:00 PM PDT 24
Finished May 14 12:46:04 PM PDT 24
Peak memory 204408 kb
Host smart-b9b5472a-2598-4352-9840-48a6ee9f221d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120655934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1120655934
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3114670277
Short name T580
Test name
Test status
Simulation time 1488773949 ps
CPU time 4.29 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:46:01 PM PDT 24
Peak memory 205636 kb
Host smart-d6690a40-532c-41ce-98c0-5ad587ce9eb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114670277 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3114670277
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1387334118
Short name T978
Test name
Test status
Simulation time 8877160700 ps
CPU time 6.52 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:12 PM PDT 24
Peak memory 204292 kb
Host smart-cc837563-2bb2-488e-a8af-63ac65c2745b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387334118 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1387334118
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1777061155
Short name T1161
Test name
Test status
Simulation time 1782844218 ps
CPU time 13.27 seconds
Started May 14 12:45:52 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 204380 kb
Host smart-60fe2663-125d-4f4b-a525-431be5c1f492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777061155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1777061155
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3351536876
Short name T931
Test name
Test status
Simulation time 1310110834 ps
CPU time 6.02 seconds
Started May 14 12:46:03 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 204444 kb
Host smart-a639b6ae-58da-4d4e-8fc9-72403f0ed5f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351536876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3351536876
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3110985882
Short name T1041
Test name
Test status
Simulation time 41947642217 ps
CPU time 739.37 seconds
Started May 14 12:45:55 PM PDT 24
Finished May 14 12:58:15 PM PDT 24
Peak memory 5727604 kb
Host smart-974ae77c-9b41-47e4-8a07-7dfb630bdb1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110985882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3110985882
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.3794740193
Short name T1025
Test name
Test status
Simulation time 34781939959 ps
CPU time 49.46 seconds
Started May 14 12:45:54 PM PDT 24
Finished May 14 12:46:44 PM PDT 24
Peak memory 515148 kb
Host smart-0fe829ab-a6e4-46d5-8f6e-db473237ea44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794740193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.3794740193
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3633608208
Short name T334
Test name
Test status
Simulation time 2897551261 ps
CPU time 7.69 seconds
Started May 14 12:45:46 PM PDT 24
Finished May 14 12:45:55 PM PDT 24
Peak memory 220620 kb
Host smart-7e45197a-ce59-4db7-bbd4-435c2f4fa8b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633608208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3633608208
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.4045824636
Short name T16
Test name
Test status
Simulation time 831355829 ps
CPU time 4.36 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:12 PM PDT 24
Peak memory 206544 kb
Host smart-9a5dd152-c0dc-4b4d-86be-6c2b30e57aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045824636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.4045824636
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3897114577
Short name T273
Test name
Test status
Simulation time 24312047 ps
CPU time 0.66 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:45:58 PM PDT 24
Peak memory 204088 kb
Host smart-67188b1f-4caf-4dd1-8bef-582a28fd8869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897114577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3897114577
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.1119021701
Short name T872
Test name
Test status
Simulation time 98925124 ps
CPU time 1.69 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:45:59 PM PDT 24
Peak memory 212616 kb
Host smart-c4f5523b-f621-4bdd-bcaa-9151d2d1ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119021701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1119021701
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.458286048
Short name T1192
Test name
Test status
Simulation time 307300364 ps
CPU time 15.81 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:46:05 PM PDT 24
Peak memory 266940 kb
Host smart-3af7e1a1-fc2a-476e-bb43-ddeb323d2ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458286048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.458286048
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.977299628
Short name T1162
Test name
Test status
Simulation time 7832243792 ps
CPU time 56.44 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 652068 kb
Host smart-ebecd4f8-daa9-4fbb-9577-760d05f32d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977299628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.977299628
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1032892647
Short name T503
Test name
Test status
Simulation time 6053876910 ps
CPU time 40.22 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:47 PM PDT 24
Peak memory 550020 kb
Host smart-4c19ad4f-0420-4d0b-bf20-6978a7564bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032892647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1032892647
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3399311666
Short name T876
Test name
Test status
Simulation time 498755437 ps
CPU time 0.99 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 204112 kb
Host smart-8a1c72bf-a773-4bc9-9e6e-5330192dc01a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399311666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3399311666
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2721680121
Short name T905
Test name
Test status
Simulation time 129491501 ps
CPU time 6.47 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 204292 kb
Host smart-d818f147-569d-43fd-9bb4-1aaf2c4c6ee3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721680121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2721680121
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.5381264
Short name T97
Test name
Test status
Simulation time 3032485117 ps
CPU time 66.85 seconds
Started May 14 12:45:48 PM PDT 24
Finished May 14 12:46:56 PM PDT 24
Peak memory 925372 kb
Host smart-37663ab8-c880-4e77-9405-804b2bfb7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5381264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.5381264
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3413859893
Short name T76
Test name
Test status
Simulation time 1251018293 ps
CPU time 4.19 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:13 PM PDT 24
Peak memory 204388 kb
Host smart-55ec29ce-f083-406b-9def-118371e6a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413859893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3413859893
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1740603848
Short name T1111
Test name
Test status
Simulation time 1510948957 ps
CPU time 71.11 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:47:18 PM PDT 24
Peak memory 314836 kb
Host smart-43a761db-c175-4274-bb1a-78221dfe1092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740603848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1740603848
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.246092387
Short name T488
Test name
Test status
Simulation time 28354414 ps
CPU time 0.66 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 204076 kb
Host smart-a7012e2a-ef41-47fe-85e3-d0e59a45b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246092387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.246092387
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1070266188
Short name T1027
Test name
Test status
Simulation time 5591517564 ps
CPU time 40.06 seconds
Started May 14 12:45:46 PM PDT 24
Finished May 14 12:46:28 PM PDT 24
Peak memory 224768 kb
Host smart-a9c384be-1907-4cf1-ad53-cd8ff63ce9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070266188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1070266188
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1191321489
Short name T1315
Test name
Test status
Simulation time 5345629077 ps
CPU time 27.11 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 333108 kb
Host smart-91fb2987-f9d4-4534-be5b-f222dece9065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191321489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1191321489
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2090366552
Short name T1326
Test name
Test status
Simulation time 64792152779 ps
CPU time 349.71 seconds
Started May 14 12:45:49 PM PDT 24
Finished May 14 12:51:40 PM PDT 24
Peak memory 782580 kb
Host smart-9303b9a8-8ff1-4e58-9032-cb795240ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090366552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2090366552
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1532749123
Short name T236
Test name
Test status
Simulation time 794273246 ps
CPU time 17.31 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 12:46:17 PM PDT 24
Peak memory 212516 kb
Host smart-a12de312-d529-40a3-8e3a-0051893852da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532749123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1532749123
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3317017322
Short name T1336
Test name
Test status
Simulation time 2659199117 ps
CPU time 4.88 seconds
Started May 14 12:46:02 PM PDT 24
Finished May 14 12:46:09 PM PDT 24
Peak memory 212708 kb
Host smart-84b5e2d6-ede9-4aa3-994b-e7db672e6a22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317017322 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3317017322
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2862843415
Short name T810
Test name
Test status
Simulation time 10169140562 ps
CPU time 9.35 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:17 PM PDT 24
Peak memory 234564 kb
Host smart-7c5b2197-a855-4d7a-8694-72d69794d716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862843415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2862843415
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1809821219
Short name T62
Test name
Test status
Simulation time 10081677239 ps
CPU time 65.66 seconds
Started May 14 12:46:03 PM PDT 24
Finished May 14 12:47:10 PM PDT 24
Peak memory 442912 kb
Host smart-aaf3bb97-11e7-4d34-9af9-dd8c57a62025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809821219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1809821219
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.273957425
Short name T112
Test name
Test status
Simulation time 335245469 ps
CPU time 2.27 seconds
Started May 14 12:46:02 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 204332 kb
Host smart-8b4cba9f-eaec-4aa9-abc9-3dbddd4d206e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273957425 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.273957425
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1390375069
Short name T782
Test name
Test status
Simulation time 974341059 ps
CPU time 3.93 seconds
Started May 14 12:46:12 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 204408 kb
Host smart-54e3c056-d5be-4a65-81d1-baa081a8beb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390375069 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1390375069
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2912558748
Short name T600
Test name
Test status
Simulation time 17287566002 ps
CPU time 37.78 seconds
Started May 14 12:46:00 PM PDT 24
Finished May 14 12:46:40 PM PDT 24
Peak memory 686868 kb
Host smart-2eee121e-f7f4-43ad-abd7-ee8e9ed99e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912558748 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2912558748
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.244118872
Short name T223
Test name
Test status
Simulation time 4939846414 ps
CPU time 15.13 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 204392 kb
Host smart-638cb7c1-6f08-47e7-b257-581e407c90df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244118872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.244118872
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3399382801
Short name T483
Test name
Test status
Simulation time 1153585888 ps
CPU time 25.12 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:32 PM PDT 24
Peak memory 204424 kb
Host smart-2f7c7627-00e1-43b8-8583-46eb9a6d579f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399382801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3399382801
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2716545531
Short name T360
Test name
Test status
Simulation time 46974728644 ps
CPU time 1002.75 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 01:02:43 PM PDT 24
Peak memory 6800944 kb
Host smart-1eb18276-139a-4b03-8194-4ff2c540177c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716545531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2716545531
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2717128816
Short name T382
Test name
Test status
Simulation time 13485864349 ps
CPU time 193.58 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 12:49:14 PM PDT 24
Peak memory 821524 kb
Host smart-a9004007-056b-458f-a010-f33fa70ea342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717128816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2717128816
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.808300560
Short name T1346
Test name
Test status
Simulation time 1253593799 ps
CPU time 6.76 seconds
Started May 14 12:45:58 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 212536 kb
Host smart-39bc3063-8790-4dc0-8ea2-86b8a2b8cf20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808300560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.808300560
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.993604818
Short name T1340
Test name
Test status
Simulation time 124262746 ps
CPU time 0.6 seconds
Started May 14 12:45:53 PM PDT 24
Finished May 14 12:45:54 PM PDT 24
Peak memory 204156 kb
Host smart-f593760e-ad70-4419-b0ea-cd7a1b7d3be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993604818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.993604818
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1478940222
Short name T574
Test name
Test status
Simulation time 112399675 ps
CPU time 1.7 seconds
Started May 14 12:46:03 PM PDT 24
Finished May 14 12:46:06 PM PDT 24
Peak memory 212808 kb
Host smart-3b78ffba-98aa-41fb-a7e8-edb8092da6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478940222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1478940222
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2623198149
Short name T988
Test name
Test status
Simulation time 1287296688 ps
CPU time 16.08 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:25 PM PDT 24
Peak memory 260792 kb
Host smart-57e9cb93-161b-4124-811b-ad624dedb8d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623198149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2623198149
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.4018696544
Short name T56
Test name
Test status
Simulation time 3500058015 ps
CPU time 118.48 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:48:06 PM PDT 24
Peak memory 555696 kb
Host smart-83d076ce-df6e-44e6-9394-5d92ee439d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018696544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.4018696544
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.4104132246
Short name T1358
Test name
Test status
Simulation time 1116474636 ps
CPU time 69.24 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:47:17 PM PDT 24
Peak memory 467584 kb
Host smart-a2ae3cb6-5c46-40c5-8701-ccd8a3d9f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104132246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4104132246
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3367480585
Short name T81
Test name
Test status
Simulation time 108167946 ps
CPU time 0.95 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:45:58 PM PDT 24
Peak memory 204356 kb
Host smart-f5391bc9-f255-4cce-821f-12e29b79a060
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367480585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3367480585
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3717986062
Short name T663
Test name
Test status
Simulation time 240303203 ps
CPU time 3.45 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:46:00 PM PDT 24
Peak memory 226884 kb
Host smart-2f875291-1a10-4800-834a-a95f33465a65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717986062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3717986062
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3426670110
Short name T475
Test name
Test status
Simulation time 3703265399 ps
CPU time 54.46 seconds
Started May 14 12:46:02 PM PDT 24
Finished May 14 12:46:58 PM PDT 24
Peak memory 643376 kb
Host smart-eea092ec-78f6-4d14-ade8-1d049cc73362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426670110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3426670110
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1479866247
Short name T499
Test name
Test status
Simulation time 396975248 ps
CPU time 6.15 seconds
Started May 14 12:45:55 PM PDT 24
Finished May 14 12:46:03 PM PDT 24
Peak memory 204352 kb
Host smart-77885811-c71a-4026-99d1-6374e943322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479866247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1479866247
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1886764633
Short name T530
Test name
Test status
Simulation time 15031781140 ps
CPU time 23.09 seconds
Started May 14 12:46:01 PM PDT 24
Finished May 14 12:46:26 PM PDT 24
Peak memory 309624 kb
Host smart-38600feb-308b-4394-a265-6af7f99ecb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886764633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1886764633
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.668606243
Short name T596
Test name
Test status
Simulation time 18646715 ps
CPU time 0.67 seconds
Started May 14 12:46:01 PM PDT 24
Finished May 14 12:46:03 PM PDT 24
Peak memory 204100 kb
Host smart-79d54a5e-e33f-44e9-bcba-a7b8d1259254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668606243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.668606243
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.870595704
Short name T738
Test name
Test status
Simulation time 6946568915 ps
CPU time 6.84 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:12 PM PDT 24
Peak memory 217216 kb
Host smart-fab0c4b6-0212-45d8-af9e-0e23d37490bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870595704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.870595704
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1775812216
Short name T632
Test name
Test status
Simulation time 7725630148 ps
CPU time 37.94 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 12:46:39 PM PDT 24
Peak memory 348460 kb
Host smart-e0e50b3f-549d-4616-b4f9-c0dd78ab71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775812216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1775812216
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.461650881
Short name T1349
Test name
Test status
Simulation time 39006135726 ps
CPU time 1103.54 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 01:04:38 PM PDT 24
Peak memory 2119508 kb
Host smart-7d61b0ee-5d59-4bd1-b0f8-72081930e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461650881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.461650881
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.272272996
Short name T79
Test name
Test status
Simulation time 3046291636 ps
CPU time 22.3 seconds
Started May 14 12:45:56 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 212672 kb
Host smart-4c217cfd-6f4b-42f9-b5eb-e2be6ca4e34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272272996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.272272996
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1095400766
Short name T589
Test name
Test status
Simulation time 3671705215 ps
CPU time 3.31 seconds
Started May 14 12:46:00 PM PDT 24
Finished May 14 12:46:05 PM PDT 24
Peak memory 204480 kb
Host smart-758a5e76-7e74-4ae0-ad18-00480ecb50c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095400766 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1095400766
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2478242113
Short name T389
Test name
Test status
Simulation time 10091051123 ps
CPU time 27.66 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:38 PM PDT 24
Peak memory 362172 kb
Host smart-fbc1df54-90e7-4f93-bcb2-d0e267925c7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478242113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2478242113
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2034434876
Short name T950
Test name
Test status
Simulation time 10214415384 ps
CPU time 30.53 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 12:46:30 PM PDT 24
Peak memory 352344 kb
Host smart-6ac85805-7cf1-4004-bb50-47e10e575665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034434876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2034434876
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.612854008
Short name T1196
Test name
Test status
Simulation time 483414658 ps
CPU time 2.34 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 204336 kb
Host smart-6cc5d58f-5e7c-4474-bda9-f9ae47dddb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612854008 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.612854008
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.975528604
Short name T1123
Test name
Test status
Simulation time 3739697207 ps
CPU time 4.89 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 207476 kb
Host smart-2bdf379e-8aeb-4764-a659-f91acf08e03e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975528604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.975528604
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.4015872236
Short name T944
Test name
Test status
Simulation time 11969516555 ps
CPU time 30.53 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:36 PM PDT 24
Peak memory 688416 kb
Host smart-f810a0c7-fdc6-4094-b7a2-e1c1916d8d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015872236 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.4015872236
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.794945709
Short name T331
Test name
Test status
Simulation time 2784679123 ps
CPU time 11.18 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:17 PM PDT 24
Peak memory 204468 kb
Host smart-c91865d8-222f-4ef6-9510-1b7e70d0ff7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794945709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.794945709
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2511007832
Short name T261
Test name
Test status
Simulation time 2956279377 ps
CPU time 21.52 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 229972 kb
Host smart-e176e2e5-e621-473e-be55-af450bd90fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511007832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2511007832
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3974499190
Short name T800
Test name
Test status
Simulation time 29130258230 ps
CPU time 58.15 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:47:05 PM PDT 24
Peak memory 1024708 kb
Host smart-9bcabe91-dba6-4c32-a668-82b22e09a7b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974499190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3974499190
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3796053681
Short name T254
Test name
Test status
Simulation time 26125466404 ps
CPU time 190.06 seconds
Started May 14 12:45:59 PM PDT 24
Finished May 14 12:49:10 PM PDT 24
Peak memory 1584896 kb
Host smart-9fba3a77-a5ea-4c4d-9f62-f3cef79a953c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796053681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3796053681
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.875473451
Short name T926
Test name
Test status
Simulation time 1310121307 ps
CPU time 6.58 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 220692 kb
Host smart-766f08ba-def8-4050-adc7-532872fe4257
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875473451 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.875473451
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2188725445
Short name T517
Test name
Test status
Simulation time 48613258 ps
CPU time 0.62 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:07 PM PDT 24
Peak memory 204148 kb
Host smart-58e01c97-131e-4ba3-b05b-667de791c5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188725445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2188725445
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1211990360
Short name T546
Test name
Test status
Simulation time 386486912 ps
CPU time 1.42 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 212656 kb
Host smart-32462a15-cb8b-4b48-ade6-f03b0c80b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211990360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1211990360
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1054985574
Short name T1308
Test name
Test status
Simulation time 285779903 ps
CPU time 6.43 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 12:46:16 PM PDT 24
Peak memory 262088 kb
Host smart-f79d259a-819b-4ea0-9370-0e4280a1741b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054985574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1054985574
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.98166851
Short name T438
Test name
Test status
Simulation time 5463964936 ps
CPU time 83.63 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:47:38 PM PDT 24
Peak memory 496212 kb
Host smart-6947c459-d5b8-453d-939a-4f1b5d2954b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98166851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.98166851
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.114319033
Short name T1217
Test name
Test status
Simulation time 8776640960 ps
CPU time 149.12 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:48:46 PM PDT 24
Peak memory 687108 kb
Host smart-871359b0-0682-40d5-ac50-102b146fda6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114319033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.114319033
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.122875462
Short name T767
Test name
Test status
Simulation time 88643373 ps
CPU time 0.9 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:14 PM PDT 24
Peak memory 204160 kb
Host smart-b5ca00df-8104-4eca-b48f-a70e327f2ef1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122875462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.122875462
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3114042054
Short name T945
Test name
Test status
Simulation time 705744398 ps
CPU time 8.14 seconds
Started May 14 12:46:15 PM PDT 24
Finished May 14 12:46:25 PM PDT 24
Peak memory 204348 kb
Host smart-5cb24175-ae4a-4946-84c2-466976ecd05a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114042054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3114042054
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1234546738
Short name T1194
Test name
Test status
Simulation time 8666357530 ps
CPU time 111.04 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:48:02 PM PDT 24
Peak memory 1262636 kb
Host smart-db69e2ea-52f6-43b3-9996-fb859b60e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234546738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1234546738
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2804479658
Short name T1167
Test name
Test status
Simulation time 2556077744 ps
CPU time 5.68 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:46:17 PM PDT 24
Peak memory 204464 kb
Host smart-a06fb355-0dc0-4502-a5c5-29d8bdad2e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804479658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2804479658
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1616083808
Short name T625
Test name
Test status
Simulation time 5218415132 ps
CPU time 60.3 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:47:13 PM PDT 24
Peak memory 339612 kb
Host smart-dbbd7c83-a2d7-4900-a679-b56a8b39c0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616083808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1616083808
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3905041283
Short name T450
Test name
Test status
Simulation time 25442533 ps
CPU time 0.68 seconds
Started May 14 12:46:00 PM PDT 24
Finished May 14 12:46:02 PM PDT 24
Peak memory 204040 kb
Host smart-c9496d80-42f0-4606-b562-88ca7ccfeb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905041283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3905041283
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3304713166
Short name T641
Test name
Test status
Simulation time 13683025880 ps
CPU time 126.44 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:48:21 PM PDT 24
Peak memory 1020572 kb
Host smart-6b0d9548-698a-498b-b177-fe2633723f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304713166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3304713166
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3597751447
Short name T1200
Test name
Test status
Simulation time 4801649899 ps
CPU time 16.14 seconds
Started May 14 12:46:02 PM PDT 24
Finished May 14 12:46:20 PM PDT 24
Peak memory 269348 kb
Host smart-e3782c17-59d1-4b9a-8ebd-4021a79bb0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597751447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3597751447
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.733439848
Short name T751
Test name
Test status
Simulation time 5131723587 ps
CPU time 9.56 seconds
Started May 14 12:46:11 PM PDT 24
Finished May 14 12:46:24 PM PDT 24
Peak memory 220364 kb
Host smart-ef0fc76e-e4b9-41fa-8338-d0d98d963cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733439848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.733439848
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.529752126
Short name T29
Test name
Test status
Simulation time 770340797 ps
CPU time 3.52 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 204392 kb
Host smart-af18afe8-b2f7-4dd7-813f-4281e6793fb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529752126 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.529752126
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3844410533
Short name T495
Test name
Test status
Simulation time 10206698417 ps
CPU time 7.12 seconds
Started May 14 12:46:09 PM PDT 24
Finished May 14 12:46:19 PM PDT 24
Peak memory 241988 kb
Host smart-4c3f41aa-7fd5-44a4-af1c-12379b82e9f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844410533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3844410533
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.4198434925
Short name T520
Test name
Test status
Simulation time 10227982320 ps
CPU time 16.71 seconds
Started May 14 12:46:13 PM PDT 24
Finished May 14 12:46:33 PM PDT 24
Peak memory 318648 kb
Host smart-3867ca4a-6424-44dd-9334-472c8790705d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198434925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.4198434925
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.4134402253
Short name T318
Test name
Test status
Simulation time 1598296070 ps
CPU time 2.69 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:11 PM PDT 24
Peak memory 204428 kb
Host smart-3f68ca2c-8a52-478d-8df1-940ba570084a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134402253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.4134402253
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1988075004
Short name T1275
Test name
Test status
Simulation time 942161492 ps
CPU time 5.3 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:13 PM PDT 24
Peak memory 220372 kb
Host smart-02e0f3c2-8cbd-47cb-80cd-913839fedf0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988075004 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1988075004
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2821828557
Short name T1289
Test name
Test status
Simulation time 6619408141 ps
CPU time 6.85 seconds
Started May 14 12:46:06 PM PDT 24
Finished May 14 12:46:15 PM PDT 24
Peak memory 372856 kb
Host smart-5d00f6ed-7676-44cb-8bd0-264e8684a3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821828557 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2821828557
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1393068823
Short name T781
Test name
Test status
Simulation time 1117047774 ps
CPU time 23.19 seconds
Started May 14 12:46:04 PM PDT 24
Finished May 14 12:46:29 PM PDT 24
Peak memory 204256 kb
Host smart-8af546ec-c8ef-4a10-ad6b-e79dfdbcf495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393068823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1393068823
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.4158441478
Short name T1145
Test name
Test status
Simulation time 5580696341 ps
CPU time 23.57 seconds
Started May 14 12:46:10 PM PDT 24
Finished May 14 12:46:37 PM PDT 24
Peak memory 237032 kb
Host smart-5ba5b070-de86-4a0f-a41e-d2ff43de6108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158441478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.4158441478
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1181454927
Short name T266
Test name
Test status
Simulation time 46954068366 ps
CPU time 72.86 seconds
Started May 14 12:46:08 PM PDT 24
Finished May 14 12:47:23 PM PDT 24
Peak memory 1142880 kb
Host smart-8bb1d598-3e2e-482c-84f0-f65463748edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181454927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1181454927
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.821726414
Short name T486
Test name
Test status
Simulation time 40231687289 ps
CPU time 1003.33 seconds
Started May 14 12:46:07 PM PDT 24
Finished May 14 01:02:53 PM PDT 24
Peak memory 2455792 kb
Host smart-0cd367d3-71dd-4cda-879e-247bec6d08bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821726414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.821726414
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.4116303144
Short name T602
Test name
Test status
Simulation time 4599356248 ps
CPU time 6.57 seconds
Started May 14 12:46:05 PM PDT 24
Finished May 14 12:46:14 PM PDT 24
Peak memory 212684 kb
Host smart-c2c16d64-3a8b-4912-bac8-72b29859afe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116303144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.4116303144
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1493160890
Short name T14
Test name
Test status
Simulation time 2555063043 ps
CPU time 4.54 seconds
Started May 14 12:46:14 PM PDT 24
Finished May 14 12:46:21 PM PDT 24
Peak memory 204384 kb
Host smart-ed738f91-4249-45ae-8d77-1460d2b402f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493160890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1493160890
Directory /workspace/9.i2c_target_unexp_stop/latest
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