Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

164131

1

T5

538

T18

768

T51

96

ack

13986

1

T5

4

T18

24

T38

1

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	675	1			T5	1		T18	2		T33	1
high	36766	1			T5	117		T18	165		T33	2
med	66429	1			T5	211		T18	310		T33	2
sml	73594	1			T5	213		T18	311		T38	1
all_zero	653	1			T18	4		T51	1		T41	3

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89019

1

T5

269

T18

423

T38

1

auto[1]

89098

1

T5

273

T18

369

T33

16

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122526

1

T5

355

T18

535

T38

1

auto[1]

55591

1

T5

187

T18

257

T33

13

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170723

1

T5

542

T18

781

T38

1

auto[1]

7394

1

T18

11

T33

24

T56

24

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168387

1

T5

538

T18

769

T33

24

auto[1]

9730

1

T5

4

T18

23

T38

1

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169339

1

T5

541

T18

770

T38

1

auto[1]

8778

1

T5

1

T18

22

T33

11

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89019

1

T5

269

T18

423

T38

1

auto[1]

89098

1

T5

273

T18

369

T33

16

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122526

1

T5

355

T18

535

T38

1

auto[1]

55591

1

T5

187

T18

257

T33

13

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170723

1

T5

542

T18

781

T38

1

auto[1]

7394

1

T18

11

T33

24

T56

24

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168387

1

T5

538

T18

769

T33

24

auto[1]

9730

1

T5

4

T18

23

T38

1

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169339

1

T5

541

T18

770

T38

1

auto[1]

8778

1

T5

1

T18

22

T33

11

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T53

1

T139

1

T251

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T103

1

T252

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T253

1

T254

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

321

1

T18

1

T41

3

T255

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

142

1

T18

1

T67

2

T39

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

143

1

T18

1

T41

1

T39

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

531

1

T18

5

T67

2

T42

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

251

1

T18

1

T67

2

T43

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

274

1

T18

1

T39

2

T255

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

506

1

T41

1

T67

2

T64

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

250

1

T18

2

T41

1

T67

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

287

1

T18

2

T41

1

T67

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

5

1

T256

1

T257

1

T258

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T39

1

T37

1

T119

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

1

1

T139

1

-

-

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	52626	1			T5	175		T18	262		T51	29
write_address_byte	9730	1			T5	4		T18	23		T38	1
read_with_ack	2146	1			T33	13		T56	11		T41	4
read_with_nack	5248	1			T18	11		T33	11		T56	13
stop_byte	8778	1			T5	1		T18	22		T33	11
write_address_byte_nak	4903	1			T18	20		T41	13		T67	24
data_byte_nack	164131	1			T5	538		T18	768		T51	96
stop_byte_nack	5352	1			T5	1		T18	19		T51	1
nakok_byte_nack	82011	1			T5	271		T18	357		T51	49
nakok_addr_byte_nack	2469	1			T18	7		T41	6		T67	16