Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 42172920 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 10189695 1 T1 290 T2 101 T3 290



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 51424582 1 T1 14216 T2 480 T3 649349
values[0x0] 468861 1 T1 152 T2 69 T3 173
values[0x1] 469172 1 T1 180 T2 84 T3 182



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 30153024 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22209591 1 T1 6482 T2 299 T3 162797



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 190690 1 T1 36 T3 2727 T5 418
valid_sources[0x01] 268658 1 T1 49 T2 2 T3 2532
valid_sources[0x02] 204012 1 T1 52 T2 2 T3 2695
valid_sources[0x03] 182402 1 T1 49 T2 7 T3 2417
valid_sources[0x04] 184733 1 T1 57 T2 3 T3 2323
valid_sources[0x05] 197392 1 T1 48 T2 8 T3 2348
valid_sources[0x06] 189015 1 T1 70 T2 1 T3 2626
valid_sources[0x07] 198292 1 T1 67 T2 2 T3 2662
valid_sources[0x08] 202385 1 T1 59 T2 4 T3 2682
valid_sources[0x09] 221027 1 T1 55 T2 6 T3 2557
valid_sources[0x0a] 326151 1 T1 50 T2 13 T3 2580
valid_sources[0x0b] 191706 1 T1 81 T3 2542 T5 346
valid_sources[0x0c] 192607 1 T1 62 T2 3 T3 2522
valid_sources[0x0d] 206522 1 T1 66 T2 1 T3 2440
valid_sources[0x0e] 200995 1 T1 61 T2 5 T3 2532
valid_sources[0x0f] 203586 1 T1 57 T2 9 T3 2618
valid_sources[0x10] 366665 1 T1 39 T3 2449 T5 367
valid_sources[0x11] 194262 1 T1 54 T2 1 T3 2688
valid_sources[0x12] 185764 1 T1 44 T3 2545 T5 396
valid_sources[0x13] 188302 1 T1 67 T3 2537 T5 405
valid_sources[0x14] 208984 1 T1 52 T2 7 T3 2657
valid_sources[0x15] 207841 1 T1 37 T2 1 T3 2427
valid_sources[0x16] 299711 1 T1 51 T2 7 T3 2431
valid_sources[0x17] 190483 1 T1 60 T3 2522 T5 390
valid_sources[0x18] 198416 1 T1 76 T2 1 T3 2574
valid_sources[0x19] 183679 1 T1 40 T2 10 T3 2478
valid_sources[0x1a] 202448 1 T1 37 T2 2 T3 2616
valid_sources[0x1b] 179224 1 T1 39 T2 2 T3 2467
valid_sources[0x1c] 308539 1 T1 50 T2 1 T3 2428
valid_sources[0x1d] 187060 1 T1 45 T2 3 T3 2593
valid_sources[0x1e] 194683 1 T1 50 T2 9 T3 2467
valid_sources[0x1f] 205122 1 T1 49 T2 1 T3 2390
valid_sources[0x20] 195495 1 T1 41 T2 2 T3 2719
valid_sources[0x21] 194645 1 T1 70 T2 3 T3 2608
valid_sources[0x22] 222297 1 T1 55 T2 9 T3 2625
valid_sources[0x23] 176907 1 T1 61 T2 17 T3 2596
valid_sources[0x24] 183119 1 T1 58 T2 5 T3 2615
valid_sources[0x25] 181971 1 T1 52 T2 1 T3 2316
valid_sources[0x26] 193175 1 T1 44 T3 2686 T5 319
valid_sources[0x27] 203269 1 T1 75 T2 10 T3 2617
valid_sources[0x28] 211425 1 T1 55 T2 7 T3 2524
valid_sources[0x29] 182031 1 T1 50 T2 2 T3 2466
valid_sources[0x2a] 330319 1 T1 74 T2 3 T3 2384
valid_sources[0x2b] 176808 1 T1 47 T2 1 T3 2622
valid_sources[0x2c] 194051 1 T1 53 T3 2529 T5 397
valid_sources[0x2d] 183662 1 T1 61 T2 2 T3 2659
valid_sources[0x2e] 183271 1 T1 58 T2 3 T3 2623
valid_sources[0x2f] 201204 1 T1 56 T3 2616 T5 420
valid_sources[0x30] 196116 1 T1 63 T3 2563 T5 459
valid_sources[0x31] 186311 1 T1 59 T2 3 T3 2498
valid_sources[0x32] 202618 1 T1 83 T3 2575 T5 237
valid_sources[0x33] 212555 1 T1 59 T3 2448 T5 415
valid_sources[0x34] 182880 1 T1 41 T2 1 T3 2504
valid_sources[0x35] 257371 1 T1 24 T2 4 T3 2557
valid_sources[0x36] 222706 1 T1 41 T3 2467 T5 290
valid_sources[0x37] 192614 1 T1 38 T2 2 T3 2567
valid_sources[0x38] 201300 1 T1 55 T2 1 T3 2579
valid_sources[0x39] 194172 1 T1 57 T2 1 T3 2562
valid_sources[0x3a] 182827 1 T1 61 T2 1 T3 2550
valid_sources[0x3b] 186712 1 T1 53 T2 1 T3 2467
valid_sources[0x3c] 499269 1 T1 57 T2 1 T3 2728
valid_sources[0x3d] 196694 1 T1 39 T3 2668 T5 320
valid_sources[0x3e] 193824 1 T1 51 T2 5 T3 2617
valid_sources[0x3f] 192759 1 T1 71 T2 6 T3 2504
valid_sources[0x40] 190955 1 T1 82 T2 2 T3 2549
valid_sources[0x41] 188512 1 T1 61 T2 13 T3 2523
valid_sources[0x42] 187155 1 T1 81 T2 4 T3 2469
valid_sources[0x43] 196606 1 T1 63 T2 3 T3 2581
valid_sources[0x44] 188322 1 T1 80 T3 2526 T5 404
valid_sources[0x45] 188518 1 T1 56 T2 5 T3 2437
valid_sources[0x46] 189679 1 T1 49 T2 1 T3 2575
valid_sources[0x47] 193039 1 T1 58 T3 2629 T5 314
valid_sources[0x48] 184734 1 T1 67 T3 2618 T5 367
valid_sources[0x49] 181194 1 T1 52 T2 2 T3 2365
valid_sources[0x4a] 193096 1 T1 57 T3 2624 T5 280
valid_sources[0x4b] 185808 1 T1 63 T2 3 T3 2535
valid_sources[0x4c] 194839 1 T1 46 T2 1 T3 2398
valid_sources[0x4d] 186862 1 T1 47 T2 1 T3 2302
valid_sources[0x4e] 177125 1 T1 51 T3 2566 T5 394
valid_sources[0x4f] 184543 1 T1 43 T3 2700 T5 359
valid_sources[0x50] 182103 1 T1 49 T2 2 T3 2460
valid_sources[0x51] 193967 1 T1 71 T3 2635 T5 316
valid_sources[0x52] 192671 1 T1 76 T2 5 T3 2442
valid_sources[0x53] 181673 1 T1 57 T2 7 T3 2524
valid_sources[0x54] 184047 1 T1 60 T2 3 T3 2408
valid_sources[0x55] 184318 1 T1 55 T2 3 T3 2364
valid_sources[0x56] 206120 1 T1 66 T3 2506 T5 340
valid_sources[0x57] 318559 1 T1 63 T2 3 T3 2484
valid_sources[0x58] 182843 1 T1 33 T2 2 T3 2400
valid_sources[0x59] 191807 1 T1 56 T3 2416 T5 414
valid_sources[0x5a] 191885 1 T1 76 T3 2547 T5 389
valid_sources[0x5b] 181562 1 T1 50 T2 1 T3 2483
valid_sources[0x5c] 334283 1 T1 42 T3 2483 T5 324
valid_sources[0x5d] 192225 1 T1 58 T2 6 T3 2481
valid_sources[0x5e] 190631 1 T1 73 T3 2708 T5 378
valid_sources[0x5f] 417101 1 T1 27 T3 2421 T5 365
valid_sources[0x60] 202464 1 T1 86 T2 3 T3 2526
valid_sources[0x61] 190028 1 T1 77 T3 2499 T5 385
valid_sources[0x62] 205659 1 T1 89 T3 2654 T5 349
valid_sources[0x63] 309219 1 T1 58 T2 13 T3 2634
valid_sources[0x64] 184759 1 T1 58 T3 2587 T5 382
valid_sources[0x65] 219175 1 T1 66 T3 2563 T5 405
valid_sources[0x66] 210192 1 T1 73 T2 5 T3 2359
valid_sources[0x67] 185651 1 T1 58 T3 2735 T5 345
valid_sources[0x68] 190325 1 T1 52 T2 2 T3 2734
valid_sources[0x69] 208984 1 T1 55 T3 2580 T5 384
valid_sources[0x6a] 274084 1 T1 52 T2 1 T3 2581
valid_sources[0x6b] 189534 1 T1 81 T2 2 T3 2598
valid_sources[0x6c] 244758 1 T1 50 T3 2524 T5 452
valid_sources[0x6d] 210092 1 T1 69 T2 2 T3 2525
valid_sources[0x6e] 215348 1 T1 53 T2 3 T3 2634
valid_sources[0x6f] 193449 1 T1 42 T2 4 T3 2544
valid_sources[0x70] 182049 1 T1 49 T3 2440 T5 332
valid_sources[0x71] 219977 1 T1 60 T2 9 T3 2543
valid_sources[0x72] 199530 1 T1 65 T3 2438 T5 396
valid_sources[0x73] 213452 1 T1 44 T3 2606 T5 346
valid_sources[0x74] 184509 1 T1 56 T2 2 T3 2516
valid_sources[0x75] 194981 1 T1 50 T2 2 T3 2399
valid_sources[0x76] 195058 1 T1 64 T2 7 T3 2611
valid_sources[0x77] 194683 1 T1 56 T2 3 T3 2521
valid_sources[0x78] 197210 1 T1 57 T3 2587 T5 386
valid_sources[0x79] 187007 1 T1 58 T3 2520 T5 336
valid_sources[0x7a] 184045 1 T1 74 T2 2 T3 2548
valid_sources[0x7b] 201322 1 T1 42 T2 1 T3 2515
valid_sources[0x7c] 188163 1 T1 52 T2 3 T3 2590
valid_sources[0x7d] 175708 1 T1 65 T2 10 T3 2491
valid_sources[0x7e] 210565 1 T1 67 T2 1 T3 2468
valid_sources[0x7f] 199180 1 T1 42 T2 6 T3 2601
valid_sources[0x80] 192134 1 T1 70 T3 2301 T5 412



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 9768774 1 T1 176 T2 47 T3 199
values[0x0] all_enables biggest_size 246964 1 T1 61 T2 37 T3 53
values[0x1] all_enables biggest_size 173957 1 T1 53 T2 17 T3 38

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%