SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
i2c_env_pkg.b2b_txn_host_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c_env_pkg.b2b_txn_target_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
B2B_txn_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 3284 | 1 | T18 | 4 | T33 | 5 | T56 | 12 | ||||
b2b_read_same_addr | 299 | 1 | T56 | 1 | T42 | 3 | T43 | 4 | ||||
write_after_read_different_addr | 3279 | 1 | T18 | 5 | T33 | 7 | T56 | 7 | ||||
write_after_read_same_addr | 56 | 1 | T34 | 1 | T39 | 1 | T264 | 1 | ||||
read_after_write_different_addr | 3296 | 1 | T5 | 1 | T18 | 6 | T33 | 7 | ||||
read_after_write_same_addr | 44 | 1 | T41 | 1 | T34 | 1 | T37 | 2 | ||||
b2b_write_different_addr | 3214 | 1 | T18 | 8 | T33 | 15 | T56 | 8 | ||||
b2b_write_same_addr | 233 | 1 | T5 | 2 | T41 | 2 | T42 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
b2b_read_different_addr | 307 | 1 | T11 | 27 | T114 | 2 | T265 | 7 | ||||
b2b_read_same_addr | 576 | 1 | T6 | 1 | T31 | 11 | T11 | 19 | ||||
write_after_read_different_addr | 14730 | 1 | T2 | 7 | T3 | 12 | T6 | 11 | ||||
write_after_read_same_addr | 121 | 1 | T266 | 15 | T267 | 16 | T268 | 20 | ||||
read_after_write_different_addr | 14719 | 1 | T2 | 7 | T3 | 12 | T6 | 11 | ||||
read_after_write_same_addr | 121 | 1 | T266 | 15 | T267 | 16 | T268 | 20 | ||||
b2b_write_different_addr | 26069 | 1 | T1 | 76 | T2 | 12 | T3 | 27 | ||||
b2b_write_same_addr | 232299 | 1 | T1 | 357 | T2 | 82 | T3 | 358 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |