Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	427249693	0	0	0
ctrl_rd_A	427249693	3075	0	0
host_fifo_config_rd_A	427249693	5969	0	0
host_nack_handler_timeout_rd_A	427249693	2074	0	0
host_timeout_ctrl_rd_A	427249693	1666	0	0
intr_enable_rd_A	427249693	4798	0	0
ovrd_rd_A	427249693	3214	0	0
target_fifo_config_rd_A	427249693	1797	0	0
target_id_rd_A	427249693	2465	0	0
target_timeout_ctrl_rd_A	427249693	1980	0	0
timeout_ctrl_rd_A	427249693	2066	0	0
timing0_rd_A	427249693	1958	0	0
timing1_rd_A	427249693	1956	0	0
timing2_rd_A	427249693	1885	0	0
timing3_rd_A	427249693	1887	0	0
timing4_rd_A	427249693	1749	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	3075	0	0
T92	3689	72	0	0
T93	5463	14	0	0
T94	1572	31	0	0
T95	2194	14	0	0
T96	3645	22	0	0
T97	11313	9	0	0
T98	5535	21	0	0
T99	3940	23	0	0
T100	14648	52	0	0
T101	6163	13	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	5969	0	0
T46	225499	0	0	0
T76	1990	0	0	0
T102	105393	114	0	0
T103	211231	347	0	0
T104	0	236	0	0
T105	0	146	0	0
T106	0	159	0	0
T107	0	129	0	0
T108	0	87	0	0
T109	0	74	0	0
T110	0	256	0	0
T111	0	157	0	0
T112	218633	0	0	0
T113	21881	0	0	0
T114	242723	0	0	0
T115	9955	0	0	0
T116	246961	0	0	0
T117	244483	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	2074	0	0
T92	3689	17	0	0
T93	5463	29	0	0
T94	1572	3	0	0
T95	2194	13	0	0
T96	3645	13	0	0
T97	11313	5	0	0
T98	5535	5	0	0
T99	3940	17	0	0
T100	14648	47	0	0
T101	6163	73	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1666	0	0
T92	3689	6	0	0
T93	5463	12	0	0
T94	1572	3	0	0
T95	2194	4	0	0
T96	3645	9	0	0
T97	11313	34	0	0
T98	5535	5	0	0
T99	3940	10	0	0
T100	14648	80	0	0
T118	3867	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	4798	0	0
T46	225499	0	0	0
T52	0	21	0	0
T76	1990	0	0	0
T92	0	53	0	0
T102	105393	39	0	0
T103	211231	0	0	0
T112	218633	0	0	0
T113	21881	0	0	0
T114	242723	0	0	0
T115	9955	0	0	0
T116	246961	0	0	0
T117	244483	0	0	0
T119	0	13	0	0
T120	0	1	0	0
T121	0	10	0	0
T122	0	9	0	0
T123	0	11	0	0
T124	0	38	0	0
T125	0	12	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	3214	0	0
T126	2023	58	0	0
T127	0	29	0	0
T128	0	33	0	0
T129	0	21	0	0
T130	0	34	0	0
T131	0	17	0	0
T132	0	64	0	0
T133	0	39	0	0
T134	0	45	0	0
T135	0	59	0	0
T136	173341	0	0	0
T137	149214	0	0	0
T138	523740	0	0	0
T139	492539	0	0	0
T140	286304	0	0	0
T141	1746	0	0	0
T142	182619	0	0	0
T143	133206	0	0	0
T144	164731	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1797	0	0
T92	3689	30	0	0
T93	5463	7	0	0
T94	1572	4	0	0
T95	2194	7	0	0
T96	3645	6	0	0
T97	11313	8	0	0
T98	5535	14	0	0
T99	3940	1	0	0
T100	14648	13	0	0
T118	3867	1	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	2465	0	0
T92	3689	16	0	0
T93	5463	16	0	0
T94	1572	7	0	0
T96	3645	20	0	0
T97	11313	9	0	0
T98	5535	11	0	0
T99	3940	39	0	0
T100	14648	55	0	0
T101	6163	37	0	0
T145	2887	10	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1980	0	0
T92	3689	18	0	0
T93	5463	7	0	0
T94	1572	11	0	0
T95	2194	15	0	0
T96	3645	4	0	0
T97	11313	21	0	0
T98	5535	8	0	0
T99	3940	25	0	0
T100	14648	38	0	0
T101	6163	44	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	2066	0	0
T92	3689	28	0	0
T93	5463	12	0	0
T95	2194	7	0	0
T96	3645	14	0	0
T97	11313	23	0	0
T98	5535	15	0	0
T99	3940	18	0	0
T100	14648	34	0	0
T101	6163	43	0	0
T118	3867	9	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1958	0	0
T92	3689	30	0	0
T93	5463	3	0	0
T94	1572	6	0	0
T95	2194	12	0	0
T96	3645	7	0	0
T97	11313	2	0	0
T99	3940	28	0	0
T100	14648	32	0	0
T101	6163	39	0	0
T118	3867	2	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1956	0	0
T92	3689	15	0	0
T93	5463	12	0	0
T94	1572	4	0	0
T95	2194	8	0	0
T96	3645	2	0	0
T97	11313	12	0	0
T98	5535	4	0	0
T99	3940	37	0	0
T100	14648	57	0	0
T118	3867	2	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1885	0	0
T92	3689	18	0	0
T93	5463	3	0	0
T94	1572	6	0	0
T95	2194	4	0	0
T96	3645	1	0	0
T97	11313	20	0	0
T98	5535	13	0	0
T99	3940	21	0	0
T100	14648	19	0	0
T101	6163	50	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1887	0	0
T92	3689	30	0	0
T93	5463	11	0	0
T94	1572	5	0	0
T95	2194	8	0	0
T96	3645	1	0	0
T97	11313	12	0	0
T98	5535	1	0	0
T99	3940	28	0	0
T100	14648	45	0	0
T118	3867	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427249693	1749	0	0
T92	3689	14	0	0
T93	5463	30	0	0
T95	2194	2	0	0
T96	3645	2	0	0
T97	11313	18	0	0
T98	5535	11	0	0
T99	3940	15	0	0
T100	14648	31	0	0
T101	6163	54	0	0
T146	5741	40	0	0