Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

160191

1

T2

9

T49

198

T40

34

ack

14416

1

T2

4

T5

38

T54

19

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	597	1			T37	8		T45	3		T155	1
high	35835	1			T2	2		T5	4		T54	1
med	65042	1			T2	2		T5	4		T54	3
sml	72480	1			T2	9		T5	30		T54	15
all_zero	653	1			T49	2		T37	3		T67	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87300

1

T2

4

T5

18

T54

9

auto[1]

87307

1

T2

9

T5

20

T54

10

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120133

1

T2

9

T5

24

T54

19

auto[1]

54474

1

T2

4

T5

14

T49

65

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166938

1

T2

7

T5

12

T54

10

auto[1]

7669

1

T2

6

T5

26

T54

9

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164792

1

T2

9

T5

26

T54

9

auto[1]

9815

1

T2

4

T5

12

T54

10

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165790

1

T2

10

T5

26

T54

10

auto[1]

8817

1

T2

3

T5

12

T54

9

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87300

1

T2

4

T5

18

T54

9

auto[1]

87307

1

T2

9

T5

20

T54

10

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120133

1

T2

9

T5

24

T54

19

auto[1]

54474

1

T2

4

T5

14

T49

65

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166938

1

T2

7

T5

12

T54

10

auto[1]

7669

1

T2

6

T5

26

T54

9

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164792

1

T2

9

T5

26

T54

9

auto[1]

9815

1

T2

4

T5

12

T54

10

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165790

1

T2

10

T5

26

T54

10

auto[1]

8817

1

T2

3

T5

12

T54

9

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T254

1

T255

1

T256

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T257

1

T258

1

T259

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T106

1

T126

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

260

1

T49

1

T37

1

T67

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

142

1

T49

1

T37

1

T45

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

139

1

T49

1

T37

2

T67

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

489

1

T2

1

T49

1

T37

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

254

1

T49

3

T37

2

T67

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

234

1

T49

1

T37

1

T67

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

543

1

T49

3

T37

6

T67

4

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

244

1

T49

1

T37

2

T67

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

245

1

T2

1

T49

1

T37

1

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T49

1

T260

1

T261

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T111

1

T262

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T263

1

T107

1

T111

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51279	1			T49	49		T40	12		T37	383
write_address_byte	9815	1			T2	4		T5	12		T54	10
read_with_ack	2331	1			T2	3		T5	14		T37	3
read_with_nack	5338	1			T2	3		T5	12		T54	9
stop_byte	8817	1			T2	3		T5	12		T54	9
write_address_byte_nak	4781	1			T2	3		T49	26		T37	34
data_byte_nack	160191	1			T2	9		T49	198		T40	34
stop_byte_nack	5258	1			T2	3		T49	26		T40	2
nakok_byte_nack	80118	1			T2	5		T49	105		T40	15
nakok_addr_byte_nack	2408	1			T2	2		T49	15		T37	15