Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41940640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10674053

1

T1

140

T2

643

T3

903

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51644749	1			T1	64970		T2	2123		T3	1762
values[0x0]	484524	1			T1	105		T2	78		T3	11
values[0x1]	485420	1			T1	90		T2	59		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29940329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22674364

1

T1

16565

T2

1095

T3

1080

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	191456	1			T1	1		T2	29		T3	22
valid_sources[0x01]	321377	1			T1	2		T2	3		T3	14
valid_sources[0x02]	190400	1			T5	3		T6	1		T54	451
valid_sources[0x03]	221810	1			T2	8		T5	3		T8	9
valid_sources[0x04]	190133	1			T1	1		T2	9		T3	4
valid_sources[0x05]	199065	1			T1	1		T2	3		T3	1
valid_sources[0x06]	203393	1			T2	7		T5	160		T6	3
valid_sources[0x07]	232147	1			T1	1		T2	5		T3	3
valid_sources[0x08]	188296	1			T1	1		T2	15		T5	148
valid_sources[0x09]	208459	1			T1	2		T2	13		T5	1419
valid_sources[0x0a]	190651	1			T1	1		T2	3		T3	20
valid_sources[0x0b]	199897	1			T2	3		T3	8		T5	4
valid_sources[0x0c]	186363	1			T2	9		T5	4		T8	7
valid_sources[0x0d]	407475	1			T1	1		T2	16		T5	7
valid_sources[0x0e]	194806	1			T2	7		T3	29		T5	14
valid_sources[0x0f]	185923	1			T2	14		T5	4		T6	3
valid_sources[0x10]	193753	1			T2	3		T5	143		T54	326
valid_sources[0x11]	194111	1			T1	1		T2	1		T5	4
valid_sources[0x12]	192665	1			T1	1		T2	10		T5	4
valid_sources[0x13]	173981	1			T5	9		T6	4		T54	506
valid_sources[0x14]	211658	1			T1	2		T2	16		T5	8
valid_sources[0x15]	210707	1			T1	1		T2	22		T5	183
valid_sources[0x16]	226707	1			T1	2		T2	15		T3	13
valid_sources[0x17]	197266	1			T2	13		T3	22		T5	3
valid_sources[0x18]	190704	1			T2	14		T3	54		T5	1
valid_sources[0x19]	186835	1			T1	1		T2	5		T3	11
valid_sources[0x1a]	192328	1			T2	6		T5	4		T8	4
valid_sources[0x1b]	185266	1			T1	2		T2	12		T3	10
valid_sources[0x1c]	195642	1			T2	17		T3	20		T5	421
valid_sources[0x1d]	188720	1			T1	1		T5	12		T6	13
valid_sources[0x1e]	198435	1			T2	13		T3	22		T5	13
valid_sources[0x1f]	183988	1			T1	1		T2	29		T5	12
valid_sources[0x20]	208643	1			T1	3		T2	12		T3	1
valid_sources[0x21]	179783	1			T1	2		T2	13		T3	30
valid_sources[0x22]	188625	1			T1	1		T5	146		T54	453
valid_sources[0x23]	259970	1			T2	5		T3	22		T5	4
valid_sources[0x24]	177387	1			T1	1		T2	9		T5	11
valid_sources[0x25]	195352	1			T1	2		T2	2		T5	3
valid_sources[0x26]	177106	1			T1	1		T2	6		T3	12
valid_sources[0x27]	198786	1			T2	8		T5	3		T54	450
valid_sources[0x28]	190059	1			T2	2		T5	5		T54	501
valid_sources[0x29]	240212	1			T2	6		T3	28		T5	5
valid_sources[0x2a]	352642	1			T2	14		T5	5		T6	5
valid_sources[0x2b]	205858	1			T1	2		T2	1		T5	12
valid_sources[0x2c]	186966	1			T2	4		T3	13		T5	159
valid_sources[0x2d]	188320	1			T1	1		T2	5		T3	8
valid_sources[0x2e]	218456	1			T2	14		T4	1		T5	4
valid_sources[0x2f]	196038	1			T1	2		T2	5		T3	33
valid_sources[0x30]	193519	1			T2	3		T3	17		T5	10
valid_sources[0x31]	197827	1			T2	8		T3	9		T4	23
valid_sources[0x32]	213539	1			T2	1		T5	1		T6	15
valid_sources[0x33]	174628	1			T5	15		T54	490		T49	155
valid_sources[0x34]	213081	1			T1	1		T2	18		T5	3
valid_sources[0x35]	192878	1			T2	10		T4	1		T5	602
valid_sources[0x36]	198224	1			T2	2		T5	3		T6	2
valid_sources[0x37]	185030	1			T1	2		T2	14		T5	451
valid_sources[0x38]	198243	1			T1	1		T2	11		T5	10
valid_sources[0x39]	190797	1			T3	9		T5	5		T6	6
valid_sources[0x3a]	199158	1			T2	18		T3	22		T5	13
valid_sources[0x3b]	204187	1			T3	2		T5	4		T54	551
valid_sources[0x3c]	258021	1			T2	1		T3	6		T5	2
valid_sources[0x3d]	203217	1			T2	12		T5	302		T6	8
valid_sources[0x3e]	198028	1			T2	7		T3	14		T5	7
valid_sources[0x3f]	189267	1			T2	2		T5	863		T7	2
valid_sources[0x40]	204479	1			T2	1		T5	2		T6	1
valid_sources[0x41]	177273	1			T1	1		T2	3		T5	11
valid_sources[0x42]	196059	1			T2	17		T5	2		T6	9
valid_sources[0x43]	393809	1			T1	1		T2	18		T5	12
valid_sources[0x44]	294356	1			T1	64985		T2	4		T5	16
valid_sources[0x45]	185607	1			T2	6		T5	9		T6	7
valid_sources[0x46]	192675	1			T1	1		T2	16		T3	14
valid_sources[0x47]	185556	1			T1	3		T2	25		T3	32
valid_sources[0x48]	193207	1			T1	1		T2	9		T5	5
valid_sources[0x49]	184032	1			T2	2		T5	14		T6	2
valid_sources[0x4a]	216190	1			T1	1		T2	4		T3	7
valid_sources[0x4b]	179418	1			T2	17		T5	868		T6	2
valid_sources[0x4c]	190222	1			T2	4		T5	447		T6	8
valid_sources[0x4d]	179842	1			T1	2		T2	2		T3	22
valid_sources[0x4e]	223043	1			T1	1		T2	10		T5	6
valid_sources[0x4f]	227442	1			T2	9		T5	149		T54	431
valid_sources[0x50]	179037	1			T1	1		T2	11		T5	3
valid_sources[0x51]	186633	1			T1	2		T2	11		T5	3
valid_sources[0x52]	180097	1			T2	2		T3	9		T4	1
valid_sources[0x53]	198084	1			T3	19		T5	298		T6	5
valid_sources[0x54]	193505	1			T2	16		T3	89		T5	691
valid_sources[0x55]	190380	1			T2	4		T5	287		T6	3
valid_sources[0x56]	190432	1			T2	4		T4	4		T5	172
valid_sources[0x57]	258612	1			T1	1		T2	2		T5	12
valid_sources[0x58]	181248	1			T2	12		T5	4		T8	7
valid_sources[0x59]	188632	1			T2	19		T5	293		T6	1
valid_sources[0x5a]	178697	1			T1	1		T2	12		T3	24
valid_sources[0x5b]	198327	1			T2	4		T5	149		T54	513
valid_sources[0x5c]	192157	1			T1	1		T2	5		T4	2
valid_sources[0x5d]	190387	1			T2	14		T5	2		T6	1
valid_sources[0x5e]	327171	1			T2	25		T5	6		T6	1
valid_sources[0x5f]	174724	1			T2	14		T5	4		T6	4
valid_sources[0x60]	205315	1			T5	7		T8	1		T54	495
valid_sources[0x61]	199765	1			T1	2		T2	12		T5	10
valid_sources[0x62]	202224	1			T2	2		T3	12		T5	14
valid_sources[0x63]	182468	1			T1	3		T2	6		T5	298
valid_sources[0x64]	206885	1			T1	1		T2	8		T3	8
valid_sources[0x65]	177505	1			T1	1		T2	2		T5	6
valid_sources[0x66]	196629	1			T2	7		T5	4		T54	361
valid_sources[0x67]	271550	1			T1	1		T2	7		T5	4
valid_sources[0x68]	180289	1			T1	1		T2	11		T3	37
valid_sources[0x69]	205165	1			T1	4		T2	22		T5	17
valid_sources[0x6a]	203159	1			T2	19		T5	5		T6	4
valid_sources[0x6b]	208837	1			T2	28		T5	8		T6	1
valid_sources[0x6c]	185502	1			T5	6		T6	1		T8	2
valid_sources[0x6d]	181157	1			T1	1		T2	2		T5	11
valid_sources[0x6e]	184619	1			T2	3		T5	4		T6	3
valid_sources[0x6f]	260349	1			T1	1		T2	3		T5	172
valid_sources[0x70]	186834	1			T2	35		T3	2		T5	12
valid_sources[0x71]	203119	1			T2	3		T5	4		T6	1
valid_sources[0x72]	181471	1			T1	1		T2	10		T5	3
valid_sources[0x73]	214062	1			T2	1		T5	156		T8	25
valid_sources[0x74]	184525	1			T1	1		T2	14		T5	432
valid_sources[0x75]	186509	1			T1	3		T5	9		T8	17
valid_sources[0x76]	182943	1			T1	1		T2	8		T5	2
valid_sources[0x77]	207805	1			T2	6		T5	739		T8	10
valid_sources[0x78]	200721	1			T1	2		T3	79		T5	23
valid_sources[0x79]	184984	1			T3	17		T5	5		T6	3
valid_sources[0x7a]	197959	1			T2	3		T3	60		T5	10
valid_sources[0x7b]	212725	1			T2	4		T5	4		T6	3
valid_sources[0x7c]	461551	1			T2	13		T3	49		T5	2
valid_sources[0x7d]	291102	1			T2	15		T5	1		T6	4
valid_sources[0x7e]	198222	1			T1	2		T2	11		T4	45
valid_sources[0x7f]	194505	1			T2	6		T3	21		T5	3
valid_sources[0x80]	202711	1			T1	2		T2	11		T5	161

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10238479

1

T1

78

T2

565

T3

893

values[0x0]

all_enables

biggest_size

255151

1

T1

41

T2

52

T3

7

values[0x1]

all_enables

biggest_size

180423

1

T1

21

T2

26

T3

3