Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	427817992	0	0	0
ctrl_rd_A	427817992	1851	0	0
host_fifo_config_rd_A	427817992	5007	0	0
host_nack_handler_timeout_rd_A	427817992	1032	0	0
host_timeout_ctrl_rd_A	427817992	914	0	0
intr_enable_rd_A	427817992	3376	0	0
ovrd_rd_A	427817992	1713	0	0
target_fifo_config_rd_A	427817992	1014	0	0
target_id_rd_A	427817992	1326	0	0
target_timeout_ctrl_rd_A	427817992	1113	0	0
timeout_ctrl_rd_A	427817992	1168	0	0
timing0_rd_A	427817992	1125	0	0
timing1_rd_A	427817992	1085	0	0
timing2_rd_A	427817992	1039	0	0
timing3_rd_A	427817992	1074	0	0
timing4_rd_A	427817992	991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1851	0	0
T94	6760	59	0	0
T95	3056	16	0	0
T96	6889	87	0	0
T97	2318	20	0	0
T98	3079	31	0	0
T99	14424	202	0	0
T100	3395	36	0	0
T101	2164	12	0	0
T102	12861	30	0	0
T103	2712	52	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	5007	0	0
T19	299029	0	0	0
T48	740452	198	0	0
T104	0	163	0	0
T105	0	80	0	0
T106	0	236	0	0
T107	0	117	0	0
T108	0	103	0	0
T109	0	154	0	0
T110	0	132	0	0
T111	0	431	0	0
T112	0	156	0	0
T113	11650	0	0	0
T114	94517	0	0	0
T115	221018	0	0	0
T116	6193	0	0	0
T117	529750	0	0	0
T118	2776	0	0	0
T119	130164	0	0	0
T120	16396	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1032	0	0
T94	6760	48	0	0
T95	3056	4	0	0
T96	6889	29	0	0
T98	3079	45	0	0
T99	14424	67	0	0
T100	3395	30	0	0
T102	12861	21	0	0
T103	2712	19	0	0
T121	8203	31	0	0
T122	4284	38	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	914	0	0
T94	6760	68	0	0
T95	3056	4	0	0
T96	6889	53	0	0
T97	2318	7	0	0
T98	3079	13	0	0
T99	14424	51	0	0
T100	3395	22	0	0
T101	2164	7	0	0
T102	12861	21	0	0
T103	2712	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	3376	0	0
T19	299029	0	0	0
T48	740452	7	0	0
T104	0	19	0	0
T111	0	13	0	0
T112	0	10	0	0
T113	11650	0	0	0
T114	94517	0	0	0
T115	221018	0	0	0
T116	6193	0	0	0
T117	529750	0	0	0
T118	2776	0	0	0
T119	130164	0	0	0
T120	16396	0	0	0
T123	0	46	0	0
T124	0	10	0	0
T125	0	8	0	0
T126	0	7	0	0
T127	0	24	0	0
T128	0	13	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1713	0	0
T35	220775	0	0	0
T129	1284	42	0	0
T130	0	29	0	0
T131	0	53	0	0
T132	0	44	0	0
T133	0	40	0	0
T134	0	24	0	0
T135	0	75	0	0
T136	0	28	0	0
T137	0	34	0	0
T138	0	25	0	0
T139	45198	0	0	0
T140	48451	0	0	0
T141	104970	0	0	0
T142	32068	0	0	0
T143	78837	0	0	0
T144	190120	0	0	0
T145	1942	0	0	0
T146	707260	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1014	0	0
T94	6760	89	0	0
T95	3056	18	0	0
T96	6889	36	0	0
T97	2318	13	0	0
T98	3079	16	0	0
T99	14424	55	0	0
T100	3395	17	0	0
T101	2164	2	0	0
T102	12861	22	0	0
T103	2712	15	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1326	0	0
T94	6760	42	0	0
T95	3056	30	0	0
T96	6889	31	0	0
T97	2318	12	0	0
T98	3079	31	0	0
T99	14424	91	0	0
T100	3395	28	0	0
T101	2164	13	0	0
T103	2712	18	0	0
T121	8203	81	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1113	0	0
T94	6760	84	0	0
T95	3056	29	0	0
T96	6889	68	0	0
T97	2318	4	0	0
T98	3079	17	0	0
T99	14424	70	0	0
T100	3395	27	0	0
T101	2164	9	0	0
T102	12861	11	0	0
T103	2712	10	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1168	0	0
T94	6760	43	0	0
T95	3056	20	0	0
T96	6889	45	0	0
T97	2318	18	0	0
T98	3079	31	0	0
T99	14424	134	0	0
T100	3395	22	0	0
T101	2164	9	0	0
T102	12861	2	0	0
T103	2712	9	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1125	0	0
T94	6760	60	0	0
T95	3056	8	0	0
T96	6889	41	0	0
T97	2318	9	0	0
T98	3079	21	0	0
T99	14424	65	0	0
T100	3395	21	0	0
T101	2164	9	0	0
T102	12861	55	0	0
T103	2712	6	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1085	0	0
T94	6760	37	0	0
T95	3056	18	0	0
T96	6889	26	0	0
T97	2318	5	0	0
T98	3079	28	0	0
T99	14424	61	0	0
T100	3395	23	0	0
T101	2164	6	0	0
T102	12861	22	0	0
T103	2712	6	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1039	0	0
T94	6760	35	0	0
T95	3056	7	0	0
T96	6889	33	0	0
T97	2318	5	0	0
T98	3079	18	0	0
T99	14424	84	0	0
T100	3395	24	0	0
T101	2164	5	0	0
T102	12861	8	0	0
T103	2712	14	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	1074	0	0
T94	6760	75	0	0
T96	6889	35	0	0
T98	3079	13	0	0
T99	14424	43	0	0
T100	3395	11	0	0
T101	2164	11	0	0
T102	12861	16	0	0
T103	2712	17	0	0
T121	8203	69	0	0
T122	4284	17	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427817992	991	0	0
T94	6760	40	0	0
T95	3056	12	0	0
T96	6889	76	0	0
T97	2318	8	0	0
T98	3079	17	0	0
T99	14424	71	0	0
T100	3395	19	0	0
T101	2164	11	0	0
T102	12861	10	0	0
T103	2712	9	0	0