Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48302792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11412223

1

T1

177

T2

10

T3

534

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58722850	1			T1	370		T2	17		T3	1022
values[0x0]	496016	1			T1	100		T2	7		T3	327
values[0x1]	496149	1			T1	99		T2	9		T3	313

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34380437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25334578

1

T1

304

T2

13

T3

839

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	223284	1			T1	5		T3	39		T4	5
valid_sources[0x01]	217721	1			T1	1		T4	10		T5	38
valid_sources[0x02]	464821	1			T1	2		T5	35		T7	4
valid_sources[0x03]	213358	1			T1	2		T5	55		T7	2
valid_sources[0x04]	218354	1			T1	1		T4	41		T5	67
valid_sources[0x05]	216836	1			T1	1		T4	8		T5	44
valid_sources[0x06]	361968	1			T1	6		T5	23		T7	6
valid_sources[0x07]	271163	1			T1	4		T3	29		T4	3
valid_sources[0x08]	210473	1			T5	129		T7	5		T8	256
valid_sources[0x09]	236780	1			T1	3		T5	100		T7	1
valid_sources[0x0a]	223787	1			T1	2		T5	137		T7	1
valid_sources[0x0b]	724697	1			T1	2		T4	20		T5	35
valid_sources[0x0c]	216437	1			T1	5		T5	27		T7	3
valid_sources[0x0d]	200644	1			T1	4		T5	66		T7	1
valid_sources[0x0e]	228593	1			T1	3		T4	7		T5	35
valid_sources[0x0f]	204780	1			T1	1		T2	1		T3	12
valid_sources[0x10]	211662	1			T1	1		T5	36		T7	6
valid_sources[0x11]	208698	1			T1	2		T5	58		T7	3
valid_sources[0x12]	233131	1			T5	41		T7	1303		T8	230
valid_sources[0x13]	205696	1			T1	3		T5	76		T7	4
valid_sources[0x14]	226854	1			T1	1		T4	24		T5	92
valid_sources[0x15]	229159	1			T1	3		T3	14		T5	94
valid_sources[0x16]	214231	1			T1	5		T3	53		T5	28
valid_sources[0x17]	222190	1			T1	4		T5	21		T7	3
valid_sources[0x18]	211149	1			T1	2		T3	25		T5	109
valid_sources[0x19]	231387	1			T1	4		T5	91		T7	4
valid_sources[0x1a]	212311	1			T1	1		T3	1		T5	22
valid_sources[0x1b]	219308	1			T5	50		T7	6		T8	236
valid_sources[0x1c]	321441	1			T1	6		T5	39		T7	3
valid_sources[0x1d]	217205	1			T4	13		T5	139		T7	2
valid_sources[0x1e]	235302	1			T1	7		T4	9		T5	42
valid_sources[0x1f]	224833	1			T1	3		T5	30		T7	2
valid_sources[0x20]	223206	1			T1	1		T4	3		T5	62
valid_sources[0x21]	207763	1			T1	1		T2	1		T5	67
valid_sources[0x22]	219270	1			T4	16		T5	46		T7	2
valid_sources[0x23]	208227	1			T1	2		T5	59		T7	5
valid_sources[0x24]	244593	1			T1	7		T2	1		T5	43
valid_sources[0x25]	224535	1			T1	4		T5	36		T7	3
valid_sources[0x26]	217539	1			T1	2		T5	74		T7	9
valid_sources[0x27]	214497	1			T1	1		T5	39		T7	4
valid_sources[0x28]	215026	1			T1	3		T3	7		T5	94
valid_sources[0x29]	215930	1			T1	4		T3	13		T5	66
valid_sources[0x2a]	210589	1			T1	3		T4	4		T5	86
valid_sources[0x2b]	215819	1			T1	4		T5	52		T7	3
valid_sources[0x2c]	211180	1			T1	2		T5	90		T7	3
valid_sources[0x2d]	250237	1			T3	1		T4	4		T5	62
valid_sources[0x2e]	319294	1			T1	1		T3	3		T5	57
valid_sources[0x2f]	218122	1			T1	7		T4	9		T5	43
valid_sources[0x30]	222468	1			T1	2		T3	9		T5	103
valid_sources[0x31]	210705	1			T1	2		T5	54		T7	6
valid_sources[0x32]	218470	1			T1	1		T4	13		T5	47
valid_sources[0x33]	225740	1			T1	2		T5	28		T7	3
valid_sources[0x34]	227733	1			T5	80		T7	5		T8	175
valid_sources[0x35]	238484	1			T1	1		T2	1		T5	111
valid_sources[0x36]	218532	1			T5	67		T7	2		T8	250
valid_sources[0x37]	251186	1			T1	3		T2	2		T4	4
valid_sources[0x38]	234319	1			T1	2		T5	142		T7	2
valid_sources[0x39]	216664	1			T1	2		T4	5		T5	5
valid_sources[0x3a]	212829	1			T4	25		T5	59		T7	1431
valid_sources[0x3b]	217071	1			T5	45		T7	4		T8	216
valid_sources[0x3c]	218276	1			T5	28		T7	6		T8	210
valid_sources[0x3d]	202324	1			T1	2		T5	126		T7	4
valid_sources[0x3e]	226039	1			T1	1		T3	50		T5	79
valid_sources[0x3f]	218393	1			T1	6		T5	20		T7	3
valid_sources[0x40]	221392	1			T1	1		T3	44		T4	11
valid_sources[0x41]	515341	1			T1	3		T5	94		T7	5
valid_sources[0x42]	212178	1			T1	8		T4	1		T5	77
valid_sources[0x43]	221440	1			T1	6		T5	17		T7	2
valid_sources[0x44]	212703	1			T1	2		T5	26		T8	204
valid_sources[0x45]	210844	1			T1	7		T5	19		T7	2
valid_sources[0x46]	252090	1			T1	1		T3	24		T5	31
valid_sources[0x47]	228345	1			T1	4		T3	43		T5	22
valid_sources[0x48]	222655	1			T1	5		T5	115		T7	1
valid_sources[0x49]	224537	1			T1	2		T4	1		T5	44
valid_sources[0x4a]	232578	1			T1	2		T4	13		T5	113
valid_sources[0x4b]	206884	1			T1	2		T5	89		T8	256
valid_sources[0x4c]	215867	1			T1	1		T5	30		T7	1
valid_sources[0x4d]	234278	1			T1	2		T5	42		T7	2
valid_sources[0x4e]	295192	1			T1	1		T4	2		T5	66
valid_sources[0x4f]	220196	1			T3	38		T5	68		T7	4
valid_sources[0x50]	231354	1			T1	1		T5	31		T7	3
valid_sources[0x51]	214283	1			T1	3		T4	20		T5	48
valid_sources[0x52]	238365	1			T1	3		T5	39		T7	9
valid_sources[0x53]	233791	1			T1	1		T3	80		T4	2
valid_sources[0x54]	296490	1			T1	3		T3	22		T4	6
valid_sources[0x55]	224877	1			T1	2		T5	89		T7	2
valid_sources[0x56]	255381	1			T1	3		T2	1		T4	23
valid_sources[0x57]	205273	1			T1	3		T5	104		T7	4
valid_sources[0x58]	224287	1			T5	39		T7	4		T8	215
valid_sources[0x59]	216846	1			T1	2		T4	8		T5	38
valid_sources[0x5a]	228142	1			T1	2		T3	43		T4	6
valid_sources[0x5b]	228797	1			T1	2		T5	141		T7	86
valid_sources[0x5c]	260128	1			T1	1		T2	1		T4	8
valid_sources[0x5d]	214766	1			T1	4		T5	93		T7	5
valid_sources[0x5e]	230646	1			T1	1		T5	122		T7	4
valid_sources[0x5f]	228381	1			T1	1		T4	4		T5	51
valid_sources[0x60]	228024	1			T1	6		T5	86		T7	1
valid_sources[0x61]	221992	1			T1	1		T2	1		T5	74
valid_sources[0x62]	218007	1			T1	1		T5	40		T7	6
valid_sources[0x63]	235881	1			T1	3		T4	23		T5	38
valid_sources[0x64]	546640	1			T1	1		T2	1		T3	6
valid_sources[0x65]	219702	1			T1	1		T3	59		T5	98
valid_sources[0x66]	237057	1			T1	2		T4	3		T5	82
valid_sources[0x67]	253328	1			T1	2		T5	55		T7	5
valid_sources[0x68]	228756	1			T1	3		T4	11		T5	63
valid_sources[0x69]	220304	1			T1	3		T4	24		T5	30
valid_sources[0x6a]	216909	1			T1	4		T4	3		T5	43
valid_sources[0x6b]	214910	1			T1	2		T5	35		T7	1
valid_sources[0x6c]	230868	1			T1	2		T5	42		T7	3
valid_sources[0x6d]	222132	1			T1	4		T3	35		T5	84
valid_sources[0x6e]	217238	1			T1	1		T5	100		T7	2
valid_sources[0x6f]	220806	1			T1	1		T5	47		T7	3
valid_sources[0x70]	251914	1			T3	8		T4	9		T5	123
valid_sources[0x71]	217712	1			T1	4		T3	7		T5	27
valid_sources[0x72]	242070	1			T1	2		T4	35		T5	88
valid_sources[0x73]	230143	1			T5	80		T7	1		T8	255
valid_sources[0x74]	227984	1			T1	5		T3	9		T5	51
valid_sources[0x75]	231721	1			T1	6		T5	20		T7	3
valid_sources[0x76]	314145	1			T1	4		T5	51		T7	2
valid_sources[0x77]	232874	1			T1	2		T4	4		T5	32
valid_sources[0x78]	221028	1			T5	98		T7	200		T8	216
valid_sources[0x79]	217499	1			T1	3		T4	9		T5	14
valid_sources[0x7a]	225048	1			T1	3		T5	35		T7	5
valid_sources[0x7b]	212889	1			T1	1		T4	8		T5	48
valid_sources[0x7c]	222358	1			T1	1		T5	62		T7	1
valid_sources[0x7d]	250060	1			T1	1		T3	40		T5	63
valid_sources[0x7e]	232644	1			T1	2		T4	23		T5	90
valid_sources[0x7f]	246596	1			T1	3		T5	53		T7	5
valid_sources[0x80]	213874	1			T1	1		T2	1		T5	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10963878

1

T1

82

T2

9

T3

227

values[0x0]

all_enables

biggest_size

262409

1

T1

59

T2

1

T3

176

values[0x1]

all_enables

biggest_size

185936

1

T1

36

T3

131

T4

13