Unified Coverage Report :: Group :: i2c_env_pkg::i2c_acq_fifo_cg

Group : i2c_env_pkg::i2c_acq_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.acq_fifo_cg	95.83	1	100	1	64	64

---

Group Instance : i2c_env_pkg.acq_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.acq_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	13	1	12	92.31

Variables for Group Instance i2c_env_pkg.acq_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_abyte	5	0	5	100.00	100	1	1	0
cp_action	4	0	4	100.00	100	1	1	0
cp_request_type	2	0	2	100.00	100	1	1	0
cp_target_read_ack_nack	0	0	0				1	0

Crosses for Group Instance i2c_env_pkg.acq_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_abyte_X_cp_action	13	1	12	92.31	100	1	1	0

Summary for Variable cp_abyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_abyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	987	1			T1	3		T3	2		T4	1
high	57214	1			T1	27		T3	119		T4	90
med	104884	1			T1	47		T3	116		T4	176
sml	101767	1			T1	52		T3	162		T4	238
all_zero	1244	1			T3	3		T4	1		T19	1

---

Summary for Variable cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
rstart	42107	1			T1	22		T3	57		T4	50
start	12800	1			T1	5		T3	40		T4	4
stop	12802	1			T1	12		T3	40		T4	4
none	198387	1			T1	90		T3	265		T4	448

---

Summary for Variable cp_request_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_request_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

write

5567

1

T1

3

T3

16

T4

4

read

7233

1

T1

2

T3

24

T5

3

---

Summary for Variable cp_target_read_ack_nack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	0	0	0

User Defined Bins for cp_target_read_ack_nack

Excluded/Illegal bins

NAME	COUNT	STATUS
read_req_nack_before_rstart	0	Excluded
read_req_ack_before_stop	0	Excluded
read_req_nack_before_stop	0	Excluded
read_req_ack_before_rstart	0	Excluded

---

Summary for Cross cp_abyte_X_cp_action

Samples crossed: cp_abyte cp_action

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	1	12	92.31	1
Automatically Generated Cross Bins	10	1	9	90.00	1
User Defined Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for cp_abyte_X_cp_action

Uncovered bins

cp_abyte	cp_action	COUNT	AT LEAST	NUMBER	STATUS
[all_ones]	[stop]	0	1	1

Covered bins

cp_abyte	cp_action	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	rstart	182	1			T227	132		T228	11		T229	39
high	rstart	9645	1			T1	13		T3	27		T19	181
high	stop	2592	1			T1	6		T3	7		T4	1
med	rstart	16908	1			T1	5		T5	55		T66	20
med	stop	5099	1			T1	2		T3	15		T4	2
sml	rstart	15096	1			T1	4		T3	30		T4	50
sml	stop	5011	1			T1	4		T3	17		T4	1
all_zero	rstart	276	1			T230	104		T231	15		T232	28
all_zero	stop	100	1			T3	1		T88	1		T73	1

User Defined Cross Bins for cp_abyte_X_cp_action

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
write_address_byte	12800	1			T1	5		T3	40		T4	4
read_address_byte	12800	1			T1	5		T3	40		T4	4
data_byte	198387	1			T1	90		T3	265		T4	448