Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	96.08	100.00	84.31			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.70	100.00	84.28			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
96.08	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T35,T72
1	1	Covered	T1,T3,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T77,T78,T37
1	1	Covered	T1,T3,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T131,T37,T84

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T131,T37,T84
1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T131,T37,T84
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T3,T5
1	0	-	Covered	T1,T3,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	5192	5192	0	0
MinimalSramFifoDepth_A	5192	5192	0	0
NoErr_A	1817802280	1817136464	0	0
NoSramReadWhenEmpty_A	1817802280	1432920671	0	0
NoSramWriteWhenFull_A	1817802280	30416050	0	0
OupBufWreadyAfterSramRead_A	1817802280	717580	0	0
SramRvalidAfterRead_A	1817802280	717580	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5192	5192	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5192	5192	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1817802280	1817136464	0	0
T1	239052	238792	0	0
T2	4752	4360	0	0
T3	561444	561052	0	0
T4	1262408	1262008	0	0
T5	479448	479060	0	0
T6	7612	7212	0	0
T7	1162604	1162400	0	0
T8	1543012	1542700	0	0
T9	79704	79416	0	0
T10	78348	76008	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1817802280	1432920671	0	0
T1	239052	204228	0	0
T2	4752	4360	0	0
T3	561444	462839	0	0
T4	1262408	950987	0	0
T5	479448	454834	0	0
T6	7612	7212	0	0
T7	1162604	889880	0	0
T8	1543012	1179573	0	0
T9	79704	60860	0	0
T10	78348	75476	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1817802280	30416050	0	0
T7	290651	548	0	0
T8	0	488	0	0
T9	39852	4139	0	0
T10	39174	0	0	0
T15	229412	11	0	0
T16	0	22	0	0
T19	806988	38059	0	0
T20	94914	0	0	0
T35	0	2388	0	0
T37	0	292037	0	0
T38	0	27333	0	0
T39	28567	0	0	0
T47	159916	12924	0	0
T53	27566	0	0	0
T62	22274	20	0	0
T64	0	749	0	0
T66	237442	0	0	0
T67	2340	0	0	0
T72	0	3475	0	0
T80	0	203320	0	0
T85	0	14144	0	0
T100	0	781	0	0
T130	258010	0	0	0
T132	0	2793	0	0
T133	0	21	0	0
T134	0	5388	0	0
T135	0	19137	0	0
T136	0	34880	0	0
T137	157808	0	0	0
T138	132610	0	0	0
T139	178403	0	0	0
T140	234207	0	0	0
T141	154326	0	0	0
T142	150377	0	0	0
T143	997696	0	0	0
T144	76377	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1817802280	717580	0	0
T1	119526	106	0	0
T2	2376	0	0	0
T3	280722	296	0	0
T4	631204	504	0	0
T5	239724	0	0	0
T6	3806	0	0	0
T7	1162604	1375	0	0
T8	1543012	1750	0	0
T9	79704	88	0	0
T10	78348	2	0	0
T11	0	55	0	0
T19	806988	717	0	0
T20	94914	28	0	0
T28	0	308	0	0
T29	0	303	0	0
T30	0	345	0	0
T35	0	3290	0	0
T39	0	67	0	0
T40	0	26	0	0
T47	0	6001	0	0
T53	27566	0	0	0
T62	22274	0	0	0
T64	0	2375	0	0
T65	0	112	0	0
T66	237442	383	0	0
T67	2340	0	0	0
T85	0	73	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1817802280	717580	0	0
T1	119526	106	0	0
T2	2376	0	0	0
T3	280722	296	0	0
T4	631204	504	0	0
T5	239724	0	0	0
T6	3806	0	0	0
T7	1162604	1375	0	0
T8	1543012	1750	0	0
T9	79704	88	0	0
T10	78348	2	0	0
T11	0	55	0	0
T19	806988	717	0	0
T20	94914	28	0	0
T28	0	308	0	0
T29	0	303	0	0
T30	0	345	0	0
T35	0	3290	0	0
T39	0	67	0	0
T40	0	26	0	0
T47	0	6001	0	0
T53	27566	0	0	0
T62	22274	0	0	0
T64	0	2375	0	0
T65	0	112	0	0
T66	237442	383	0	0
T67	2340	0	0	0
T85	0	73	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T77,T78,T79
1	1	Covered	T1,T3,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T11,T73
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T11,T73

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T19,T11,T73

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T3,T5
1	0	-	Covered	T1,T3,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1298	1298	0	0
MinimalSramFifoDepth_A	1298	1298	0	0
NoErr_A	454450570	454284116	0	0
NoSramReadWhenEmpty_A	454450570	381154223	0	0
NoSramWriteWhenFull_A	454450570	6562191	0	0
OupBufWreadyAfterSramRead_A	454450570	195071	0	0
SramRvalidAfterRead_A	454450570	195071	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	454284116	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	381154223	0	0
T1	59763	50997	0	0
T2	1188	1090	0	0
T3	140361	95190	0	0
T4	315602	315502	0	0
T5	119862	95539	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	6562191	0	0
T11	0	200	0	0
T19	403494	38059	0	0
T20	47457	0	0	0
T28	231015	0	0	0
T39	28567	0	0	0
T47	159916	0	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T64	491992	0	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T73	0	3051	0	0
T77	0	38075	0	0
T131	0	17564	0	0
T145	0	91054	0	0
T146	0	7430	0	0
T147	0	57481	0	0
T148	0	24143	0	0
T149	0	79409	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	195071	0	0
T1	59763	60	0	0
T2	1188	0	0	0
T3	140361	229	0	0
T4	315602	0	0	0
T5	119862	145	0	0
T6	1903	0	0	0
T7	290651	0	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T11	0	250	0	0
T19	0	1004	0	0
T20	0	59	0	0
T28	0	111	0	0
T29	0	66	0	0
T30	0	203	0	0
T31	0	136	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	195071	0	0
T1	59763	60	0	0
T2	1188	0	0	0
T3	140361	229	0	0
T4	315602	0	0	0
T5	119862	145	0	0
T6	1903	0	0	0
T7	290651	0	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T11	0	250	0	0
T19	0	1004	0	0
T20	0	59	0	0
T28	0	111	0	0
T29	0	66	0	0
T30	0	203	0	0
T31	0	136	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T37,T74,T75
1	1	Covered	T7,T8,T9

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T7,T8,T9
1	0	Covered	T37,T74,T75

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T37,T74,T75
1	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T37,T74,T75
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T35,T85
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T35,T85

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T9,T35,T85

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T8,T9
1	0	-	Covered	T7,T8,T9
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1298	1298	0	0
MinimalSramFifoDepth_A	1298	1298	0	0
NoErr_A	454450570	454284116	0	0
NoSramReadWhenEmpty_A	454450570	382053129	0	0
NoSramWriteWhenFull_A	454450570	23101599	0	0
OupBufWreadyAfterSramRead_A	454450570	164676	0	0
SramRvalidAfterRead_A	454450570	164676	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	454284116	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	382053129	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	154675	0	0
T8	385753	202564	0	0
T9	19926	1298	0	0
T10	19587	18470	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	23101599	0	0
T9	19926	4139	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	5	0	0
T37	0	292037	0	0
T38	0	27333	0	0
T39	28567	0	0	0
T47	159916	0	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T80	0	203320	0	0
T85	0	14116	0	0
T133	0	21	0	0
T134	0	5388	0	0
T135	0	19137	0	0
T136	0	34880	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	164676	0	0
T7	290651	693	0	0
T8	385753	882	0	0
T9	19926	88	0	0
T10	19587	2	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	1430	0	0
T39	0	67	0	0
T40	0	26	0	0
T47	0	1475	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T64	0	1197	0	0
T65	0	112	0	0
T66	118721	0	0	0
T67	1170	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	164676	0	0
T7	290651	693	0	0
T8	385753	882	0	0
T9	19926	88	0	0
T10	19587	2	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	1430	0	0
T39	0	67	0	0
T40	0	26	0	0
T47	0	1475	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T64	0	1197	0	0
T65	0	112	0	0
T66	118721	0	0	0
T67	1170	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16
1	1	Covered	T1,T3,T4

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T131,T84,T79

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T131,T84,T79
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T131,T84,T79
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T16
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T15,T16

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T3,T4
1	0	-	Covered	T1,T3,T4
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1298	1298	0	0
MinimalSramFifoDepth_A	1298	1298	0	0
NoErr_A	454450570	454284116	0	0
NoSramReadWhenEmpty_A	454450570	251982089	0	0
NoSramWriteWhenFull_A	454450570	33	0	0
OupBufWreadyAfterSramRead_A	454450570	179755	0	0
SramRvalidAfterRead_A	454450570	179755	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	454284116	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	251982089	0	0
T1	59763	33835	0	0
T2	1188	1090	0	0
T3	140361	87123	0	0
T4	315602	4481	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	33	0	0
T15	229412	11	0	0
T16	0	22	0	0
T130	258010	0	0	0
T137	157808	0	0	0
T138	132610	0	0	0
T139	178403	0	0	0
T140	234207	0	0	0
T141	154326	0	0	0
T142	150377	0	0	0
T143	997696	0	0	0
T144	76377	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	179755	0	0
T1	59763	106	0	0
T2	1188	0	0	0
T3	140361	296	0	0
T4	315602	504	0	0
T5	119862	0	0	0
T6	1903	0	0	0
T7	290651	0	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T11	0	55	0	0
T19	0	717	0	0
T20	0	28	0	0
T28	0	308	0	0
T29	0	303	0	0
T30	0	345	0	0
T66	0	383	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	179755	0	0
T1	59763	106	0	0
T2	1188	0	0	0
T3	140361	296	0	0
T4	315602	504	0	0
T5	119862	0	0	0
T6	1903	0	0	0
T7	290651	0	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T11	0	55	0	0
T19	0	717	0	0
T20	0	28	0	0
T28	0	308	0	0
T29	0	303	0	0
T30	0	345	0	0
T66	0	383	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T35,T72
1	1	Covered	T7,T8,T10

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T76
1	1	Covered	T7,T8,T62

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T47
1	1	Covered	T7,T8,T62

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T62
1	1	Covered	T7,T8,T47

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T62
0	1	Covered	T7,T8,T47
1	0	Covered	T150,T76

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T150,T76
1	Covered	T7,T8,T62

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T150,T76
0	1	Covered	T7,T8,T62
1	0	Covered	T7,T8,T47

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T62
1	1	Covered	T7,T8,T47

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T62
1	1	Covered	T7,T8,T47

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T62
1	1	Covered	T7,T8,T62

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T62
1	1	Covered	T7,T8,T62

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T47
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T62

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T62

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T62
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T62

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T62
1	0	Not Covered
1	1	Covered	T7,T8,T62

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T47
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T8,T47
1	0	-	Covered	T7,T8,T62
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1298	1298	0	0
MinimalSramFifoDepth_A	1298	1298	0	0
NoErr_A	454450570	454284116	0	0
NoSramReadWhenEmpty_A	454450570	417731230	0	0
NoSramWriteWhenFull_A	454450570	752227	0	0
OupBufWreadyAfterSramRead_A	454450570	178078	0	0
SramRvalidAfterRead_A	454450570	178078	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1298	1298	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	454284116	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	290600	0	0
T8	385753	385675	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	417731230	0	0
T1	59763	59698	0	0
T2	1188	1090	0	0
T3	140361	140263	0	0
T4	315602	315502	0	0
T5	119862	119765	0	0
T6	1903	1803	0	0
T7	290651	154005	0	0
T8	385753	205659	0	0
T9	19926	19854	0	0
T10	19587	19002	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	752227	0	0
T7	290651	548	0	0
T8	385753	488	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	2383	0	0
T47	0	12924	0	0
T53	13783	0	0	0
T62	11137	20	0	0
T64	0	749	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T72	0	3475	0	0
T85	0	28	0	0
T100	0	781	0	0
T132	0	2793	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	178078	0	0
T7	290651	682	0	0
T8	385753	868	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	1860	0	0
T38	0	1302	0	0
T47	0	4526	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T64	0	1178	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T72	0	992	0	0
T85	0	73	0	0
T100	0	992	0	0
T132	0	868	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454450570	178078	0	0
T7	290651	682	0	0
T8	385753	868	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T35	0	1860	0	0
T38	0	1302	0	0
T47	0	4526	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T64	0	1178	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T72	0	992	0	0
T85	0	73	0	0
T100	0	992	0	0
T132	0	868	0	0