Module Definition
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Module : prim_subreg
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.32 100.00 96.10 92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_fmt_threshold 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_rx_threshold 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_acq_threshold 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_controller_halt 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_tx_stretch 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_tx_threshold 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_intr_state_acq_stretch 65.24 85.71 50.00 60.00
tb.dut.u_reg.u_target_nack_count 80.95 100.00 57.14 85.71
tb.dut.u_reg.u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_fbyte 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_start 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_stop 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_readb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_rcont 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fdata_nakok 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sclval 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_thigh 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing0_tlow 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_r 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing1_t_f 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timing4_t_buf 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask0 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_address1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_id_mask1 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_txdata 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_controller_events_nack 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_controller_events_bus_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_controller_events_arbitration_lost 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_events_bus_timeout 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_target_events_arbitration_lost 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=13,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=9,SwAccess=0,RESVAL=0,Mubi=0 + DW=30,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_fmt_threshold

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_rx_threshold

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_acq_threshold

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_controller_halt

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_tx_stretch

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_tx_threshold

SCORELINE
65.24 85.71
tb.dut.u_reg.u_intr_state_acq_stretch

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_start

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_stop

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_readb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_rcont

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fdata_nakok

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORELINE
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval

SCORELINE
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_thigh

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing0_tlow

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_r

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing1_t_f

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode

SCORELINE
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask0

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_address1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_id_mask1

SCORELINE
100.00 100.00
tb.dut.u_reg.u_txdata

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val

SCORELINE
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en

SCORELINE
100.00 100.00
tb.dut.u_reg.u_controller_events_nack

SCORELINE
100.00 100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_controller_events_bus_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_controller_events_arbitration_lost

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_events_bus_timeout

SCORELINE
100.00 100.00
tb.dut.u_reg.u_target_events_arbitration_lost

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
72 1 1


Line Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
80.95 100.00
tb.dut.u_reg.u_target_nack_count

Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 1 1
57 1 1
58 1 1
59 1 1
MISSING_ELSE
64 1 1
65 1 1
70 1 1


Cond Coverage for Module : prim_subreg ( parameter DW=30,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=20,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte

SCORECOND
100.00 100.00
tb.dut.u_reg.u_txdata

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_fmt_threshold

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_rx_threshold

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_acq_threshold

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_controller_halt

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_tx_stretch

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_tx_threshold

SCORECOND
65.24 50.00
tb.dut.u_reg.u_intr_state_acq_stretch

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_controller_events_nack

SCORECOND
100.00 100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_controller_events_bus_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_controller_events_arbitration_lost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_events_bus_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_events_arbitration_lost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_start

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_stop

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_readb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_rcont

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fdata_nakok

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval

SCORECOND
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T41,T42

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
80.95 57.14
tb.dut.u_reg.u_target_nack_count

TotalCoveredPercent
Conditions7457.14
Logical7457.14
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT127,T90,T128

 LINE       70
 EXPRESSION ((de && we) ? d : q)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       70
 SUB-EXPRESSION (de && we)
                 -1    -2
-1--2-StatusTests
01CoveredT127,T90,T128
10Not Covered
11Not Covered

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_r

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask0

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_address1

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_id_mask1

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCORECOND
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCORECOND
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing1_t_f

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Cond Coverage for Module : prim_subreg ( parameter DW=13,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_thigh

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing0_tlow

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto

SCORECOND
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

Branch Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=8,SwAccess=2,RESVAL=0,Mubi=0 + DW=12,SwAccess=0,RESVAL=0,Mubi=0 + DW=13,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=9,SwAccess=0,RESVAL=0,Mubi=0 + DW=30,SwAccess=0,RESVAL=0,Mubi=0 + DW=7,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=31,SwAccess=0,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_fmt_threshold

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_rx_threshold

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_acq_threshold

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_controller_halt

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_tx_stretch

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_tx_threshold

SCOREBRANCH
65.24 60.00
tb.dut.u_reg.u_intr_state_acq_stretch

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_rx_overflow

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_scl_interference

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_interference

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_stretch_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_sda_unstable

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_cmd_complete

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_unexp_stop

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_state_host_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_controller_events_nack

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_controller_events_unhandled_nack_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_controller_events_bus_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_controller_events_arbitration_lost

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_events_tx_pending

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_events_bus_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_events_arbitration_lost

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_fmt_threshold

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_threshold

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_rx_overflow

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_controller_halt

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_scl_interference

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_interference

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_stretch_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_sda_unstable

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_cmd_complete

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_stretch

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_tx_threshold

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_acq_stretch

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_unexp_stop

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_intr_enable_host_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_enablehost

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_enabletarget

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_llpbk

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_nack_addr_after_timeout

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_ack_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_multi_controller_monitor_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ctrl_tx_stretch_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_start

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_stop

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_readb

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_rcont

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_nakok

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_rxrst

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_fmtrst

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_acqrst

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fifo_ctrl_txrst

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ovrd_txovrden

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ovrd_sclval

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_ovrd_sdaval

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_mode

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_en

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_fdata_fbyte

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_txdata

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_rx_thresh

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_host_fifo_config_fmt_thresh

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_tx_thresh

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_fifo_config_acq_thresh

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing0_thigh

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing0_tlow

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing2_tsu_sta

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing2_thd_sta

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing3_thd_dat

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing4_tsu_sto

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing4_t_buf

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing1_t_r

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing1_t_f

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timing3_tsu_dat

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_timeout_ctrl_val

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_id_address0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_id_mask0

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_id_address1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_id_mask1

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_host_timeout_ctrl

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_target_timeout_ctrl_val

SCOREBRANCH
100.00 100.00
tb.dut.u_reg.u_host_nack_handler_timeout_val

Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


Branch Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=6,RESVAL=0,Mubi=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
80.95 85.71
tb.dut.u_reg.u_target_nack_count

Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 64 2 2 100.00
TERNARY 70 2 1 50.00
IF 56 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (wr_en) ?

Branches:
-1-StatusTests
1 Covered T127,T90,T128
0 Covered T1,T2,T3


LineNo. Expression -1-: 70 ((de && we)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni)) -2-: 58 if (wr_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T127,T90,T128
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%