Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	455119528	0	0	0
ctrl_rd_A	455119528	1095	0	0
host_fifo_config_rd_A	455119528	5210	0	0
host_nack_handler_timeout_rd_A	455119528	815	0	0
host_timeout_ctrl_rd_A	455119528	733	0	0
intr_enable_rd_A	455119528	1882	0	0
ovrd_rd_A	455119528	1630	0	0
target_fifo_config_rd_A	455119528	877	0	0
target_id_rd_A	455119528	1065	0	0
target_timeout_ctrl_rd_A	455119528	810	0	0
timeout_ctrl_rd_A	455119528	903	0	0
timing0_rd_A	455119528	798	0	0
timing1_rd_A	455119528	884	0	0
timing2_rd_A	455119528	791	0	0
timing3_rd_A	455119528	929	0	0
timing4_rd_A	455119528	942	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	1095	0	0
T90	3790	8	0	0
T91	4971	16	0	0
T92	3581	2	0	0
T93	10234	7	0	0
T94	2118	25	0	0
T95	1806	20	0	0
T96	9001	13	0	0
T97	5193	19	0	0
T98	8452	204	0	0
T99	4071	75	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	5210	0	0
T7	290651	63	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T20	47457	0	0	0
T37	0	78	0	0
T46	0	252	0	0
T47	0	187	0	0
T50	0	221	0	0
T53	13783	0	0	0
T62	11137	0	0	0
T66	118721	0	0	0
T67	1170	0	0	0
T100	0	185	0	0
T101	0	103	0	0
T102	0	49	0	0
T103	0	212	0	0
T104	0	132	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	815	0	0
T90	3790	3	0	0
T91	4971	9	0	0
T92	3581	24	0	0
T93	10234	15	0	0
T94	2118	13	0	0
T95	1806	15	0	0
T96	9001	20	0	0
T97	5193	5	0	0
T98	8452	59	0	0
T99	4071	16	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	733	0	0
T90	3790	20	0	0
T91	4971	4	0	0
T92	3581	28	0	0
T93	10234	3	0	0
T94	2118	5	0	0
T95	1806	8	0	0
T96	9001	29	0	0
T97	5193	10	0	0
T98	8452	50	0	0
T99	4071	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	1882	0	0
T18	289895	0	0	0
T26	433029	0	0	0
T27	131943	0	0	0
T37	428553	28	0	0
T46	0	14	0	0
T90	0	6	0	0
T104	0	28	0	0
T105	0	10	0	0
T106	0	37	0	0
T107	0	10	0	0
T108	0	32	0	0
T109	0	14	0	0
T110	0	6	0	0
T111	97015	0	0	0
T112	109745	0	0	0
T113	12425	0	0	0
T114	204724	0	0	0
T115	835797	0	0	0
T116	28561	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	1630	0	0
T2	1188	19	0	0
T3	140361	0	0	0
T4	315602	0	0	0
T5	119862	0	0	0
T6	1903	0	0	0
T7	290651	0	0	0
T8	385753	0	0	0
T9	19926	0	0	0
T10	19587	0	0	0
T19	403494	0	0	0
T117	0	56	0	0
T118	0	14	0	0
T119	0	33	0	0
T120	0	36	0	0
T121	0	21	0	0
T122	0	50	0	0
T123	0	62	0	0
T124	0	49	0	0
T125	0	30	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	877	0	0
T90	3790	20	0	0
T91	4971	6	0	0
T92	3581	21	0	0
T93	10234	18	0	0
T94	2118	11	0	0
T95	1806	17	0	0
T96	9001	36	0	0
T97	5193	6	0	0
T98	8452	63	0	0
T99	4071	27	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	1065	0	0
T90	3790	13	0	0
T91	4971	32	0	0
T92	3581	11	0	0
T93	10234	4	0	0
T94	2118	11	0	0
T95	1806	29	0	0
T96	9001	14	0	0
T97	5193	26	0	0
T98	8452	91	0	0
T99	4071	36	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	810	0	0
T90	3790	30	0	0
T91	4971	6	0	0
T92	3581	19	0	0
T93	10234	1	0	0
T94	2118	10	0	0
T95	1806	13	0	0
T96	9001	13	0	0
T97	5193	11	0	0
T98	8452	38	0	0
T99	4071	21	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	903	0	0
T90	3790	30	0	0
T91	4971	17	0	0
T92	3581	10	0	0
T93	10234	25	0	0
T94	2118	8	0	0
T95	1806	10	0	0
T96	9001	19	0	0
T97	5193	4	0	0
T98	8452	99	0	0
T99	4071	19	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	798	0	0
T90	3790	16	0	0
T91	4971	45	0	0
T92	3581	36	0	0
T93	10234	2	0	0
T94	2118	8	0	0
T95	1806	13	0	0
T96	9001	21	0	0
T97	5193	6	0	0
T98	8452	55	0	0
T99	4071	17	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	884	0	0
T90	3790	12	0	0
T91	4971	31	0	0
T92	3581	20	0	0
T93	10234	18	0	0
T94	2118	5	0	0
T95	1806	7	0	0
T96	9001	42	0	0
T97	5193	15	0	0
T98	8452	76	0	0
T99	4071	29	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	791	0	0
T90	3790	11	0	0
T91	4971	23	0	0
T92	3581	27	0	0
T93	10234	16	0	0
T94	2118	16	0	0
T95	1806	13	0	0
T96	9001	9	0	0
T98	8452	56	0	0
T99	4071	15	0	0
T126	6563	31	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	929	0	0
T90	3790	20	0	0
T91	4971	5	0	0
T92	3581	4	0	0
T93	10234	9	0	0
T95	1806	3	0	0
T96	9001	19	0	0
T97	5193	10	0	0
T98	8452	86	0	0
T99	4071	37	0	0
T126	6563	71	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455119528	942	0	0
T90	3790	26	0	0
T91	4971	15	0	0
T92	3581	23	0	0
T93	10234	16	0	0
T94	2118	3	0	0
T95	1806	12	0	0
T96	9001	17	0	0
T97	5193	10	0	0
T98	8452	44	0	0
T99	4071	36	0	0