Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

159903

1

T5

90

T7

2374

T9

902

ack

14499

1

T3

52

T5

5

T7

151

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	632	1			T7	4		T9	2		T55	2
high	35783	1			T3	8		T5	22		T7	492
med	64752	1			T3	5		T5	35		T7	989
sml	72556	1			T3	39		T5	38		T7	1032
all_zero	679	1			T7	8		T9	7		T55	2

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86880

1

T3

24

T5

41

T7

1292

auto[1]

87522

1

T3

28

T5

54

T7

1233

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119939

1

T3

33

T5

72

T7

1731

auto[1]

54463

1

T3

19

T5

23

T7

794

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166690

1

T3

17

T5

89

T7

2450

auto[1]

7712

1

T3

35

T5

6

T7

75

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164468

1

T3

35

T5

84

T7

2424

auto[1]

9934

1

T3

17

T5

11

T7

101

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165424

1

T3

36

T5

88

T7

2437

auto[1]

8978

1

T3

16

T5

7

T7

88

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86880

1

T3

24

T5

41

T7

1292

auto[1]

87522

1

T3

28

T5

54

T7

1233

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119939

1

T3

33

T5

72

T7

1731

auto[1]

54463

1

T3

19

T5

23

T7

794

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

166690

1

T3

17

T5

89

T7

2450

auto[1]

7712

1

T3

35

T5

6

T7

75

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164468

1

T3

35

T5

84

T7

2424

auto[1]

9934

1

T3

17

T5

11

T7

101

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165424

1

T3

36

T5

88

T7

2437

auto[1]

8978

1

T3

16

T5

7

T7

88

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T243

1

T244

1

T245

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

3

1

T48

1

T94

1

T246

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

3

1

T148

1

T247

1

T248

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

280

1

T7

3

T41

1

T67

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

146

1

T7

3

T9

2

T249

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

151

1

T148

1

T249

1

T155

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

538

1

T5

1

T7

7

T9

6

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

257

1

T7

3

T9

2

T67

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

269

1

T5

1

T7

2

T67

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

539

1

T5

1

T7

6

T9

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

283

1

T7

4

T148

2

T250

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

254

1

T7

3

T9

2

T67

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

10

1

T116

1

T251

1

T252

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T142

1

T139

1

T253

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

8

1

T254

1

T95

1

T255

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	50765	1			T5	22		T7	799		T9	310
write_address_byte	9934	1			T3	17		T5	11		T7	101
read_with_ack	2261	1			T3	19		T5	2		T7	17
read_with_nack	5451	1			T3	16		T5	4		T7	58
stop_byte	8978	1			T3	16		T5	7		T7	88
write_address_byte_nak	4935	1			T5	9		T7	51		T9	28
data_byte_nack	159903	1			T5	90		T7	2374		T9	902
stop_byte_nack	5378	1			T5	7		T7	51		T9	25
nakok_byte_nack	80209	1			T5	49		T7	1163		T9	447
nakok_addr_byte_nack	2483	1			T5	3		T7	32		T9	18