Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41851614	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10460243

1

T1

68

T2

15

T3

7559

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51397843	1			T1	168		T2	18		T3	26256
values[0x0]	455813	1			T1	79		T2	8		T3	507
values[0x1]	458201	1			T1	81		T2	13		T3	566

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29836105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22475752

1

T1

137

T2

19

T3

13195

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	210184	1			T3	149		T5	1		T7	786
valid_sources[0x01]	192905	1			T3	12		T7	753		T9	4433
valid_sources[0x02]	195855	1			T1	1		T3	20		T5	1
valid_sources[0x03]	189851	1			T3	6		T5	8		T7	793
valid_sources[0x04]	196424	1			T1	3		T3	4		T5	2
valid_sources[0x05]	217056	1			T1	2		T3	3		T5	1
valid_sources[0x06]	176234	1			T3	10		T5	6		T7	775
valid_sources[0x07]	204620	1			T1	2		T3	17		T7	780
valid_sources[0x08]	197876	1			T1	1		T3	26		T7	819
valid_sources[0x09]	212182	1			T1	1		T3	19		T5	507
valid_sources[0x0a]	197023	1			T1	1		T3	17		T7	742
valid_sources[0x0b]	180189	1			T1	1		T3	14		T7	770
valid_sources[0x0c]	189176	1			T3	6		T5	484		T7	783
valid_sources[0x0d]	196168	1			T1	1		T3	10		T5	2
valid_sources[0x0e]	253263	1			T1	1		T3	3		T5	4
valid_sources[0x0f]	198694	1			T3	11		T5	505		T7	848
valid_sources[0x10]	185841	1			T1	1		T3	20		T5	1
valid_sources[0x11]	309112	1			T3	11		T7	725		T9	4006
valid_sources[0x12]	188208	1			T3	6		T5	2		T7	819
valid_sources[0x13]	184137	1			T1	2		T3	5		T7	771
valid_sources[0x14]	244964	1			T1	1		T3	11		T5	3
valid_sources[0x15]	198479	1			T1	2		T3	10		T5	3
valid_sources[0x16]	843986	1			T3	150		T5	1		T7	755
valid_sources[0x17]	194782	1			T3	15		T5	1		T7	804
valid_sources[0x18]	193832	1			T1	3		T3	5		T7	783
valid_sources[0x19]	194358	1			T2	2		T3	4		T5	3
valid_sources[0x1a]	213404	1			T1	2		T3	3		T7	817
valid_sources[0x1b]	196936	1			T3	6		T5	6		T7	762
valid_sources[0x1c]	199744	1			T1	2		T3	7		T5	508
valid_sources[0x1d]	179387	1			T1	1		T3	5		T5	2
valid_sources[0x1e]	264294	1			T1	1		T2	6		T3	7
valid_sources[0x1f]	243904	1			T1	1		T2	2		T3	209
valid_sources[0x20]	203078	1			T1	1		T3	465		T7	818
valid_sources[0x21]	188617	1			T1	1		T3	301		T7	759
valid_sources[0x22]	183517	1			T1	1		T3	6		T5	1
valid_sources[0x23]	240248	1			T1	1		T3	9		T5	1
valid_sources[0x24]	198762	1			T1	1		T3	1		T5	2
valid_sources[0x25]	202593	1			T3	5		T7	799		T8	5
valid_sources[0x26]	190363	1			T1	2		T3	4		T5	1
valid_sources[0x27]	194409	1			T1	3		T3	9		T7	730
valid_sources[0x28]	182386	1			T1	3		T3	27		T5	6
valid_sources[0x29]	182919	1			T1	1		T3	4		T5	1
valid_sources[0x2a]	190670	1			T1	1		T3	846		T5	2
valid_sources[0x2b]	176774	1			T1	1		T3	18		T7	797
valid_sources[0x2c]	176489	1			T1	2		T3	135		T5	3
valid_sources[0x2d]	200995	1			T1	2		T3	160		T5	1
valid_sources[0x2e]	193524	1			T1	2		T3	8		T7	800
valid_sources[0x2f]	190013	1			T3	7		T7	824		T8	1
valid_sources[0x30]	186099	1			T3	159		T5	3		T7	755
valid_sources[0x31]	207853	1			T1	1		T3	3		T7	791
valid_sources[0x32]	188307	1			T3	1126		T5	1		T7	771
valid_sources[0x33]	272900	1			T1	2		T3	2		T5	2
valid_sources[0x34]	186224	1			T1	1		T3	4		T5	8
valid_sources[0x35]	202151	1			T3	3		T5	500		T7	796
valid_sources[0x36]	188852	1			T3	156		T5	513		T7	764
valid_sources[0x37]	188619	1			T1	1		T3	4		T5	3
valid_sources[0x38]	187029	1			T1	1		T3	17		T5	11
valid_sources[0x39]	194409	1			T1	2		T3	7		T5	514
valid_sources[0x3a]	190611	1			T2	5		T3	2		T5	503
valid_sources[0x3b]	189784	1			T1	2		T3	6		T5	2
valid_sources[0x3c]	199807	1			T1	2		T3	589		T5	496
valid_sources[0x3d]	204189	1			T1	2		T3	155		T5	1
valid_sources[0x3e]	206561	1			T1	1		T3	14		T7	746
valid_sources[0x3f]	184129	1			T1	1		T2	1		T3	12
valid_sources[0x40]	192474	1			T1	2		T3	4		T7	756
valid_sources[0x41]	188748	1			T1	3		T3	292		T5	2
valid_sources[0x42]	185411	1			T1	3		T3	13		T7	790
valid_sources[0x43]	194326	1			T1	2		T3	12		T7	767
valid_sources[0x44]	191546	1			T1	2		T3	167		T5	2
valid_sources[0x45]	198610	1			T3	6		T5	3		T7	710
valid_sources[0x46]	204678	1			T3	299		T7	763		T8	20
valid_sources[0x47]	184195	1			T1	1		T3	8		T5	514
valid_sources[0x48]	206288	1			T1	1		T3	15		T5	510
valid_sources[0x49]	196938	1			T1	5		T3	145		T5	1
valid_sources[0x4a]	196511	1			T3	11		T5	499		T7	805
valid_sources[0x4b]	195566	1			T1	1		T2	3		T3	8
valid_sources[0x4c]	185632	1			T1	1		T3	158		T6	59
valid_sources[0x4d]	197907	1			T1	1		T3	5		T7	817
valid_sources[0x4e]	192352	1			T3	5		T5	1		T7	746
valid_sources[0x4f]	199415	1			T1	1		T3	1		T7	747
valid_sources[0x50]	194651	1			T3	2		T5	1		T7	830
valid_sources[0x51]	198115	1			T1	1		T3	2		T5	1
valid_sources[0x52]	196252	1			T1	1		T3	16		T7	832
valid_sources[0x53]	205602	1			T1	1		T3	12		T5	5
valid_sources[0x54]	266261	1			T3	4		T7	739		T9	3981
valid_sources[0x55]	191327	1			T1	1		T3	5		T7	773
valid_sources[0x56]	182372	1			T3	4		T5	3		T7	733
valid_sources[0x57]	177684	1			T1	1		T3	17		T5	1
valid_sources[0x58]	311252	1			T1	3		T3	829		T5	1
valid_sources[0x59]	200221	1			T1	1		T2	1		T3	5
valid_sources[0x5a]	192346	1			T1	1		T3	7		T5	6
valid_sources[0x5b]	197689	1			T1	1		T3	3		T5	1
valid_sources[0x5c]	194599	1			T1	3		T3	2		T5	2
valid_sources[0x5d]	185760	1			T1	1		T2	1		T3	6
valid_sources[0x5e]	317239	1			T1	1		T3	6		T5	1
valid_sources[0x5f]	185791	1			T1	1		T2	1		T3	140
valid_sources[0x60]	203560	1			T1	1		T3	1007		T5	2
valid_sources[0x61]	185622	1			T1	2		T3	4		T5	2
valid_sources[0x62]	201927	1			T3	14		T7	745		T8	4
valid_sources[0x63]	199361	1			T3	9		T7	820		T9	4266
valid_sources[0x64]	186033	1			T3	10		T5	4		T7	746
valid_sources[0x65]	238098	1			T1	2		T3	6		T7	708
valid_sources[0x66]	193677	1			T1	4		T3	446		T7	768
valid_sources[0x67]	185351	1			T1	6		T3	13		T5	3
valid_sources[0x68]	193297	1			T3	3		T5	487		T7	787
valid_sources[0x69]	191498	1			T1	1		T3	17		T5	1
valid_sources[0x6a]	197946	1			T3	6		T5	1		T7	855
valid_sources[0x6b]	224825	1			T1	4		T3	717		T5	8
valid_sources[0x6c]	185465	1			T1	1		T3	10		T5	497
valid_sources[0x6d]	191014	1			T1	1		T3	561		T5	9
valid_sources[0x6e]	186872	1			T1	2		T3	8		T5	1
valid_sources[0x6f]	201353	1			T1	2		T3	5		T5	505
valid_sources[0x70]	199039	1			T1	2		T3	2		T5	1
valid_sources[0x71]	193105	1			T1	4		T3	2		T5	5
valid_sources[0x72]	192218	1			T1	2		T3	150		T7	804
valid_sources[0x73]	187289	1			T3	11		T7	724		T8	1
valid_sources[0x74]	202694	1			T1	1		T3	13		T5	498
valid_sources[0x75]	198936	1			T1	1		T3	10		T5	6
valid_sources[0x76]	183876	1			T1	1		T3	11		T5	501
valid_sources[0x77]	183723	1			T3	418		T5	5		T7	762
valid_sources[0x78]	180777	1			T1	2		T3	7		T7	776
valid_sources[0x79]	195634	1			T1	1		T3	5		T7	810
valid_sources[0x7a]	202840	1			T1	4		T3	171		T7	780
valid_sources[0x7b]	195637	1			T1	1		T3	7		T5	1
valid_sources[0x7c]	192077	1			T1	3		T3	280		T5	999
valid_sources[0x7d]	182694	1			T1	1		T3	2		T5	2
valid_sources[0x7e]	198942	1			T1	1		T3	156		T5	3
valid_sources[0x7f]	175365	1			T3	4		T7	784		T8	2
valid_sources[0x80]	189244	1			T1	1		T3	149		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10043202

1

T1

1

T2

10

T3

6917

values[0x0]

all_enables

biggest_size

242239

1

T1

41

T2

3

T3

318

values[0x1]

all_enables

biggest_size

174802

1

T1

26

T2

2

T3

324