Unified Coverage Report :: Module :: i2c_fifo_sync_sram_adapter

Module : i2c_fifo_sync_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter	94.12	100.00	76.47			100.00	100.00
tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter	95.59	100.00	82.35			100.00	100.00
tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter	96.08	100.00	84.31			100.00	100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12	100.00	76.47			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.70	100.00	84.28			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	100.00	82.35			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.73	100.00	90.91			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.08	100.00	84.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	86.79			98.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	100.00				100.00	40.00	u_fifos

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_inp_buf	94.32	100.00	81.82			95.45	100.00
u_oup_buf	97.16	100.00	88.64			100.00	100.00
u_sram_ptrs	100.00	100.00	100.00			100.00

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=64,SramAw=9,SramBaseAddr,DepthW=7,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=6,SramDepthW=6,SramAddrLeadingZeros=3 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

SCORE	LINE
96.08	100.00

tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

SCORE	LINE
94.12	100.00

tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Line Coverage for Module : i2c_fifo_sync_sram_adapter ( parameter Width=13,Depth=268,SramAw=9,SramBaseAddr=192,DepthW=9,OupBufDepth=2,InpBufDepthW=2,OupBufDepthW=2,SramPtrW=9,SramDepthW=9,SramAddrLeadingZeros=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.59	100.00

tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T3,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T68
1	1	Covered	T1,T3,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T6

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T3,T5,T6
1	0	Covered	T143,T76,T131

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T143,T76,T131
1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T143,T76,T131
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T6

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T6

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T6

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Module : i2c_fifo_sync_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T5,T6
1	0	-	Covered	T1,T3,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : i2c_fifo_sync_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	5156	5156	0	0
MinimalSramFifoDepth_A	5156	5156	0	0
NoErr_A	1531018060	1530342112	0	0
NoSramReadWhenEmpty_A	1531018060	1198945906	0	0
NoSramWriteWhenFull_A	1531018060	23674888	0	0
OupBufWreadyAfterSramRead_A	1531018060	719755	0	0
SramRvalidAfterRead_A	1531018060	719755	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5156	5156	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5156	5156	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531018060	1530342112	0	0
T1	57168	56856	0	0
T2	7504	7164	0	0
T3	763300	762788	0	0
T4	6632	6272	0	0
T5	198284	198076	0	0
T6	385640	385420	0	0
T7	825700	824880	0	0
T8	162080	161700	0	0
T9	884496	884088	0	0
T10	647976	647704	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531018060	1198945906	0	0
T1	57168	48282	0	0
T2	7504	7164	0	0
T3	763300	732617	0	0
T4	6632	6272	0	0
T5	198284	175421	0	0
T6	385640	322894	0	0
T7	825700	692340	0	0
T8	162080	132988	0	0
T9	884496	1352912	0	0
T10	647976	498300	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531018060	23674888	0	0
T7	412850	45419	0	0
T8	81040	0	0	0
T9	442248	103527	0	0
T10	323988	2565	0	0
T11	862686	10252	0	0
T16	228328	8	0	0
T17	0	15	0	0
T27	294591	70308	0	0
T28	111084	0	0	0
T30	0	54972	0	0
T32	25628	0	0	0
T33	126747	0	0	0
T52	151876	0	0	0
T55	392199	939181	0	0
T67	0	57836	0	0
T77	0	27415	0	0
T142	0	43607	0	0
T148	0	142	0	0
T149	0	2701	0	0
T150	0	3043	0	0
T151	0	3795	0	0
T152	0	15284	0	0
T153	0	495	0	0
T154	0	386754	0	0
T155	0	19	0	0
T156	0	2182	0	0
T157	137545	0	0	0
T158	964706	0	0	0
T159	256757	0	0	0
T160	239710	0	0	0
T161	2917	0	0	0
T162	75829	0	0	0
T163	253831	0	0	0
T164	124377	0	0	0
T165	211423	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531018060	719755	0	0
T3	190825	42	0	0
T4	1658	0	0	0
T5	49571	86	0	0
T6	289230	158	0	0
T7	825700	6010	0	0
T8	162080	89	0	0
T9	884496	2096	0	0
T10	647976	744	0	0
T11	1150248	235	0	0
T12	0	214	0	0
T18	0	593	0	0
T23	0	102	0	0
T24	0	147	0	0
T27	294591	0	0	0
T28	111084	0	0	0
T29	0	396	0	0
T32	51256	31	0	0
T33	126747	1	0	0
T41	0	49	0	0
T52	0	42	0	0
T55	130733	544	0	0
T67	0	990	0	0
T141	0	210	0	0
T166	0	181	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531018060	719755	0	0
T3	190825	42	0	0
T4	1658	0	0	0
T5	49571	86	0	0
T6	289230	158	0	0
T7	825700	6010	0	0
T8	162080	89	0	0
T9	884496	2096	0	0
T10	647976	744	0	0
T11	1150248	235	0	0
T12	0	214	0	0
T18	0	593	0	0
T23	0	102	0	0
T24	0	147	0	0
T27	294591	0	0	0
T28	111084	0	0	0
T29	0	396	0	0
T32	51256	31	0	0
T33	126747	1	0	0
T41	0	49	0	0
T52	0	42	0	0
T55	130733	544	0	0
T67	0	990	0	0
T141	0	210	0	0
T166	0	181	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	39	76.47
Logical	51	39	76.47
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T11

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T75
1	1	Covered	T6,T8,T11

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
1	0	Not Covered

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T6,T8,T11
1	0	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T27,T30
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T30

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Not Covered
1	1	Covered	T11,T27,T30

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6,T8,T11
1	0	-	Covered	T6,T8,T11
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_tx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1289	1289	0	0
MinimalSramFifoDepth_A	1289	1289	0	0
NoErr_A	382754515	382585528	0	0
NoSramReadWhenEmpty_A	382754515	306681662	0	0
NoSramWriteWhenFull_A	382754515	6537201	0	0
OupBufWreadyAfterSramRead_A	382754515	207954	0	0
SramRvalidAfterRead_A	382754515	207954	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	382585528	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	96355	0	0
T7	206425	206220	0	0
T8	40520	40425	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	306681662	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	77022	0	0
T7	206425	206220	0	0
T8	40520	26991	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	6537201	0	0
T11	287562	10252	0	0
T23	40547	0	0	0
T27	98197	70308	0	0
T28	37028	0	0	0
T29	114810	0	0	0
T30	93096	54972	0	0
T31	0	27321	0	0
T33	42249	0	0	0
T52	151876	0	0	0
T55	130733	0	0	0
T73	0	42044	0	0
T76	0	77730	0	0
T78	0	26404	0	0
T143	0	20795	0	0
T167	0	85474	0	0
T168	0	3271	0	0
T169	903	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	207954	0	0
T6	96410	96	0	0
T7	206425	0	0	0
T8	40520	74	0	0
T9	221124	0	0	0
T10	161994	0	0	0
T11	287562	916	0	0
T23	0	72	0	0
T24	0	63	0	0
T27	98197	315	0	0
T28	37028	35	0	0
T29	0	165	0	0
T30	0	263	0	0
T31	0	178	0	0
T32	12814	0	0	0
T33	42249	0	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	207954	0	0
T6	96410	96	0	0
T7	206425	0	0	0
T8	40520	74	0	0
T9	221124	0	0	0
T10	161994	0	0	0
T11	287562	916	0	0
T23	0	72	0	0
T24	0	63	0	0
T27	98197	315	0	0
T28	37028	35	0	0
T29	0	165	0	0
T30	0	263	0	0
T31	0	178	0	0
T32	12814	0	0	0
T33	42249	0	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T68,T69,T70
1	1	Covered	T1,T3,T5

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T7

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T3,T5,T7
1	0	Covered	T68,T69,T70

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T68,T69,T70
1	Covered	T1,T3,T5

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T68,T69,T70
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T5,T7

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T7

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T7

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T55
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T55

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Not Covered
1	1	Covered	T7,T9,T55

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T3,T5,T7
1	0	-	Covered	T1,T3,T5
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_fmt_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1289	1289	0	0
MinimalSramFifoDepth_A	1289	1289	0	0
NoErr_A	382754515	382585528	0	0
NoSramReadWhenEmpty_A	382754515	322632273	0	0
NoSramWriteWhenFull_A	382754515	16420916	0	0
OupBufWreadyAfterSramRead_A	382754515	162292	0	0
SramRvalidAfterRead_A	382754515	162292	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	382585528	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	96355	0	0
T7	206425	206220	0	0
T8	40520	40425	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	322632273	0	0
T1	14292	5640	0	0
T2	1876	1791	0	0
T3	190825	160526	0	0
T4	1658	1568	0	0
T5	49571	26864	0	0
T6	96410	96355	0	0
T7	206425	147890	0	0
T8	40520	40425	0	0
T9	221124	710982	0	0
T10	161994	161926	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	16420916	0	0
T7	206425	37738	0	0
T8	40520	0	0	0
T9	221124	100471	0	0
T10	161994	0	0	0
T11	287562	0	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T55	130733	939181	0	0
T67	0	57781	0	0
T77	0	27415	0	0
T142	0	43607	0	0
T152	0	15274	0	0
T154	0	386754	0	0
T155	0	19	0	0
T156	0	2182	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	162292	0	0
T3	190825	42	0	0
T4	1658	0	0	0
T5	49571	86	0	0
T6	96410	0	0	0
T7	206425	2388	0	0
T8	40520	0	0	0
T9	221124	977	0	0
T10	161994	0	0	0
T11	287562	0	0	0
T32	12814	31	0	0
T33	0	1	0	0
T41	0	49	0	0
T52	0	42	0	0
T55	0	544	0	0
T67	0	928	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	162292	0	0
T3	190825	42	0	0
T4	1658	0	0	0
T5	49571	86	0	0
T6	96410	0	0	0
T7	206425	2388	0	0
T8	40520	0	0	0
T9	221124	977	0	0
T10	161994	0	0	0
T11	287562	0	0	0
T32	12814	31	0	0
T33	0	1	0	0
T41	0	49	0	0
T52	0	42	0	0
T55	0	544	0	0
T67	0	928	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
156	1	1
157	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	42	82.35
Logical	51	42	82.35
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17
1	1	Covered	T6,T8,T11

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T6,T8,T11

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
1	0	Covered	T143,T76,T131

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T143,T76,T131
1	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T143,T76,T131
0	1	Covered	T6,T8,T11
1	0	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T11
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T17

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Not Covered
1	1	Covered	T16,T17

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6,T8,T11
1	0	-	Covered	T6,T8,T11
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_acq_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1289	1289	0	0
MinimalSramFifoDepth_A	1289	1289	0	0
NoErr_A	382754515	382585528	0	0
NoSramReadWhenEmpty_A	382754515	223205093	0	0
NoSramWriteWhenFull_A	382754515	23	0	0
OupBufWreadyAfterSramRead_A	382754515	171709	0	0
SramRvalidAfterRead_A	382754515	171709	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	382585528	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	96355	0	0
T7	206425	206220	0	0
T8	40520	40425	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	223205093	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	53162	0	0
T7	206425	206220	0	0
T8	40520	25147	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	23	0	0
T16	228328	8	0	0
T17	0	15	0	0
T157	137545	0	0	0
T158	964706	0	0	0
T159	256757	0	0	0
T160	239710	0	0	0
T161	2917	0	0	0
T162	75829	0	0	0
T163	253831	0	0	0
T164	124377	0	0	0
T165	211423	0	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	171709	0	0
T6	96410	158	0	0
T7	206425	0	0	0
T8	40520	89	0	0
T9	221124	0	0	0
T10	161994	0	0	0
T11	287562	235	0	0
T12	0	214	0	0
T18	0	593	0	0
T23	0	102	0	0
T24	0	147	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T29	0	396	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T141	0	210	0	0
T166	0	181	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	171709	0	0
T6	96410	158	0	0
T7	206425	0	0	0
T8	40520	89	0	0
T9	221124	0	0	0
T10	161994	0	0	0
T11	287562	235	0	0
T12	0	214	0	0
T18	0	593	0	0
T23	0	102	0	0
T24	0	147	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T29	0	396	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T141	0	210	0	0
T166	0	181	0	0

Line Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
TOTAL		44	44	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	28	28	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	249	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
121	1	1
125	1	1
150	1	1
151	1	1
153	1	1
154	1	1
162	1	1
164	1	1
165	1	1
167	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
183	1	1
184	1	1
185	1	1
187	1	1
			MISSING_ELSE
191	1	1
196	1	1
198	1	1
199	1	1
200	1	1
204	1	1
205	1	1
206	1	1
207	1	1
212	1	1
213	1	1
214	1	1
215	1	1
220	1	1
221	1	1
222	1	1
223	1	1
228	1	1
236	1	1
240	1	1
244	1	1
249	1	1

---

Cond Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       120
 EXPRESSION (fifo_wvalid_i && fifo_wready_o)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T3,T5,T7

 LINE       125
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T71,T72,T51
1	1	Covered	T7,T9,T10

 LINE       150
 EXPRESSION (sram_access && sram_write_o)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       151
 EXPRESSION (sram_access && ((!sram_write_o)))
             -----1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       162
 EXPRESSION (clr_i ? 1'b0 : sram_incr_rd_ptr)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION (( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) ) || (fifo_rvalid_o && fifo_rready_i))
             -------------------------------1-------------------------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T10
0	1	Covered	T7,T9,T10
1	0	Covered	T170,T71,T72

 LINE       196
 SUB-EXPRESSION ( ! ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full) )
                    ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T170,T71,T72
1	Covered	T7,T9,T10

 LINE       196
 SUB-EXPRESSION ((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)
                 -------------------1-------------------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T170,T71,T72
0	1	Covered	T7,T9,T10
1	0	Covered	T7,T9,T10

 LINE       196
 SUB-EXPRESSION (oup_buf_almost_full && oup_buf_wvalid)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       196
 SUB-EXPRESSION (fifo_rvalid_o && fifo_rready_i)
                 ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       204
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       207
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       212
 EXPRESSION (oup_buf_wready && ((!sram_read_in_prev_cyc_q)))
             -------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T2,T3

 LINE       220
 EXPRESSION (((!sram_full)) && inp_buf_rvalid)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T9,T10

 LINE       223
 EXPRESSION (((!sram_full)) && sram_gnt_i)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T9,T10

 LINE       236
 EXPRESSION (inp_buf_wready && ( ! (sram_full && oup_buf_full) ))
             -------1------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T10
1	1	Covered	T1,T2,T3

 LINE       236
 SUB-EXPRESSION ( ! (sram_full && oup_buf_full) )
                    -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       236
 SUB-EXPRESSION (sram_full && oup_buf_full)
                 ----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T10
1	0	Not Covered
1	1	Covered	T7,T9,T10

---

Branch Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	162	2	2	100.00
IF	164	2	2	100.00
IF	183	2	2	100.00
IF	191	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifo_sync_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(clr_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (sram_read_in_prev_cyc_q)

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!sram_empty))
-2-:	196	if (((!((oup_buf_almost_full && oup_buf_wvalid) || oup_buf_full)) || (fifo_rvalid_o && fifo_rready_i)))
-3-:	212	if ((oup_buf_wready && (!sram_read_in_prev_cyc_q)))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T7,T9,T10
1	0	-	Covered	T7,T9,T10
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i2c_core.u_fifos.u_rx_fifo_sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MinimalSramAw_A	1289	1289	0	0
MinimalSramFifoDepth_A	1289	1289	0	0
NoErr_A	382754515	382585528	0	0
NoSramReadWhenEmpty_A	382754515	346426878	0	0
NoSramWriteWhenFull_A	382754515	716748	0	0
OupBufWreadyAfterSramRead_A	382754515	177800	0	0
SramRvalidAfterRead_A	382754515	177800	0	0

MinimalSramAw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

MinimalSramFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1289	1289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NoErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	382585528	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	96355	0	0
T7	206425	206220	0	0
T8	40520	40425	0	0
T9	221124	221022	0	0
T10	161994	161926	0	0

NoSramReadWhenEmpty_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	346426878	0	0
T1	14292	14214	0	0
T2	1876	1791	0	0
T3	190825	190697	0	0
T4	1658	1568	0	0
T5	49571	49519	0	0
T6	96410	96355	0	0
T7	206425	132010	0	0
T8	40520	40425	0	0
T9	221124	199886	0	0
T10	161994	12522	0	0

NoSramWriteWhenFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	716748	0	0
T7	206425	7681	0	0
T8	40520	0	0	0
T9	221124	3056	0	0
T10	161994	2565	0	0
T11	287562	0	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T55	130733	0	0	0
T67	0	55	0	0
T148	0	142	0	0
T149	0	2701	0	0
T150	0	3043	0	0
T151	0	3795	0	0
T152	0	10	0	0
T153	0	495	0	0

OupBufWreadyAfterSramRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	177800	0	0
T7	206425	3622	0	0
T8	40520	0	0	0
T9	221124	1119	0	0
T10	161994	744	0	0
T11	287562	0	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T55	130733	0	0	0
T67	0	62	0	0
T148	0	806	0	0
T149	0	806	0	0
T150	0	992	0	0
T151	0	1116	0	0
T152	0	67	0	0
T153	0	868	0	0

SramRvalidAfterRead_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382754515	177800	0	0
T7	206425	3622	0	0
T8	40520	0	0	0
T9	221124	1119	0	0
T10	161994	744	0	0
T11	287562	0	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T55	130733	0	0	0
T67	0	62	0	0
T148	0	806	0	0
T149	0	806	0	0
T150	0	992	0	0
T151	0	1116	0	0
T152	0	67	0	0
T153	0	868	0	0