Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	383400905	0	0	0
ctrl_rd_A	383400905	2192	0	0
host_fifo_config_rd_A	383400905	5710	0	0
host_nack_handler_timeout_rd_A	383400905	1498	0	0
host_timeout_ctrl_rd_A	383400905	1404	0	0
intr_enable_rd_A	383400905	3946	0	0
ovrd_rd_A	383400905	2158	0	0
target_fifo_config_rd_A	383400905	1630	0	0
target_id_rd_A	383400905	1722	0	0
target_timeout_ctrl_rd_A	383400905	1434	0	0
timeout_ctrl_rd_A	383400905	1654	0	0
timing0_rd_A	383400905	1517	0	0
timing1_rd_A	383400905	1476	0	0
timing2_rd_A	383400905	1478	0	0
timing3_rd_A	383400905	1600	0	0
timing4_rd_A	383400905	1510	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	2192	0	0
T82	1291	1	0	0
T83	2311	13	0	0
T84	7139	32	0	0
T85	1825	9	0	0
T86	3551	11	0	0
T87	15046	63	0	0
T88	12078	54	0	0
T89	2931	68	0	0
T90	2693	7	0	0
T91	2208	4	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	5710	0	0
T7	206425	321	0	0
T8	40520	0	0	0
T9	221124	0	0	0
T10	161994	0	0	0
T11	287562	0	0	0
T27	98197	0	0	0
T28	37028	0	0	0
T32	12814	0	0	0
T33	42249	0	0	0
T55	130733	0	0	0
T92	0	127	0	0
T93	0	251	0	0
T94	0	164	0	0
T95	0	271	0	0
T96	0	143	0	0
T97	0	221	0	0
T98	0	167	0	0
T99	0	140	0	0
T100	0	217	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1498	0	0
T82	1291	9	0	0
T83	2311	15	0	0
T84	7139	49	0	0
T85	1825	4	0	0
T86	3551	51	0	0
T87	15046	38	0	0
T88	12078	57	0	0
T89	2931	15	0	0
T90	2693	6	0	0
T91	2208	4	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1404	0	0
T82	1291	8	0	0
T83	2311	15	0	0
T84	7139	57	0	0
T85	1825	5	0	0
T86	3551	6	0	0
T87	15046	14	0	0
T88	12078	37	0	0
T89	2931	20	0	0
T90	2693	1	0	0
T91	2208	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	3946	0	0
T82	0	1	0	0
T93	141189	22	0	0
T96	0	12	0	0
T101	0	47	0	0
T102	0	14	0	0
T103	0	15	0	0
T104	0	8	0	0
T105	0	7	0	0
T106	0	16	0	0
T107	0	11	0	0
T108	52878	0	0	0
T109	87566	0	0	0
T110	123784	0	0	0
T111	190463	0	0	0
T112	16877	0	0	0
T113	2513	0	0	0
T114	1460	0	0	0
T115	699551	0	0	0
T116	79198	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	2158	0	0
T37	736541	0	0	0
T79	217348	0	0	0
T117	1110	48	0	0
T118	0	56	0	0
T119	0	48	0	0
T120	0	35	0	0
T121	0	30	0	0
T122	0	48	0	0
T123	0	16	0	0
T124	0	96	0	0
T125	0	38	0	0
T126	0	38	0	0
T127	72442	0	0	0
T128	158534	0	0	0
T129	122216	0	0	0
T130	442056	0	0	0
T131	504577	0	0	0
T132	1067	0	0	0
T133	1721	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1630	0	0
T82	1291	11	0	0
T83	2311	11	0	0
T84	7139	43	0	0
T85	1825	15	0	0
T86	3551	66	0	0
T87	15046	42	0	0
T88	12078	25	0	0
T89	2931	27	0	0
T91	2208	14	0	0
T134	12985	283	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1722	0	0
T82	1291	4	0	0
T83	2311	23	0	0
T84	7139	43	0	0
T85	1825	25	0	0
T86	3551	2	0	0
T87	15046	39	0	0
T88	12078	6	0	0
T89	2931	19	0	0
T91	2208	17	0	0
T134	12985	252	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1434	0	0
T82	1291	5	0	0
T83	2311	4	0	0
T84	7139	31	0	0
T85	1825	8	0	0
T86	3551	7	0	0
T87	15046	31	0	0
T88	12078	27	0	0
T89	2931	9	0	0
T91	2208	14	0	0
T134	12985	222	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1654	0	0
T82	1291	9	0	0
T83	2311	29	0	0
T84	7139	25	0	0
T85	1825	16	0	0
T86	3551	17	0	0
T87	15046	46	0	0
T88	12078	17	0	0
T89	2931	30	0	0
T90	2693	15	0	0
T91	2208	3	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1517	0	0
T82	1291	4	0	0
T83	2311	7	0	0
T84	7139	44	0	0
T85	1825	17	0	0
T86	3551	12	0	0
T87	15046	27	0	0
T88	12078	25	0	0
T89	2931	17	0	0
T90	2693	9	0	0
T91	2208	9	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1476	0	0
T83	2311	10	0	0
T84	7139	31	0	0
T85	1825	10	0	0
T86	3551	13	0	0
T87	15046	35	0	0
T88	12078	38	0	0
T89	2931	26	0	0
T90	2693	11	0	0
T91	2208	10	0	0
T134	12985	264	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1478	0	0
T82	1291	8	0	0
T83	2311	4	0	0
T84	7139	35	0	0
T85	1825	8	0	0
T86	3551	16	0	0
T87	15046	26	0	0
T88	12078	44	0	0
T89	2931	24	0	0
T90	2693	5	0	0
T91	2208	8	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1600	0	0
T82	1291	3	0	0
T83	2311	16	0	0
T84	7139	49	0	0
T85	1825	8	0	0
T86	3551	41	0	0
T87	15046	43	0	0
T88	12078	25	0	0
T89	2931	15	0	0
T90	2693	10	0	0
T91	2208	6	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383400905	1510	0	0
T82	1291	9	0	0
T83	2311	13	0	0
T84	7139	36	0	0
T85	1825	13	0	0
T86	3551	23	0	0
T87	15046	58	0	0
T88	12078	29	0	0
T89	2931	34	0	0
T90	2693	3	0	0
T91	2208	7	0	0