Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

168150

1

T1

134

T2

63

T3

513

ack

14414

1

T1

32

T2

13

T3

12

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	671	1			T1	1		T2	1		T3	1
high	37780	1			T1	33		T2	27		T3	110
med	67663	1			T1	58		T2	22		T3	199
sml	75734	1			T1	74		T2	26		T3	210
all_zero	716	1			T3	5		T6	2		T40	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90998

1

T1

80

T2

27

T3

270

auto[1]

91566

1

T1

86

T2

49

T3

255

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125141

1

T1

119

T2

55

T3

339

auto[1]

57423

1

T1

47

T2

21

T3

186

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174896

1

T1

153

T2

76

T3

518

auto[1]

7668

1

T1

13

T3

7

T6

15

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172675

1

T1

139

T2

63

T3

515

auto[1]

9889

1

T1

27

T2

13

T3

10

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173648

1

T1

140

T2

63

T3

517

auto[1]

8916

1

T1

26

T2

13

T3

8

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90998

1

T1

80

T2

27

T3

270

auto[1]

91566

1

T1

86

T2

49

T3

255

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125141

1

T1

119

T2

55

T3

339

auto[1]

57423

1

T1

47

T2

21

T3

186

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174896

1

T1

153

T2

76

T3

518

auto[1]

7668

1

T1

13

T3

7

T6

15

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172675

1

T1

139

T2

63

T3

515

auto[1]

9889

1

T1

27

T2

13

T3

10

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173648

1

T1

140

T2

63

T3

517

auto[1]

8916

1

T1

26

T2

13

T3

8

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

1

1

T255

1

-

-

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

6

1

T256

1

T257

1

T258

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T42

1

T82

1

-

-

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

274

1

T1

1

T6

2

T43

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

126

1

T1

1

T6

1

T70

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

151

1

T3

1

T6

3

T70

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

523

1

T1

3

T3

3

T70

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

255

1

T1

2

T6

1

T37

2

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

275

1

T1

2

T3

1

T70

2

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

501

1

T1

2

T3

1

T6

2

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

288

1

T6

1

T70

3

T37

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

271

1

T1

1

T3

1

T6

3

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

12

1

T51

1

T151

1

T83

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T121

1

T259

1

-

-

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

6

1

T260

1

T261

1

T262

1

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	53396	1			T1	37		T2	10		T3	171
write_address_byte	9889	1			T1	27		T2	13		T3	10
read_with_ack	2282	1			T3	3		T10	15		T43	1
read_with_nack	5386	1			T1	13		T3	4		T6	15
stop_byte	8916	1			T1	26		T2	13		T3	8
write_address_byte_nak	4921	1			T1	20		T3	8		T6	24
data_byte_nack	168150	1			T1	134		T2	63		T3	513
stop_byte_nack	5386	1			T1	19		T2	13		T3	7
nakok_byte_nack	84390	1			T1	68		T2	43		T3	246
nakok_addr_byte_nack	2441	1			T1	11		T3	2		T6	13