Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.71 100.00 98.85 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.71 100.00 98.85 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.71 100.00 98.85 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.56 98.59 96.63 100.00 97.58 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.72 100.00 100.00 94.87 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_acq_fifo_next_data 66.67 66.67
u_acqdata_abyte 100.00 100.00
u_acqdata_signal 100.00 100.00
u_alert_test 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_controller_events_arbitration_lost 97.22 100.00 91.67 100.00
u_controller_events_bus_timeout 88.89 100.00 66.67 100.00
u_controller_events_nack 100.00 100.00 100.00 100.00
u_controller_events_unhandled_nack_timeout 88.89 100.00 66.67 100.00
u_ctrl_ack_ctrl_en 100.00 100.00 100.00 100.00
u_ctrl_enablehost 100.00 100.00 100.00 100.00
u_ctrl_enabletarget 100.00 100.00 100.00 100.00
u_ctrl_llpbk 100.00 100.00 100.00 100.00
u_ctrl_multi_controller_monitor_en 100.00 100.00 100.00 100.00
u_ctrl_nack_addr_after_timeout 100.00 100.00 100.00 100.00
u_ctrl_tx_stretch_ctrl_en 100.00 100.00 100.00 100.00
u_fdata0_qe 100.00 100.00 100.00
u_fdata_fbyte 100.00 100.00 100.00 100.00
u_fdata_nakok 100.00 100.00 100.00 100.00
u_fdata_rcont 100.00 100.00 100.00 100.00
u_fdata_readb 100.00 100.00 100.00 100.00
u_fdata_start 100.00 100.00 100.00 100.00
u_fdata_stop 100.00 100.00 100.00 100.00
u_fifo_ctrl0_qe 100.00 100.00 100.00
u_fifo_ctrl_acqrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_fmtrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_rxrst 100.00 100.00 100.00 100.00
u_fifo_ctrl_txrst 100.00 100.00 100.00 100.00
u_host_fifo_config0_qe 100.00 100.00 100.00
u_host_fifo_config_fmt_thresh 100.00 100.00 100.00 100.00
u_host_fifo_config_rx_thresh 100.00 100.00 100.00 100.00
u_host_fifo_status_fmtlvl 100.00 100.00
u_host_fifo_status_rxlvl 100.00 100.00
u_host_nack_handler_timeout_en 100.00 100.00 100.00 100.00
u_host_nack_handler_timeout_val 100.00 100.00 100.00 100.00
u_host_timeout_ctrl 100.00 100.00 100.00 100.00
u_intr_enable_acq_stretch 100.00 100.00 100.00 100.00
u_intr_enable_acq_threshold 100.00 100.00 100.00 100.00
u_intr_enable_cmd_complete 100.00 100.00 100.00 100.00
u_intr_enable_controller_halt 100.00 100.00 100.00 100.00
u_intr_enable_fmt_threshold 100.00 100.00 100.00 100.00
u_intr_enable_host_timeout 100.00 100.00 100.00 100.00
u_intr_enable_rx_overflow 100.00 100.00 100.00 100.00
u_intr_enable_rx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_scl_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_interference 100.00 100.00 100.00 100.00
u_intr_enable_sda_unstable 100.00 100.00 100.00 100.00
u_intr_enable_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_enable_tx_stretch 100.00 100.00 100.00 100.00
u_intr_enable_tx_threshold 100.00 100.00 100.00 100.00
u_intr_enable_unexp_stop 100.00 100.00 100.00 100.00
u_intr_state_acq_stretch 62.59 77.78 50.00 60.00
u_intr_state_acq_threshold 62.59 77.78 50.00 60.00
u_intr_state_cmd_complete 100.00 100.00 100.00 100.00
u_intr_state_controller_halt 62.59 77.78 50.00 60.00
u_intr_state_fmt_threshold 62.59 77.78 50.00 60.00
u_intr_state_host_timeout 100.00 100.00 100.00 100.00
u_intr_state_rx_overflow 100.00 100.00 100.00 100.00
u_intr_state_rx_threshold 62.59 77.78 50.00 60.00
u_intr_state_scl_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_interference 100.00 100.00 100.00 100.00
u_intr_state_sda_unstable 100.00 100.00 100.00 100.00
u_intr_state_stretch_timeout 100.00 100.00 100.00 100.00
u_intr_state_tx_stretch 62.59 77.78 50.00 60.00
u_intr_state_tx_threshold 62.59 77.78 50.00 60.00
u_intr_state_unexp_stop 100.00 100.00 100.00 100.00
u_intr_test_acq_stretch 100.00 100.00
u_intr_test_acq_threshold 100.00 100.00
u_intr_test_cmd_complete 100.00 100.00
u_intr_test_controller_halt 100.00 100.00
u_intr_test_fmt_threshold 100.00 100.00
u_intr_test_host_timeout 100.00 100.00
u_intr_test_rx_overflow 100.00 100.00
u_intr_test_rx_threshold 100.00 100.00
u_intr_test_scl_interference 100.00 100.00
u_intr_test_sda_interference 100.00 100.00
u_intr_test_sda_unstable 100.00 100.00
u_intr_test_stretch_timeout 100.00 100.00
u_intr_test_tx_stretch 100.00 100.00
u_intr_test_tx_threshold 100.00 100.00
u_intr_test_unexp_stop 100.00 100.00
u_ovrd_sclval 100.00 100.00 100.00 100.00
u_ovrd_sdaval 100.00 100.00 100.00 100.00
u_ovrd_txovrden 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_rdata 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_ack_ctrl_stretch 100.00 100.00
u_status_acqempty 100.00 100.00
u_status_acqfull 100.00 100.00
u_status_fmtempty 100.00 100.00
u_status_fmtfull 100.00 100.00
u_status_hostidle 100.00 100.00
u_status_rxempty 100.00 100.00
u_status_rxfull 100.00 100.00
u_status_targetidle 100.00 100.00
u_status_txempty 100.00 100.00
u_status_txfull 100.00 100.00
u_target_ack_ctrl_nack 100.00 100.00
u_target_ack_ctrl_nbytes 100.00 100.00
u_target_events_arbitration_lost 88.89 100.00 66.67 100.00
u_target_events_bus_timeout 88.89 100.00 66.67 100.00
u_target_events_tx_pending 88.89 100.00 66.67 100.00
u_target_fifo_config0_qe 100.00 100.00 100.00
u_target_fifo_config_acq_thresh 100.00 100.00 100.00 100.00
u_target_fifo_config_tx_thresh 100.00 100.00 100.00 100.00
u_target_fifo_status_acqlvl 100.00 100.00
u_target_fifo_status_txlvl 100.00 100.00
u_target_id_address0 100.00 100.00 100.00 100.00
u_target_id_address1 100.00 100.00 100.00 100.00
u_target_id_mask0 100.00 100.00 100.00 100.00
u_target_id_mask1 100.00 100.00 100.00 100.00
u_target_nack_count 81.90 100.00 60.00 85.71
u_target_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_target_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timeout_ctrl_en 100.00 100.00 100.00 100.00
u_timeout_ctrl_mode 100.00 100.00 100.00 100.00
u_timeout_ctrl_val 100.00 100.00 100.00 100.00
u_timing0_thigh 100.00 100.00 100.00 100.00
u_timing0_tlow 100.00 100.00 100.00 100.00
u_timing1_t_f 100.00 100.00 100.00 100.00
u_timing1_t_r 100.00 100.00 100.00 100.00
u_timing2_thd_sta 100.00 100.00 100.00 100.00
u_timing2_tsu_sta 100.00 100.00 100.00 100.00
u_timing3_thd_dat 100.00 100.00 100.00 100.00
u_timing3_tsu_dat 100.00 100.00 100.00 100.00
u_timing4_t_buf 100.00 100.00 100.00 100.00
u_timing4_tsu_sto 100.00 100.00 100.00 100.00
u_txdata 100.00 100.00 100.00 100.00
u_txdata0_qe 100.00 100.00 100.00
u_val_scl_rx 66.67 66.67
u_val_sda_rx 66.67 66.67


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
TOTAL369369100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN116811100.00
CONT_ASSIGN118311100.00
CONT_ASSIGN119911100.00
CONT_ASSIGN121511100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN124711100.00
CONT_ASSIGN126311100.00
CONT_ASSIGN127911100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN131111100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN135911100.00
CONT_ASSIGN137511100.00
CONT_ASSIGN139111100.00
CONT_ASSIGN140711100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN142711100.00
CONT_ASSIGN184211100.00
CONT_ASSIGN187011100.00
CONT_ASSIGN189811100.00
CONT_ASSIGN192611100.00
CONT_ASSIGN195411100.00
CONT_ASSIGN198211100.00
CONT_ASSIGN202311100.00
CONT_ASSIGN205111100.00
CONT_ASSIGN207911100.00
CONT_ASSIGN210711100.00
CONT_ASSIGN214811100.00
CONT_ASSIGN217611100.00
CONT_ASSIGN221711100.00
CONT_ASSIGN224511100.00
CONT_ASSIGN296911100.00
CONT_ASSIGN308711100.00
CONT_ASSIGN310211100.00
CONT_ASSIGN311811100.00
ALWAYS33893333100.00
CONT_ASSIGN342411100.00
ALWAYS342811100.00
CONT_ASSIGN346411100.00
CONT_ASSIGN346611100.00
CONT_ASSIGN346811100.00
CONT_ASSIGN347011100.00
CONT_ASSIGN347211100.00
CONT_ASSIGN347411100.00
CONT_ASSIGN347611100.00
CONT_ASSIGN347811100.00
CONT_ASSIGN348011100.00
CONT_ASSIGN348111100.00
CONT_ASSIGN348311100.00
CONT_ASSIGN348511100.00
CONT_ASSIGN348711100.00
CONT_ASSIGN348911100.00
CONT_ASSIGN349111100.00
CONT_ASSIGN349311100.00
CONT_ASSIGN349511100.00
CONT_ASSIGN349711100.00
CONT_ASSIGN349911100.00
CONT_ASSIGN350111100.00
CONT_ASSIGN350311100.00
CONT_ASSIGN350511100.00
CONT_ASSIGN350711100.00
CONT_ASSIGN350911100.00
CONT_ASSIGN351111100.00
CONT_ASSIGN351211100.00
CONT_ASSIGN351411100.00
CONT_ASSIGN351611100.00
CONT_ASSIGN351811100.00
CONT_ASSIGN352011100.00
CONT_ASSIGN352211100.00
CONT_ASSIGN352411100.00
CONT_ASSIGN352611100.00
CONT_ASSIGN352811100.00
CONT_ASSIGN353011100.00
CONT_ASSIGN353211100.00
CONT_ASSIGN353411100.00
CONT_ASSIGN353611100.00
CONT_ASSIGN353811100.00
CONT_ASSIGN354011100.00
CONT_ASSIGN354211100.00
CONT_ASSIGN354311100.00
CONT_ASSIGN354511100.00
CONT_ASSIGN354611100.00
CONT_ASSIGN354811100.00
CONT_ASSIGN355011100.00
CONT_ASSIGN355211100.00
CONT_ASSIGN355411100.00
CONT_ASSIGN355611100.00
CONT_ASSIGN355811100.00
CONT_ASSIGN356011100.00
CONT_ASSIGN356111100.00
CONT_ASSIGN356211100.00
CONT_ASSIGN356311100.00
CONT_ASSIGN356511100.00
CONT_ASSIGN356711100.00
CONT_ASSIGN356911100.00
CONT_ASSIGN357111100.00
CONT_ASSIGN357311100.00
CONT_ASSIGN357511100.00
CONT_ASSIGN357611100.00
CONT_ASSIGN357811100.00
CONT_ASSIGN358011100.00
CONT_ASSIGN358211100.00
CONT_ASSIGN358411100.00
CONT_ASSIGN358511100.00
CONT_ASSIGN358711100.00
CONT_ASSIGN358911100.00
CONT_ASSIGN359011100.00
CONT_ASSIGN359211100.00
CONT_ASSIGN359411100.00
CONT_ASSIGN359511100.00
CONT_ASSIGN359611100.00
CONT_ASSIGN359711100.00
CONT_ASSIGN359911100.00
CONT_ASSIGN360111100.00
CONT_ASSIGN360311100.00
CONT_ASSIGN360411100.00
CONT_ASSIGN360511100.00
CONT_ASSIGN360711100.00
CONT_ASSIGN360911100.00
CONT_ASSIGN361011100.00
CONT_ASSIGN361211100.00
CONT_ASSIGN361411100.00
CONT_ASSIGN361511100.00
CONT_ASSIGN361711100.00
CONT_ASSIGN361911100.00
CONT_ASSIGN362011100.00
CONT_ASSIGN362211100.00
CONT_ASSIGN362411100.00
CONT_ASSIGN362511100.00
CONT_ASSIGN362711100.00
CONT_ASSIGN362911100.00
CONT_ASSIGN363011100.00
CONT_ASSIGN363211100.00
CONT_ASSIGN363411100.00
CONT_ASSIGN363611100.00
CONT_ASSIGN363711100.00
CONT_ASSIGN363911100.00
CONT_ASSIGN364111100.00
CONT_ASSIGN364311100.00
CONT_ASSIGN364511100.00
CONT_ASSIGN364611100.00
CONT_ASSIGN364711100.00
CONT_ASSIGN364911100.00
CONT_ASSIGN365011100.00
CONT_ASSIGN365211100.00
CONT_ASSIGN365311100.00
CONT_ASSIGN365511100.00
CONT_ASSIGN365711100.00
CONT_ASSIGN365811100.00
CONT_ASSIGN366111100.00
CONT_ASSIGN366211100.00
CONT_ASSIGN366411100.00
CONT_ASSIGN366611100.00
CONT_ASSIGN366711100.00
CONT_ASSIGN366811100.00
CONT_ASSIGN367011100.00
CONT_ASSIGN367211100.00
CONT_ASSIGN367311100.00
CONT_ASSIGN367511100.00
CONT_ASSIGN367711100.00
CONT_ASSIGN367911100.00
CONT_ASSIGN368111100.00
CONT_ASSIGN368211100.00
CONT_ASSIGN368411100.00
CONT_ASSIGN368611100.00
CONT_ASSIGN368811100.00
ALWAYS36923333100.00
ALWAYS3729126126100.00
CONT_ASSIGN396200
CONT_ASSIGN397011100.00
CONT_ASSIGN397111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
1168 1 1
1183 1 1
1199 1 1
1215 1 1
1231 1 1
1247 1 1
1263 1 1
1279 1 1
1295 1 1
1311 1 1
1327 1 1
1343 1 1
1359 1 1
1375 1 1
1391 1 1
1407 1 1
1413 1 1
1427 1 1
1842 1 1
1870 1 1
1898 1 1
1926 1 1
1954 1 1
1982 1 1
2023 1 1
2051 1 1
2079 1 1
2107 1 1
2148 1 1
2176 1 1
2217 1 1
2245 1 1
2969 1 1
3087 1 1
3102 1 1
3118 1 1
3389 1 1
3390 1 1
3391 1 1
3392 1 1
3393 1 1
3394 1 1
3395 1 1
3396 1 1
3397 1 1
3398 1 1
3399 1 1
3400 1 1
3401 1 1
3402 1 1
3403 1 1
3404 1 1
3405 1 1
3406 1 1
3407 1 1
3408 1 1
3409 1 1
3410 1 1
3411 1 1
3412 1 1
3413 1 1
3414 1 1
3415 1 1
3416 1 1
3417 1 1
3418 1 1
3419 1 1
3420 1 1
3421 1 1
3424 1 1
3428 1 1
3464 1 1
3466 1 1
3468 1 1
3470 1 1
3472 1 1
3474 1 1
3476 1 1
3478 1 1
3480 1 1
3481 1 1
3483 1 1
3485 1 1
3487 1 1
3489 1 1
3491 1 1
3493 1 1
3495 1 1
3497 1 1
3499 1 1
3501 1 1
3503 1 1
3505 1 1
3507 1 1
3509 1 1
3511 1 1
3512 1 1
3514 1 1
3516 1 1
3518 1 1
3520 1 1
3522 1 1
3524 1 1
3526 1 1
3528 1 1
3530 1 1
3532 1 1
3534 1 1
3536 1 1
3538 1 1
3540 1 1
3542 1 1
3543 1 1
3545 1 1
3546 1 1
3548 1 1
3550 1 1
3552 1 1
3554 1 1
3556 1 1
3558 1 1
3560 1 1
3561 1 1
3562 1 1
3563 1 1
3565 1 1
3567 1 1
3569 1 1
3571 1 1
3573 1 1
3575 1 1
3576 1 1
3578 1 1
3580 1 1
3582 1 1
3584 1 1
3585 1 1
3587 1 1
3589 1 1
3590 1 1
3592 1 1
3594 1 1
3595 1 1
3596 1 1
3597 1 1
3599 1 1
3601 1 1
3603 1 1
3604 1 1
3605 1 1
3607 1 1
3609 1 1
3610 1 1
3612 1 1
3614 1 1
3615 1 1
3617 1 1
3619 1 1
3620 1 1
3622 1 1
3624 1 1
3625 1 1
3627 1 1
3629 1 1
3630 1 1
3632 1 1
3634 1 1
3636 1 1
3637 1 1
3639 1 1
3641 1 1
3643 1 1
3645 1 1
3646 1 1
3647 1 1
3649 1 1
3650 1 1
3652 1 1
3653 1 1
3655 1 1
3657 1 1
3658 1 1
3661 1 1
3662 1 1
3664 1 1
3666 1 1
3667 1 1
3668 1 1
3670 1 1
3672 1 1
3673 1 1
3675 1 1
3677 1 1
3679 1 1
3681 1 1
3682 1 1
3684 1 1
3686 1 1
3688 1 1
3692 1 1
3693 1 1
3694 1 1
3695 1 1
3696 1 1
3697 1 1
3698 1 1
3699 1 1
3700 1 1
3701 1 1
3702 1 1
3703 1 1
3704 1 1
3705 1 1
3706 1 1
3707 1 1
3708 1 1
3709 1 1
3710 1 1
3711 1 1
3712 1 1
3713 1 1
3714 1 1
3715 1 1
3716 1 1
3717 1 1
3718 1 1
3719 1 1
3720 1 1
3721 1 1
3722 1 1
3723 1 1
3724 1 1
3729 1 1
3730 1 1
3732 1 1
3733 1 1
3734 1 1
3735 1 1
3736 1 1
3737 1 1
3738 1 1
3739 1 1
3740 1 1
3741 1 1
3742 1 1
3743 1 1
3744 1 1
3745 1 1
3746 1 1
3750 1 1
3751 1 1
3752 1 1
3753 1 1
3754 1 1
3755 1 1
3756 1 1
3757 1 1
3758 1 1
3759 1 1
3760 1 1
3761 1 1
3762 1 1
3763 1 1
3764 1 1
3768 1 1
3769 1 1
3770 1 1
3771 1 1
3772 1 1
3773 1 1
3774 1 1
3775 1 1
3776 1 1
3777 1 1
3778 1 1
3779 1 1
3780 1 1
3781 1 1
3782 1 1
3786 1 1
3790 1 1
3791 1 1
3792 1 1
3793 1 1
3794 1 1
3795 1 1
3796 1 1
3800 1 1
3801 1 1
3802 1 1
3803 1 1
3804 1 1
3805 1 1
3806 1 1
3807 1 1
3808 1 1
3809 1 1
3810 1 1
3814 1 1
3818 1 1
3819 1 1
3820 1 1
3821 1 1
3822 1 1
3823 1 1
3827 1 1
3828 1 1
3829 1 1
3830 1 1
3834 1 1
3835 1 1
3839 1 1
3840 1 1
3844 1 1
3845 1 1
3849 1 1
3850 1 1
3854 1 1
3855 1 1
3856 1 1
3860 1 1
3861 1 1
3865 1 1
3866 1 1
3870 1 1
3871 1 1
3875 1 1
3876 1 1
3880 1 1
3881 1 1
3885 1 1
3886 1 1
3890 1 1
3891 1 1
3892 1 1
3896 1 1
3897 1 1
3898 1 1
3899 1 1
3903 1 1
3904 1 1
3908 1 1
3912 1 1
3916 1 1
3917 1 1
3921 1 1
3925 1 1
3926 1 1
3930 1 1
3934 1 1
3935 1 1
3939 1 1
3940 1 1
3941 1 1
3942 1 1
3946 1 1
3947 1 1
3948 1 1
3962 unreachable
3970 1 1
3971 1 1


Cond Coverage for Module : i2c_reg_top
TotalCoveredPercent
Conditions34734398.85
Logical34734398.85
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT174,T175,T176
10CoveredT96,T150,T190

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT174,T175,T176
010CoveredT96,T150,T190
100CoveredT174,T175,T176

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT96,T150,T190
010CoveredT95,T189,T191
100Not Covered

 LINE       3390
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3391
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3392
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3393
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3394
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3395
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3396
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       3397
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3398
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3399
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3400
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3401
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3402
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T8

 LINE       3403
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3404
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3405
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3406
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3407
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3408
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3409
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3410
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3411
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       3412
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       3413
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T8

 LINE       3414
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       3415
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3416
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3417
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ACK_CTRL_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       3418
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQ_FIFO_NEXT_DATA_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3419
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3420
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T6,T8

 LINE       3421
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_EVENTS_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T40,T33

 LINE       3424
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       3424
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       3428
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT95,T150,T190

 LINE       3428
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
32 (addr_hit[31] & ((|(4'...CoveredT9,T40,T33
31 (addr_hit[30] & ((|(4'...CoveredT9,T40,T33
30 (addr_hit[29] & ((|(4'...CoveredT9,T40,T33
29 (addr_hit[28] & ((|(4'...CoveredT9,T40,T33
28 (addr_hit[27] & ((|(4'...CoveredT9,T40,T33
27 (addr_hit[26] & ((|(4'...CoveredT9,T40,T33
26 (addr_hit[25] & ((|(4'...CoveredT9,T40,T33
25 (addr_hit[24] & ((|(4'...CoveredT9,T40,T33
24 (addr_hit[23] & ((|(4'...CoveredT9,T40,T33
23 (addr_hit[22] & ((|(4'...CoveredT4,T5,T7
22 (addr_hit[21] & ((|(4'...CoveredT9,T40,T33
21 (addr_hit[20] & ((|(4'...CoveredT9,T40,T33
20 (addr_hit[19] & ((|(4'...CoveredT9,T40,T33
19 (addr_hit[18] & ((|(4'...CoveredT9,T40,T33
18 (addr_hit[17] & ((|(4'...CoveredT9,T40,T33
17 (addr_hit[16] & ((|(4'...CoveredT9,T40,T33
16 (addr_hit[15] & ((|(4'...CoveredT9,T40,T33
15 (addr_hit[14] & ((|(4'...CoveredT9,T40,T33
14 (addr_hit[13] & ((|(4'...CoveredT9,T40,T33
13 (addr_hit[12] & ((|(4'...CoveredT5,T7,T8
12 (addr_hit[11] & ((|(4'...CoveredT9,T40,T33
11 (addr_hit[10] & ((|(4'...CoveredT9,T40,T33
10 (addr_hit[9] & ((|(4'b...CoveredT9,T40,T33
9 (addr_hit[8] & ((|(4'b...CoveredT9,T40,T33
8 (addr_hit[7] & ((|(4'b...CoveredT9,T40,T33
7 (addr_hit[6] & ((|(4'b...CoveredT1,T3,T6
6 (addr_hit[5] & ((|(4'b...CoveredT1,T2,T3
5 (addr_hit[4] & ((|(4'b...CoveredT9,T40,T33
4 (addr_hit[3] & ((|(4'b...CoveredT9,T40,T33
3 (addr_hit[2] & ((|(4'b...CoveredT9,T40,T33
2 (addr_hit[1] & ((|(4'b...CoveredT9,T40,T33
1 (addr_hit[0] & ((|(4'b...CoveredT1,T3,T4

 LINE       3428
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       3428
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       3428
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T6
11CoveredT1,T3,T6

 LINE       3428
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT5,T7,T8

 LINE       3428
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT40,T33,T34
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT4,T5,T7

 LINE       3428
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T8
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT40,T33,T34
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T9
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T6,T8
11CoveredT9,T40,T33

 LINE       3428
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T40,T33
11CoveredT9,T40,T33

 LINE       3464
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT189,T97,T99
111CoveredT1,T2,T3

 LINE       3481
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT191,T97,T98
111CoveredT1,T2,T3

 LINE       3512
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT189,T191,T97
111CoveredT38,T82,T151

 LINE       3543
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT97,T99,T192
111CoveredT173,T170,T171

 LINE       3546
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT97,T98,T99
111CoveredT1,T2,T3

 LINE       3561
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT96,T193
111CoveredT1,T2,T3

 LINE       3562
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T6
110CoveredT190,T194,T195
111CoveredT1,T3,T6

 LINE       3563
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT189,T99,T196
111CoveredT1,T2,T3

 LINE       3576
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT97,T99,T196
111CoveredT1,T2,T3

 LINE       3585
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT189,T191,T98
111CoveredT1,T2,T3

 LINE       3590
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT189,T97,T99
111CoveredT1,T2,T3

 LINE       3595
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT197
111CoveredT37,T61,T38

 LINE       3596
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT5,T7,T8
110CoveredT96,T98,T198
111CoveredT5,T7,T8

 LINE       3597
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT96,T189,T97
111CoveredT78,T79,T80

 LINE       3604
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT190,T199,T200
111Not Covered

 LINE       3605
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT196,T192,T149
111CoveredT1,T2,T3

 LINE       3610
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT191,T97,T99
111CoveredT1,T2,T3

 LINE       3615
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT97,T99,T192
111CoveredT1,T2,T3

 LINE       3620
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT191,T99,T192
111CoveredT1,T2,T3

 LINE       3625
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT190,T189,T191
111CoveredT1,T2,T3

 LINE       3630
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT190,T189,T191
111CoveredT1,T2,T3

 LINE       3637
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT97,T99,T192
111CoveredT4,T5,T7

 LINE       3646
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT199,T200
111CoveredT4,T5,T7

 LINE       3647
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T8
110CoveredT191,T97,T99
111CoveredT4,T5,T8

 LINE       3650
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T7
110CoveredT189,T97,T99
111CoveredT4,T5,T7

 LINE       3653
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT99,T199,T192
111CoveredT95,T96,T150

 LINE       3658
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT201,T202
111CoveredT95,T96,T150

 LINE       3661
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T8,T9
110CoveredT98,T194
111CoveredT95,T96,T150

 LINE       3662
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T8,T9
110CoveredT191,T97,T192
111CoveredT7,T8,T9

 LINE       3667
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT197,T203
111Not Covered

 LINE       3668
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT150,T191,T97
111CoveredT44,T45,T46

 LINE       3673
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T6,T8
110CoveredT191,T99,T196
111CoveredT3,T6,T8

 LINE       3682
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T40,T33
110CoveredT97,T98,T204
111CoveredT95,T96,T150

Branch Coverage for Module : i2c_reg_top
Line No.TotalCoveredPercent
Branches 38 38 100.00
TERNARY 3424 2 2 100.00
IF 68 3 3 100.00
CASE 3730 33 33 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv' or '../src/lowrisc_ip_i2c_0.1/rtl/i2c_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 3424 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T174,T175,T176
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 3730 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : i2c_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 432500050 55443972 0 0
reAfterRv 432500050 55443804 0 0
rePulse 432500050 54501724 0 0
wePulse 432500050 942080 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 432500050 55443972 0 0
T1 63197 31108 0 0
T2 16078 7216 0 0
T3 271103 38666 0 0
T4 192761 264080 0 0
T5 99323 1007 0 0
T6 64596 29815 0 0
T7 496079 443 0 0
T8 511332 4366 0 0
T9 646969 772 0 0
T10 177758 17186 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 432500050 55443804 0 0
T1 63197 31108 0 0
T2 16078 7216 0 0
T3 271103 38666 0 0
T4 192761 264080 0 0
T5 99323 1007 0 0
T6 64596 29815 0 0
T7 496079 443 0 0
T8 511332 4366 0 0
T9 646969 772 0 0
T10 177758 17186 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 432500050 54501724 0 0
T1 63197 30538 0 0
T2 16078 7038 0 0
T3 271103 38034 0 0
T4 192761 263781 0 0
T5 99323 722 0 0
T6 64596 29190 0 0
T7 496079 384 0 0
T8 511332 1424 0 0
T9 646969 701 0 0
T10 177758 16330 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 432500050 942080 0 0
T1 63197 570 0 0
T2 16078 178 0 0
T3 271103 632 0 0
T4 192761 299 0 0
T5 99323 285 0 0
T6 64596 625 0 0
T7 496079 59 0 0
T8 511332 2942 0 0
T9 646969 71 0 0
T10 177758 856 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%