Unified Coverage Report :: Module :: i2c_csr_assert_fpv

Module : i2c_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_i2c_csr_assert_0/i2c_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i2c_csr_assert	93.75						93.75

---

Module Instance : tb.dut.i2c_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75						93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.72	100.00	100.00	94.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : i2c_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	432500050	0	0	0
ctrl_rd_A	432500050	1573	0	0
host_fifo_config_rd_A	432500050	4601	0	0
host_nack_handler_timeout_rd_A	432500050	1131	0	0
host_timeout_ctrl_rd_A	432500050	817	0	0
intr_enable_rd_A	432500050	3429	0	0
ovrd_rd_A	432500050	1636	0	0
target_fifo_config_rd_A	432500050	1043	0	0
target_id_rd_A	432500050	1228	0	0
target_timeout_ctrl_rd_A	432500050	1043	0	0
timeout_ctrl_rd_A	432500050	1254	0	0
timing0_rd_A	432500050	992	0	0
timing1_rd_A	432500050	1031	0	0
timing2_rd_A	432500050	1044	0	0
timing3_rd_A	432500050	1009	0	0
timing4_rd_A	432500050	925	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1573	0	0
T95	2402	27	0	0
T96	8031	103	0	0
T97	10671	21	0	0
T98	13264	149	0	0
T99	15745	44	0	0
T100	2405	53	0	0
T101	6105	64	0	0
T102	5598	49	0	0
T103	31577	178	0	0
T104	2197	7	0	0

host_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	4601	0	0
T19	22956	0	0	0
T51	0	207	0	0
T56	0	83	0	0
T58	80610	0	0	0
T89	510610	0	0	0
T105	442768	122	0	0
T106	0	77	0	0
T107	0	179	0	0
T108	0	130	0	0
T109	0	84	0	0
T110	0	210	0	0
T111	0	52	0	0
T112	0	69	0	0
T113	94862	0	0	0
T114	78231	0	0	0
T115	103107	0	0	0
T116	112680	0	0	0
T117	101474	0	0	0
T118	211249	0	0	0

host_nack_handler_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1131	0	0
T95	2402	14	0	0
T96	8031	67	0	0
T97	10671	45	0	0
T98	13264	39	0	0
T99	15745	43	0	0
T100	2405	6	0	0
T101	6105	46	0	0
T102	5598	28	0	0
T103	31577	273	0	0
T104	2197	13	0	0

host_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	817	0	0
T95	2402	4	0	0
T96	8031	22	0	0
T97	10671	30	0	0
T98	13264	23	0	0
T99	15745	18	0	0
T100	2405	13	0	0
T101	6105	54	0	0
T102	5598	26	0	0
T103	31577	221	0	0
T104	2197	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	3429	0	0
T56	854797	7	0	0
T95	0	9	0	0
T96	0	393	0	0
T119	0	26	0	0
T120	0	22	0	0
T121	0	17	0	0
T122	0	32	0	0
T123	0	9	0	0
T124	0	68	0	0
T125	0	18	0	0
T126	76450	0	0	0
T127	78452	0	0	0
T128	128783	0	0	0
T129	19898	0	0	0
T130	44749	0	0	0
T131	213088	0	0	0
T132	8405	0	0	0
T133	54289	0	0	0
T134	133601	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1636	0	0
T23	35455	0	0	0
T36	217549	0	0	0
T59	197967	0	0	0
T79	1040	23	0	0
T80	0	52	0	0
T135	0	47	0	0
T136	0	30	0	0
T137	0	51	0	0
T138	0	69	0	0
T139	0	37	0	0
T140	0	34	0	0
T141	0	28	0	0
T142	0	35	0	0
T143	260103	0	0	0
T144	172309	0	0	0
T145	11970	0	0	0
T146	989219	0	0	0
T147	39526	0	0	0
T148	487799	0	0	0

target_fifo_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1043	0	0
T95	2402	6	0	0
T96	8031	41	0	0
T97	10671	20	0	0
T98	13264	38	0	0
T99	15745	60	0	0
T100	2405	15	0	0
T101	6105	81	0	0
T102	5598	9	0	0
T103	31577	220	0	0
T104	2197	12	0	0

target_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1228	0	0
T95	2402	14	0	0
T96	8031	103	0	0
T97	10671	14	0	0
T98	13264	73	0	0
T99	15745	55	0	0
T100	2405	26	0	0
T101	6105	54	0	0
T102	5598	20	0	0
T103	31577	192	0	0
T104	2197	15	0	0

target_timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1043	0	0
T95	2402	14	0	0
T96	8031	52	0	0
T97	10671	26	0	0
T98	13264	52	0	0
T99	15745	21	0	0
T100	2405	5	0	0
T101	6105	63	0	0
T102	5598	34	0	0
T103	31577	224	0	0
T104	2197	16	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1254	0	0
T95	2402	17	0	0
T96	8031	128	0	0
T97	10671	7	0	0
T98	13264	90	0	0
T99	15745	55	0	0
T100	2405	24	0	0
T101	6105	65	0	0
T102	5598	9	0	0
T103	31577	196	0	0
T104	2197	11	0	0

timing0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	992	0	0
T95	2402	7	0	0
T96	8031	57	0	0
T97	10671	40	0	0
T98	13264	71	0	0
T99	15745	61	0	0
T100	2405	10	0	0
T101	6105	51	0	0
T102	5598	15	0	0
T103	31577	216	0	0
T104	2197	12	0	0

timing1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1031	0	0
T95	2402	12	0	0
T96	8031	34	0	0
T97	10671	14	0	0
T98	13264	50	0	0
T99	15745	64	0	0
T100	2405	10	0	0
T101	6105	71	0	0
T102	5598	5	0	0
T103	31577	228	0	0
T104	2197	4	0	0

timing2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1044	0	0
T95	2402	13	0	0
T96	8031	62	0	0
T97	10671	21	0	0
T98	13264	54	0	0
T99	15745	44	0	0
T100	2405	15	0	0
T101	6105	55	0	0
T103	31577	202	0	0
T104	2197	6	0	0
T149	8553	5	0	0

timing3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	1009	0	0
T95	2402	7	0	0
T96	8031	66	0	0
T97	10671	6	0	0
T98	13264	69	0	0
T99	15745	45	0	0
T100	2405	10	0	0
T101	6105	69	0	0
T102	5598	24	0	0
T103	31577	216	0	0
T104	2197	15	0	0

timing4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432500050	925	0	0
T95	2402	16	0	0
T96	8031	50	0	0
T97	10671	6	0	0
T98	13264	39	0	0
T99	15745	57	0	0
T100	2405	3	0	0
T101	6105	51	0	0
T102	5598	16	0	0
T103	31577	193	0	0
T104	2197	14	0	0