Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	859830	1			T1	1		T2	3		T3	3
all_values[1]	859830	1			T1	1		T2	3		T3	3
all_values[2]	859830	1			T1	1		T2	3		T3	3
all_values[3]	859830	1			T1	1		T2	3		T3	3
all_values[4]	859830	1			T1	1		T2	3		T3	3
all_values[5]	859830	1			T1	1		T2	3		T3	3
all_values[6]	859830	1			T1	1		T2	3		T3	3
all_values[7]	859830	1			T1	1		T2	3		T3	3
all_values[8]	859830	1			T1	1		T2	3		T3	3
all_values[9]	859830	1			T1	1		T2	3		T3	3
all_values[10]	859830	1			T1	1		T2	3		T3	3
all_values[11]	859830	1			T1	1		T2	3		T3	3
all_values[12]	859830	1			T1	1		T2	3		T3	3
all_values[13]	859830	1			T1	1		T2	3		T3	3
all_values[14]	859830	1			T1	1		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10561409

1

T1

15

T2

38

T3

39

auto[1]

2336041

1

T2

7

T3

6

T4

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11766253

1

T1

15

T2

45

T3

45

auto[1]

1131197

1

T39

83573

T37

190758

T50

128693

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83487	1			T1	1		T3	1		T10	40
all_values[0]	auto[0]	auto[1]	6975	1			T39	187		T37	1193		T50	233
all_values[0]	auto[1]	auto[0]	701845	1			T2	3		T3	2		T4	3
all_values[0]	auto[1]	auto[1]	67523	1			T39	5781		T37	16148		T50	8346
all_values[1]	auto[0]	auto[0]	785140	1			T1	1		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	74238	1			T39	5967		T37	17335		T50	8576
all_values[1]	auto[1]	auto[0]	203	1			T10	3		T33	11		T34	2
all_values[1]	auto[1]	auto[1]	249	1			T39	1		T37	6		T50	5
all_values[2]	auto[0]	auto[0]	776739	1			T1	1		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	82765	1			T39	5967		T37	17336		T50	8573
all_values[2]	auto[1]	auto[0]	112	1			T5	1		T166	4		T92	1
all_values[2]	auto[1]	auto[1]	214	1			T39	3		T37	4		T50	7
all_values[3]	auto[0]	auto[0]	775069	1			T1	1		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	84505	1			T39	5966		T37	17337		T50	8573
all_values[3]	auto[1]	auto[1]	256	1			T39	4		T37	3		T50	7
all_values[4]	auto[0]	auto[0]	773820	1			T1	1		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	85794	1			T39	5969		T37	17338		T50	8574
all_values[4]	auto[1]	auto[0]	12	1			T230	1		T231	1		T232	1
all_values[4]	auto[1]	auto[1]	204	1			T39	1		T37	2		T50	6
all_values[5]	auto[0]	auto[0]	808577	1			T1	1		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	51033	1			T39	5970		T37	2		T50	8572
all_values[5]	auto[1]	auto[1]	220	1			T37	3		T50	7		T51	4
all_values[6]	auto[0]	auto[0]	773619	1			T1	1		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	85974	1			T39	5968		T37	17339		T50	8580
all_values[6]	auto[1]	auto[1]	237	1			T39	2		T37	2		T50	1
all_values[7]	auto[0]	auto[0]	757712	1			T1	1		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	72761	1			T39	5837		T37	17113		T50	8490
all_values[7]	auto[1]	auto[0]	26555	1			T3	1		T10	22		T16	1
all_values[7]	auto[1]	auto[1]	2802	1			T39	133		T37	228		T50	90
all_values[8]	auto[0]	auto[0]	778669	1			T1	1		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	80952	1			T39	5970		T37	17337		T50	8574
all_values[8]	auto[1]	auto[1]	209	1			T37	2		T50	6		T78	2
all_values[9]	auto[0]	auto[0]	169172	1			T1	1		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	12850	1			T39	493		T37	4		T50	157
all_values[9]	auto[1]	auto[0]	621799	1			T2	1		T3	1		T4	1
all_values[9]	auto[1]	auto[1]	56009	1			T39	5477		T37	1		T50	8424
all_values[10]	auto[0]	auto[0]	790988	1			T1	1		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	68661	1			T39	5968		T50	8577		T51	5037
all_values[10]	auto[1]	auto[1]	181	1			T39	2		T50	4		T51	1
all_values[11]	auto[0]	auto[0]	2668	1			T1	1		T3	1		T10	3
all_values[11]	auto[0]	auto[1]	475	1			T39	26		T50	21		T51	9
all_values[11]	auto[1]	auto[0]	775415	1			T2	3		T3	2		T4	3
all_values[11]	auto[1]	auto[1]	81272	1			T39	5942		T37	17340		T50	8560
all_values[12]	auto[0]	auto[0]	780712	1			T1	1		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	78889	1			T37	17337		T50	8576		T51	5036
all_values[12]	auto[1]	auto[0]	22	1			T233	2		T234	1		T235	1
all_values[12]	auto[1]	auto[1]	207	1			T37	4		T50	5		T51	1
all_values[13]	auto[0]	auto[0]	805245	1			T1	1		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	54328	1			T39	5968		T37	2		T50	8575
all_values[13]	auto[1]	auto[1]	257	1			T39	1		T37	3		T50	5
all_values[14]	auto[0]	auto[0]	778673	1			T1	1		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	80919	1			T39	5967		T37	17335		T50	8564
all_values[14]	auto[1]	auto[1]	238	1			T39	3		T37	4		T50	5