Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	859830	1			T1	1		T2	3		T3	3
all_pins[1]	859830	1			T1	1		T2	3		T3	3
all_pins[2]	859830	1			T1	1		T2	3		T3	3
all_pins[3]	859830	1			T1	1		T2	3		T3	3
all_pins[4]	859830	1			T1	1		T2	3		T3	3
all_pins[5]	859830	1			T1	1		T2	3		T3	3
all_pins[6]	859830	1			T1	1		T2	3		T3	3
all_pins[7]	859830	1			T1	1		T2	3		T3	3
all_pins[8]	859830	1			T1	1		T2	3		T3	3
all_pins[9]	859830	1			T1	1		T2	3		T3	3
all_pins[10]	859830	1			T1	1		T2	3		T3	3
all_pins[11]	859830	1			T1	1		T2	3		T3	3
all_pins[12]	859830	1			T1	1		T2	3		T3	3
all_pins[13]	859830	1			T1	1		T2	3		T3	3
all_pins[14]	859830	1			T1	1		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10566262	1			T1	15		T2	38		T3	39
values[0x1]	2331188	1			T2	7		T3	6		T4	7
transitions[0x0=>0x1]	2330460	1			T2	7		T3	6		T4	7
transitions[0x1=>0x0]	2329346	1			T2	6		T3	5		T4	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93542	1			T1	1		T3	1		T10	39
all_pins[0]	values[0x1]	766288	1			T2	3		T3	2		T4	3
all_pins[0]	transitions[0x0=>0x1]	765964	1			T2	3		T3	2		T4	3
all_pins[0]	transitions[0x1=>0x0]	71	1			T37	1		T211	3		T106	1
all_pins[1]	values[0x0]	859435	1			T1	1		T2	3		T3	3
all_pins[1]	values[0x1]	395	1			T10	3		T33	13		T34	2
all_pins[1]	transitions[0x0=>0x1]	375	1			T10	3		T33	13		T34	2
all_pins[1]	transitions[0x1=>0x0]	191	1			T5	1		T166	4		T39	3
all_pins[2]	values[0x0]	859619	1			T1	1		T2	3		T3	3
all_pins[2]	values[0x1]	211	1			T5	1		T166	4		T39	3
all_pins[2]	transitions[0x0=>0x1]	186	1			T5	1		T166	4		T92	1
all_pins[2]	transitions[0x1=>0x0]	86	1			T39	1		T37	2		T50	1
all_pins[3]	values[0x0]	859719	1			T1	1		T2	3		T3	3
all_pins[3]	values[0x1]	111	1			T39	4		T37	2		T50	3
all_pins[3]	transitions[0x0=>0x1]	90	1			T39	3		T37	2		T50	2
all_pins[3]	transitions[0x1=>0x0]	97	1			T50	3		T51	1		T78	1
all_pins[4]	values[0x0]	859712	1			T1	1		T2	3		T3	3
all_pins[4]	values[0x1]	118	1			T39	1		T50	4		T51	1
all_pins[4]	transitions[0x0=>0x1]	97	1			T39	1		T50	4		T51	1
all_pins[4]	transitions[0x1=>0x0]	90	1			T50	2		T51	1		T243	2
all_pins[5]	values[0x0]	859719	1			T1	1		T2	3		T3	3
all_pins[5]	values[0x1]	111	1			T50	2		T51	1		T243	3
all_pins[5]	transitions[0x0=>0x1]	83	1			T50	2		T51	1		T106	2
all_pins[5]	transitions[0x1=>0x0]	102	1			T39	2		T51	1		T78	1
all_pins[6]	values[0x0]	859700	1			T1	1		T2	3		T3	3
all_pins[6]	values[0x1]	130	1			T39	2		T51	1		T78	1
all_pins[6]	transitions[0x0=>0x1]	106	1			T39	2		T51	1		T78	1
all_pins[6]	transitions[0x1=>0x0]	32230	1			T3	1		T10	23		T16	1
all_pins[7]	values[0x0]	827576	1			T1	1		T2	3		T3	2
all_pins[7]	values[0x1]	32254	1			T3	1		T10	23		T16	1
all_pins[7]	transitions[0x0=>0x1]	32235	1			T3	1		T10	23		T16	1
all_pins[7]	transitions[0x1=>0x0]	79	1			T50	4		T78	2		T45	1
all_pins[8]	values[0x0]	859732	1			T1	1		T2	3		T3	3
all_pins[8]	values[0x1]	98	1			T37	2		T50	5		T78	2
all_pins[8]	transitions[0x0=>0x1]	71	1			T37	2		T50	4		T78	2
all_pins[8]	transitions[0x1=>0x0]	677738	1			T2	1		T3	1		T4	1
all_pins[9]	values[0x0]	182065	1			T1	1		T2	2		T3	2
all_pins[9]	values[0x1]	677765	1			T2	1		T3	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	677743	1			T2	1		T3	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	79	1			T39	2		T78	2		T211	3
all_pins[10]	values[0x0]	859729	1			T1	1		T2	3		T3	3
all_pins[10]	values[0x1]	101	1			T39	2		T50	1		T51	1
all_pins[10]	transitions[0x0=>0x1]	72	1			T39	2		T50	1		T51	1
all_pins[10]	transitions[0x1=>0x0]	853180	1			T2	3		T3	2		T4	3
all_pins[11]	values[0x0]	6621	1			T1	1		T3	1		T10	3
all_pins[11]	values[0x1]	853209	1			T2	3		T3	2		T4	3
all_pins[11]	transitions[0x0=>0x1]	853147	1			T2	3		T3	2		T4	3
all_pins[11]	transitions[0x1=>0x0]	78	1			T37	2		T50	3		T211	2
all_pins[12]	values[0x0]	859690	1			T1	1		T2	3		T3	3
all_pins[12]	values[0x1]	140	1			T37	2		T50	3		T233	2
all_pins[12]	transitions[0x0=>0x1]	109	1			T37	2		T50	2		T233	2
all_pins[12]	transitions[0x1=>0x0]	110	1			T39	1		T37	2		T50	3
all_pins[13]	values[0x0]	859689	1			T1	1		T2	3		T3	3
all_pins[13]	values[0x1]	141	1			T39	1		T37	2		T50	4
all_pins[13]	transitions[0x0=>0x1]	114	1			T39	1		T37	2		T50	4
all_pins[13]	transitions[0x1=>0x0]	89	1			T39	3		T50	1		T45	4
all_pins[14]	values[0x0]	859714	1			T1	1		T2	3		T3	3
all_pins[14]	values[0x1]	116	1			T39	3		T50	1		T45	4
all_pins[14]	transitions[0x0=>0x1]	68	1			T39	3		T50	1		T45	2
all_pins[14]	transitions[0x1=>0x0]	765126	1			T2	2		T3	1		T4	2