Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	512	1			T39	4		T37	8		T50	11
all_values[1]	512	1			T39	4		T37	8		T50	11
all_values[2]	512	1			T39	4		T37	8		T50	11
all_values[3]	512	1			T39	4		T37	8		T50	11
all_values[4]	512	1			T39	4		T37	8		T50	11
all_values[5]	512	1			T39	4		T37	8		T50	11
all_values[6]	512	1			T39	4		T37	8		T50	11
all_values[7]	512	1			T39	4		T37	8		T50	11
all_values[8]	512	1			T39	4		T37	8		T50	11
all_values[9]	512	1			T39	4		T37	8		T50	11
all_values[10]	512	1			T39	4		T37	8		T50	11
all_values[11]	512	1			T39	4		T37	8		T50	11
all_values[12]	512	1			T39	4		T37	8		T50	11
all_values[13]	512	1			T39	4		T37	8		T50	11
all_values[14]	512	1			T39	4		T37	8		T50	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4008

1

T39

17

T37

50

T50

79

auto[1]

3672

1

T39

43

T37

70

T50

86

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1215

1

T39

11

T37

31

T50

14

auto[1]

6465

1

T39

49

T37

89

T50

151

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4620

1

T39

37

T37

79

T50

92

auto[1]

3060

1

T39

23

T37

41

T50

73

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	54	1			T39	1		T78	4		T243	5
all_values[0]	auto[0]	auto[0]	auto[1]	98	1			T39	1		T37	2		T50	2
all_values[0]	auto[0]	auto[1]	auto[0]	23	1			T39	1		T50	2		T243	2
all_values[0]	auto[0]	auto[1]	auto[1]	124	1			T50	1		T51	1		T45	1
all_values[0]	auto[1]	auto[0]	auto[1]	110	1			T39	1		T37	2		T50	2
all_values[0]	auto[1]	auto[1]	auto[1]	103	1			T37	4		T50	4		T51	1
all_values[1]	auto[0]	auto[0]	auto[0]	55	1			T45	2		T106	1		T125	1
all_values[1]	auto[0]	auto[0]	auto[1]	127	1			T39	1		T37	1		T50	3
all_values[1]	auto[0]	auto[1]	auto[0]	37	1			T39	2		T78	4		T243	2
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T37	3		T50	3		T243	2
all_values[1]	auto[1]	auto[0]	auto[1]	117	1			T37	2		T50	4		T51	1
all_values[1]	auto[1]	auto[1]	auto[1]	88	1			T39	1		T37	2		T50	1
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T50	1		T106	1		T244	1
all_values[2]	auto[0]	auto[0]	auto[1]	110	1			T37	3		T50	2		T78	1
all_values[2]	auto[0]	auto[1]	auto[0]	35	1			T37	1		T51	1		T45	1
all_values[2]	auto[0]	auto[1]	auto[1]	114	1			T39	1		T50	1		T51	2
all_values[2]	auto[1]	auto[0]	auto[1]	122	1			T37	1		T50	2		T78	1
all_values[2]	auto[1]	auto[1]	auto[1]	92	1			T39	3		T37	3		T50	5
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T45	1		T106	3		T125	1
all_values[3]	auto[0]	auto[0]	auto[1]	123	1			T37	1		T50	1		T51	2
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T37	1		T50	1		T45	3
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T39	1		T37	3		T50	2
all_values[3]	auto[1]	auto[0]	auto[1]	137	1			T37	2		T50	5		T78	2
all_values[3]	auto[1]	auto[1]	auto[1]	88	1			T39	3		T37	1		T50	2
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T78	1		T211	2		T106	1
all_values[4]	auto[0]	auto[0]	auto[1]	132	1			T39	1		T37	3		T50	2
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T37	1		T50	1		T51	1
all_values[4]	auto[0]	auto[1]	auto[1]	115	1			T39	2		T37	2		T50	2
all_values[4]	auto[1]	auto[0]	auto[1]	110	1			T37	1		T50	3		T51	2
all_values[4]	auto[1]	auto[1]	auto[1]	94	1			T39	1		T37	1		T50	3
all_values[5]	auto[0]	auto[0]	auto[0]	51	1			T78	4		T45	3		T115	2
all_values[5]	auto[0]	auto[0]	auto[1]	120	1			T37	1		T50	3		T51	2
all_values[5]	auto[0]	auto[1]	auto[0]	46	1			T37	5		T50	2		T45	1
all_values[5]	auto[0]	auto[1]	auto[1]	111	1			T39	3		T50	3		T51	1
all_values[5]	auto[1]	auto[0]	auto[1]	89	1			T37	2		T211	1		T243	1
all_values[5]	auto[1]	auto[1]	auto[1]	95	1			T39	1		T50	3		T51	1
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T52	1		T117	1		T118	1
all_values[6]	auto[0]	auto[0]	auto[1]	111	1			T37	3		T50	3		T51	1
all_values[6]	auto[0]	auto[1]	auto[0]	37	1			T51	1		T125	2		T245	2
all_values[6]	auto[0]	auto[1]	auto[1]	129	1			T39	2		T37	2		T50	6
all_values[6]	auto[1]	auto[0]	auto[1]	111	1			T37	1		T50	1		T45	1
all_values[6]	auto[1]	auto[1]	auto[1]	96	1			T39	2		T37	2		T50	1
all_values[7]	auto[0]	auto[0]	auto[0]	51	1			T50	1		T106	6		T125	1
all_values[7]	auto[0]	auto[0]	auto[1]	111	1			T39	3		T37	1		T50	3
all_values[7]	auto[0]	auto[1]	auto[0]	36	1			T51	4		T78	2		T106	2
all_values[7]	auto[0]	auto[1]	auto[1]	108	1			T37	4		T50	2		T45	1
all_values[7]	auto[1]	auto[0]	auto[1]	105	1			T50	2		T78	1		T45	1
all_values[7]	auto[1]	auto[1]	auto[1]	101	1			T39	1		T37	3		T50	3
all_values[8]	auto[0]	auto[0]	auto[0]	46	1			T50	1		T51	1		T245	1
all_values[8]	auto[0]	auto[0]	auto[1]	135	1			T39	3		T37	1		T50	3
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T37	2		T51	3		T211	1
all_values[8]	auto[0]	auto[1]	auto[1]	115	1			T37	4		T50	2		T78	1
all_values[8]	auto[1]	auto[0]	auto[1]	99	1			T50	2		T45	2		T211	1
all_values[8]	auto[1]	auto[1]	auto[1]	89	1			T39	1		T37	1		T50	3
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T37	1		T243	1		T125	1
all_values[9]	auto[0]	auto[0]	auto[1]	103	1			T37	1		T50	2		T51	1
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T37	4		T106	1		T114	2
all_values[9]	auto[0]	auto[1]	auto[1]	123	1			T39	1		T50	2		T51	1
all_values[9]	auto[1]	auto[0]	auto[1]	102	1			T39	2		T50	3		T78	1
all_values[9]	auto[1]	auto[1]	auto[1]	100	1			T39	1		T37	2		T50	4
all_values[10]	auto[0]	auto[0]	auto[0]	53	1			T37	5		T243	2		T245	1
all_values[10]	auto[0]	auto[0]	auto[1]	101	1			T50	3		T211	2		T243	2
all_values[10]	auto[0]	auto[1]	auto[0]	47	1			T37	3		T51	1		T243	1
all_values[10]	auto[0]	auto[1]	auto[1]	130	1			T39	2		T50	4		T51	2
all_values[10]	auto[1]	auto[0]	auto[1]	99	1			T50	2		T51	1		T45	2
all_values[10]	auto[1]	auto[1]	auto[1]	82	1			T39	2		T50	2		T78	2
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T39	1		T45	1		T125	2
all_values[11]	auto[0]	auto[0]	auto[1]	111	1			T37	3		T50	4		T51	1
all_values[11]	auto[0]	auto[1]	auto[0]	34	1			T39	1		T37	1		T51	1
all_values[11]	auto[0]	auto[1]	auto[1]	120	1			T39	1		T37	1		T50	3
all_values[11]	auto[1]	auto[0]	auto[1]	113	1			T39	1		T37	2		T50	2
all_values[11]	auto[1]	auto[1]	auto[1]	89	1			T37	1		T50	2		T51	1
all_values[12]	auto[0]	auto[0]	auto[0]	61	1			T39	2		T51	1		T125	4
all_values[12]	auto[0]	auto[0]	auto[1]	89	1			T37	1		T50	1		T51	1
all_values[12]	auto[0]	auto[1]	auto[0]	33	1			T39	2		T51	1		T211	1
all_values[12]	auto[0]	auto[1]	auto[1]	122	1			T37	3		T50	5		T211	3
all_values[12]	auto[1]	auto[0]	auto[1]	94	1			T37	1		T50	4		T51	1
all_values[12]	auto[1]	auto[1]	auto[1]	113	1			T37	3		T50	1		T45	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T37	2		T50	1		T125	1
all_values[13]	auto[0]	auto[0]	auto[1]	94	1			T50	4		T51	1		T211	1
all_values[13]	auto[0]	auto[1]	auto[0]	47	1			T39	1		T37	3		T51	1
all_values[13]	auto[0]	auto[1]	auto[1]	121	1			T39	2		T37	1		T50	3
all_values[13]	auto[1]	auto[0]	auto[1]	107	1			T37	2		T50	1		T51	1
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T39	1		T50	2		T51	1
all_values[14]	auto[0]	auto[0]	auto[0]	52	1			T37	1		T50	3		T51	2
all_values[14]	auto[0]	auto[0]	auto[1]	100	1			T37	2		T50	1		T78	2
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T37	1		T50	1		T51	2
all_values[14]	auto[0]	auto[1]	auto[1]	118	1			T39	2		T37	2		T50	2
all_values[14]	auto[1]	auto[0]	auto[1]	125	1			T37	2		T50	2		T211	1
all_values[14]	auto[1]	auto[1]	auto[1]	89	1			T39	2		T50	2		T78	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal