Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	880897	1			T1	204		T2	37		T3	3
all_values[1]	880897	1			T1	204		T2	37		T3	3
all_values[2]	880897	1			T1	204		T2	37		T3	3
all_values[3]	880897	1			T1	204		T2	37		T3	3
all_values[4]	880897	1			T1	204		T2	37		T3	3
all_values[5]	880897	1			T1	204		T2	37		T3	3
all_values[6]	880897	1			T1	204		T2	37		T3	3
all_values[7]	880897	1			T1	204		T2	37		T3	3
all_values[8]	880897	1			T1	204		T2	37		T3	3
all_values[9]	880897	1			T1	204		T2	37		T3	3
all_values[10]	880897	1			T1	204		T2	37		T3	3
all_values[11]	880897	1			T1	204		T2	37		T3	3
all_values[12]	880897	1			T1	204		T2	37		T3	3
all_values[13]	880897	1			T1	204		T2	37		T3	3
all_values[14]	880897	1			T1	204		T2	37		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10786595

1

T1

2646

T2

490

T3

38

auto[1]

2426860

1

T1

414

T2

65

T3

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10428679

1

T1

3060

T2

213

T3

45

auto[1]

2784776

1

T2

342

T87

55

T103

125499

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	68735	1			T1	19		T2	24		T7	237
all_values[0]	auto[0]	auto[1]	14837	1			T103	900		T203	4		T204	410
all_values[0]	auto[1]	auto[0]	634169	1			T1	185		T2	13		T3	3
all_values[0]	auto[1]	auto[1]	163156	1			T87	5		T103	8400		T203	15
all_values[1]	auto[0]	auto[0]	691534	1			T1	204		T2	13		T3	3
all_values[1]	auto[0]	auto[1]	188940	1			T2	23		T87	4		T103	9297
all_values[1]	auto[1]	auto[0]	209	1			T28	2		T216	3		T217	2
all_values[1]	auto[1]	auto[1]	214	1			T2	1		T87	1		T103	3
all_values[2]	auto[0]	auto[0]	691612	1			T1	204		T2	12		T3	3
all_values[2]	auto[0]	auto[1]	188985	1			T2	23		T87	2		T103	9294
all_values[2]	auto[1]	auto[0]	103	1			T218	3		T219	1		T220	2
all_values[2]	auto[1]	auto[1]	197	1			T2	2		T87	3		T103	5
all_values[3]	auto[0]	auto[0]	691750	1			T1	204		T2	12		T3	3
all_values[3]	auto[0]	auto[1]	188931	1			T2	24		T103	9295		T203	17
all_values[3]	auto[1]	auto[1]	216	1			T2	1		T103	4		T203	3
all_values[4]	auto[0]	auto[0]	696188	1			T1	204		T2	13		T3	3
all_values[4]	auto[0]	auto[1]	184501	1			T2	22		T87	2		T103	9296
all_values[4]	auto[1]	auto[0]	17	1			T8	2		T221	1		T222	3
all_values[4]	auto[1]	auto[1]	191	1			T2	2		T87	2		T103	3
all_values[5]	auto[0]	auto[0]	691723	1			T1	204		T2	14		T3	3
all_values[5]	auto[0]	auto[1]	188958	1			T2	21		T87	5		T103	9292
all_values[5]	auto[1]	auto[1]	216	1			T2	2		T103	7		T203	6
all_values[6]	auto[0]	auto[0]	692318	1			T1	204		T2	13		T3	3
all_values[6]	auto[0]	auto[1]	188360	1			T2	21		T87	4		T103	9293
all_values[6]	auto[1]	auto[1]	219	1			T2	3		T87	1		T103	6
all_values[7]	auto[0]	auto[0]	669282	1			T1	188		T2	11		T3	3
all_values[7]	auto[0]	auto[1]	184244	1			T2	19		T103	8928		T203	10
all_values[7]	auto[1]	auto[0]	22483	1			T1	16		T2	1		T8	22
all_values[7]	auto[1]	auto[1]	4888	1			T2	6		T103	372		T203	8
all_values[8]	auto[0]	auto[0]	696390	1			T1	204		T2	13		T3	3
all_values[8]	auto[0]	auto[1]	184279	1			T2	21		T87	4		T103	4634
all_values[8]	auto[1]	auto[1]	228	1			T2	3		T103	3		T203	5
all_values[9]	auto[0]	auto[0]	135212	1			T1	190		T2	11		T3	2
all_values[9]	auto[0]	auto[1]	23973	1			T2	17		T87	4		T103	303
all_values[9]	auto[1]	auto[0]	557089	1			T1	14		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	164623	1			T2	8		T87	1		T103	8997
all_values[10]	auto[0]	auto[0]	698125	1			T1	204		T2	12		T3	3
all_values[10]	auto[0]	auto[1]	182600	1			T2	24		T87	3		T103	9292
all_values[10]	auto[1]	auto[1]	172	1			T2	1		T87	1		T103	6
all_values[11]	auto[0]	auto[0]	2499	1			T1	5		T2	10		T7	2
all_values[11]	auto[0]	auto[1]	532	1			T2	13		T103	7		T203	7
all_values[11]	auto[1]	auto[0]	693885	1			T1	199		T2	3		T3	3
all_values[11]	auto[1]	auto[1]	183981	1			T2	11		T103	4630		T203	13
all_values[12]	auto[0]	auto[0]	696216	1			T1	204		T2	13		T3	3
all_values[12]	auto[0]	auto[1]	184479	1			T2	22		T87	2		T103	9296
all_values[12]	auto[1]	auto[0]	21	1			T220	1		T223	3		T224	1
all_values[12]	auto[1]	auto[1]	181	1			T2	2		T87	2		T103	3
all_values[13]	auto[0]	auto[0]	707366	1			T1	204		T2	12		T3	3
all_values[13]	auto[0]	auto[1]	173336	1			T2	22		T87	4		T103	4630
all_values[13]	auto[1]	auto[1]	195	1			T2	3		T87	1		T103	3
all_values[14]	auto[0]	auto[0]	691753	1			T1	204		T2	12		T3	3
all_values[14]	auto[0]	auto[1]	188937	1			T2	23		T87	4		T103	9295
all_values[14]	auto[1]	auto[1]	207	1			T2	2		T103	5		T203	4