Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	880897	1			T1	204		T2	37		T3	3
all_pins[1]	880897	1			T1	204		T2	37		T3	3
all_pins[2]	880897	1			T1	204		T2	37		T3	3
all_pins[3]	880897	1			T1	204		T2	37		T3	3
all_pins[4]	880897	1			T1	204		T2	37		T3	3
all_pins[5]	880897	1			T1	204		T2	37		T3	3
all_pins[6]	880897	1			T1	204		T2	37		T3	3
all_pins[7]	880897	1			T1	204		T2	37		T3	3
all_pins[8]	880897	1			T1	204		T2	37		T3	3
all_pins[9]	880897	1			T1	204		T2	37		T3	3
all_pins[10]	880897	1			T1	204		T2	37		T3	3
all_pins[11]	880897	1			T1	204		T2	37		T3	3
all_pins[12]	880897	1			T1	204		T2	37		T3	3
all_pins[13]	880897	1			T1	204		T2	37		T3	3
all_pins[14]	880897	1			T1	204		T2	37		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10791921	1			T1	2644		T2	501		T3	38
values[0x1]	2421534	1			T1	416		T2	54		T3	7
transitions[0x0=>0x1]	2420856	1			T1	416		T2	48		T3	7
transitions[0x1=>0x0]	2419739	1			T1	415		T2	47		T3	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87046	1			T1	19		T2	24		T7	237
all_pins[0]	values[0x1]	793851	1			T1	185		T2	13		T3	3
all_pins[0]	transitions[0x0=>0x1]	793541	1			T1	185		T2	13		T3	3
all_pins[0]	transitions[0x1=>0x0]	70	1			T87	1		T103	1		T222	2
all_pins[1]	values[0x0]	880517	1			T1	204		T2	37		T3	3
all_pins[1]	values[0x1]	380	1			T28	2		T87	1		T103	3
all_pins[1]	transitions[0x0=>0x1]	357	1			T28	2		T103	3		T216	4
all_pins[1]	transitions[0x1=>0x0]	189	1			T2	2		T87	1		T103	4
all_pins[2]	values[0x0]	880685	1			T1	204		T2	35		T3	3
all_pins[2]	values[0x1]	212	1			T2	2		T87	2		T103	4
all_pins[2]	transitions[0x0=>0x1]	186	1			T2	1		T87	2		T103	2
all_pins[2]	transitions[0x1=>0x0]	78	1			T103	1		T204	4		T140	3
all_pins[3]	values[0x0]	880793	1			T1	204		T2	36		T3	3
all_pins[3]	values[0x1]	104	1			T2	1		T103	3		T204	4
all_pins[3]	transitions[0x0=>0x1]	85	1			T2	1		T103	2		T204	4
all_pins[3]	transitions[0x1=>0x0]	102	1			T2	2		T8	2		T87	2
all_pins[4]	values[0x0]	880776	1			T1	204		T2	35		T3	3
all_pins[4]	values[0x1]	121	1			T2	2		T8	2		T87	2
all_pins[4]	transitions[0x0=>0x1]	103	1			T2	2		T8	2		T87	2
all_pins[4]	transitions[0x1=>0x0]	96	1			T103	2		T203	3		T204	6
all_pins[5]	values[0x0]	880783	1			T1	204		T2	37		T3	3
all_pins[5]	values[0x1]	114	1			T103	3		T203	4		T204	7
all_pins[5]	transitions[0x0=>0x1]	85	1			T103	3		T203	3		T204	4
all_pins[5]	transitions[0x1=>0x0]	88	1			T2	2		T87	1		T103	2
all_pins[6]	values[0x0]	880780	1			T1	204		T2	35		T3	3
all_pins[6]	values[0x1]	117	1			T2	2		T87	1		T103	2
all_pins[6]	transitions[0x0=>0x1]	87	1			T87	1		T103	1		T203	2
all_pins[6]	transitions[0x1=>0x0]	30312	1			T1	18		T2	5		T51	1
all_pins[7]	values[0x0]	850555	1			T1	186		T2	30		T3	3
all_pins[7]	values[0x1]	30342	1			T1	18		T2	7		T51	1
all_pins[7]	transitions[0x0=>0x1]	30318	1			T1	18		T2	5		T51	1
all_pins[7]	transitions[0x1=>0x0]	74	1			T103	2		T203	2		T204	1
all_pins[8]	values[0x0]	880799	1			T1	204		T2	35		T3	3
all_pins[8]	values[0x1]	98	1			T2	2		T103	2		T203	3
all_pins[8]	transitions[0x0=>0x1]	68	1			T2	2		T103	2		T203	3
all_pins[8]	transitions[0x1=>0x0]	721625	1			T1	14		T2	7		T3	1
all_pins[9]	values[0x0]	159242	1			T1	190		T2	30		T3	2
all_pins[9]	values[0x1]	721655	1			T1	14		T2	7		T3	1
all_pins[9]	transitions[0x0=>0x1]	721630	1			T1	14		T2	6		T3	1
all_pins[9]	transitions[0x1=>0x0]	67	1			T103	2		T203	3		T204	1
all_pins[10]	values[0x0]	880805	1			T1	204		T2	36		T3	3
all_pins[10]	values[0x1]	92	1			T2	1		T103	3		T203	3
all_pins[10]	transitions[0x0=>0x1]	73	1			T2	1		T103	3		T203	2
all_pins[10]	transitions[0x1=>0x0]	874127	1			T1	199		T2	14		T3	3
all_pins[11]	values[0x0]	6751	1			T1	5		T2	23		T7	2
all_pins[11]	values[0x1]	874146	1			T1	199		T2	14		T3	3
all_pins[11]	transitions[0x0=>0x1]	874101	1			T1	199		T2	14		T3	3
all_pins[11]	transitions[0x1=>0x0]	62	1			T103	2		T203	2		T204	2
all_pins[12]	values[0x0]	880790	1			T1	204		T2	37		T3	3
all_pins[12]	values[0x1]	107	1			T103	2		T203	4		T220	1
all_pins[12]	transitions[0x0=>0x1]	88	1			T103	1		T203	4		T220	1
all_pins[12]	transitions[0x1=>0x0]	82	1			T2	1		T103	2		T203	1
all_pins[13]	values[0x0]	880796	1			T1	204		T2	36		T3	3
all_pins[13]	values[0x1]	101	1			T2	1		T103	3		T203	1
all_pins[13]	transitions[0x0=>0x1]	74	1			T2	1		T103	2		T203	1
all_pins[13]	transitions[0x1=>0x0]	67	1			T2	2		T103	1		T203	1
all_pins[14]	values[0x0]	880803	1			T1	204		T2	35		T3	3
all_pins[14]	values[0x1]	94	1			T2	2		T103	2		T203	1
all_pins[14]	transitions[0x0=>0x1]	60	1			T2	2		T103	1		T203	1
all_pins[14]	transitions[0x1=>0x0]	792700	1			T1	184		T2	12		T3	2