Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	471	1			T2	4		T87	4		T103	11
all_values[1]	471	1			T2	4		T87	4		T103	11
all_values[2]	471	1			T2	4		T87	4		T103	11
all_values[3]	471	1			T2	4		T87	4		T103	11
all_values[4]	471	1			T2	4		T87	4		T103	11
all_values[5]	471	1			T2	4		T87	4		T103	11
all_values[6]	471	1			T2	4		T87	4		T103	11
all_values[7]	471	1			T2	4		T87	4		T103	11
all_values[8]	471	1			T2	4		T87	4		T103	11
all_values[9]	471	1			T2	4		T87	4		T103	11
all_values[10]	471	1			T2	4		T87	4		T103	11
all_values[11]	471	1			T2	4		T87	4		T103	11
all_values[12]	471	1			T2	4		T87	4		T103	11
all_values[13]	471	1			T2	4		T87	4		T103	11
all_values[14]	471	1			T2	4		T87	4		T103	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3796

1

T2

37

T87

25

T103

86

auto[1]

3269

1

T2

23

T87

35

T103

79

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T2

12

T87

17

T103

24

auto[1]

5959

1

T2

48

T87

43

T103

141

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4212

1

T2

35

T87

38

T103

101

auto[1]

2853

1

T2

25

T87

22

T103

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	47	1			T2	4		T205	3		T42	1
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T103	4		T203	2		T204	4
all_values[0]	auto[0]	auto[1]	auto[0]	40	1			T203	1		T205	4		T38	1
all_values[0]	auto[0]	auto[1]	auto[1]	113	1			T87	3		T103	3		T203	1
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T87	1		T103	3		T203	4
all_values[0]	auto[1]	auto[1]	auto[1]	80	1			T103	1		T203	3		T204	6
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T2	1		T204	1		T40	1
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T2	1		T103	3		T203	1
all_values[1]	auto[0]	auto[1]	auto[0]	26	1			T254	1		T255	3		T106	4
all_values[1]	auto[0]	auto[1]	auto[1]	123	1			T2	1		T87	3		T103	6
all_values[1]	auto[1]	auto[0]	auto[1]	107	1			T2	1		T103	2		T203	4
all_values[1]	auto[1]	auto[1]	auto[1]	83	1			T87	1		T203	2		T204	2
all_values[2]	auto[0]	auto[0]	auto[0]	36	1			T103	1		T105	1		T256	1
all_values[2]	auto[0]	auto[0]	auto[1]	121	1			T87	1		T103	4		T203	4
all_values[2]	auto[0]	auto[1]	auto[0]	21	1			T257	1		T66	2		T258	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T2	2		T103	1		T203	2
all_values[2]	auto[1]	auto[0]	auto[1]	103	1			T2	1		T103	3		T203	3
all_values[2]	auto[1]	auto[1]	auto[1]	94	1			T2	1		T87	3		T103	2
all_values[3]	auto[0]	auto[0]	auto[0]	54	1			T87	1		T103	1		T205	1
all_values[3]	auto[0]	auto[0]	auto[1]	103	1			T2	2		T103	1		T203	6
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T87	3		T205	1		T257	1
all_values[3]	auto[0]	auto[1]	auto[1]	109	1			T103	2		T203	2		T204	6
all_values[3]	auto[1]	auto[0]	auto[1]	96	1			T2	2		T103	3		T203	3
all_values[3]	auto[1]	auto[1]	auto[1]	80	1			T103	4		T204	4		T140	1
all_values[4]	auto[0]	auto[0]	auto[0]	50	1			T2	1		T87	1		T103	1
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T103	2		T203	3		T204	4
all_values[4]	auto[0]	auto[1]	auto[0]	19	1			T204	1		T94	2		T38	1
all_values[4]	auto[0]	auto[1]	auto[1]	118	1			T2	1		T87	1		T103	5
all_values[4]	auto[1]	auto[0]	auto[1]	99	1			T203	3		T204	1		T205	3
all_values[4]	auto[1]	auto[1]	auto[1]	92	1			T2	2		T87	2		T103	3
all_values[5]	auto[0]	auto[0]	auto[0]	44	1			T2	1		T103	1		T204	2
all_values[5]	auto[0]	auto[0]	auto[1]	113	1			T2	1		T87	2		T103	4
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T2	1		T204	3		T38	1
all_values[5]	auto[0]	auto[1]	auto[1]	100	1			T87	1		T103	1		T203	1
all_values[5]	auto[1]	auto[0]	auto[1]	117	1			T103	4		T203	4		T204	3
all_values[5]	auto[1]	auto[1]	auto[1]	78	1			T2	1		T87	1		T103	1
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T2	1		T103	1		T204	3
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T2	1		T87	1		T103	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T257	1		T66	3		T94	2
all_values[6]	auto[0]	auto[1]	auto[1]	109	1			T2	1		T87	1		T103	2
all_values[6]	auto[1]	auto[0]	auto[1]	121	1			T2	1		T87	1		T103	4
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T87	1		T103	3		T203	1
all_values[7]	auto[0]	auto[0]	auto[0]	46	1			T203	2		T66	2		T38	3
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T203	2		T204	3		T140	1
all_values[7]	auto[0]	auto[1]	auto[0]	42	1			T87	4		T66	1		T94	2
all_values[7]	auto[0]	auto[1]	auto[1]	102	1			T2	1		T103	5		T203	2
all_values[7]	auto[1]	auto[0]	auto[1]	110	1			T2	1		T103	3		T203	4
all_values[7]	auto[1]	auto[1]	auto[1]	89	1			T2	2		T103	3		T203	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T2	1		T103	3		T203	4
all_values[8]	auto[0]	auto[0]	auto[1]	120	1			T2	1		T103	2		T203	1
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T87	1		T103	1		T66	1
all_values[8]	auto[0]	auto[1]	auto[1]	89	1			T2	1		T87	1		T103	1
all_values[8]	auto[1]	auto[0]	auto[1]	115	1			T2	1		T87	2		T103	1
all_values[8]	auto[1]	auto[1]	auto[1]	84	1			T103	3		T203	1		T204	2
all_values[9]	auto[0]	auto[0]	auto[0]	29	1			T203	2		T204	1		T205	1
all_values[9]	auto[0]	auto[0]	auto[1]	107	1			T2	1		T103	5		T203	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T140	1		T257	2		T40	1
all_values[9]	auto[0]	auto[1]	auto[1]	111	1			T2	1		T87	1		T103	2
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T2	1		T87	2		T103	2
all_values[9]	auto[1]	auto[1]	auto[1]	95	1			T2	1		T87	1		T103	2
all_values[10]	auto[0]	auto[0]	auto[0]	54	1			T87	1		T103	1		T204	1
all_values[10]	auto[0]	auto[0]	auto[1]	104	1			T2	1		T87	2		T103	2
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T103	1		T140	4		T205	1
all_values[10]	auto[0]	auto[1]	auto[1]	112	1			T2	2		T103	1		T203	2
all_values[10]	auto[1]	auto[0]	auto[1]	95	1			T2	1		T87	1		T103	3
all_values[10]	auto[1]	auto[1]	auto[1]	77	1			T103	3		T203	3		T204	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T2	1		T87	1		T103	4
all_values[11]	auto[0]	auto[0]	auto[1]	98	1			T2	1		T103	2		T203	4
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T87	3		T257	1		T94	1
all_values[11]	auto[0]	auto[1]	auto[1]	114	1			T2	1		T103	2		T203	4
all_values[11]	auto[1]	auto[0]	auto[1]	103	1			T103	2		T203	1		T204	6
all_values[11]	auto[1]	auto[1]	auto[1]	90	1			T2	1		T103	1		T203	2
all_values[12]	auto[0]	auto[0]	auto[0]	52	1			T2	1		T103	1		T204	1
all_values[12]	auto[0]	auto[0]	auto[1]	111	1			T2	1		T87	1		T103	3
all_values[12]	auto[0]	auto[1]	auto[0]	42	1			T87	1		T204	1		T140	1
all_values[12]	auto[0]	auto[1]	auto[1]	85	1			T103	4		T203	2		T204	2
all_values[12]	auto[1]	auto[0]	auto[1]	102	1			T2	2		T87	2		T203	3
all_values[12]	auto[1]	auto[1]	auto[1]	79	1			T103	3		T203	3		T204	3
all_values[13]	auto[0]	auto[0]	auto[0]	61	1			T103	3		T204	3		T205	5
all_values[13]	auto[0]	auto[0]	auto[1]	103	1			T2	1		T87	2		T203	4
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T103	5		T203	2		T205	2
all_values[13]	auto[0]	auto[1]	auto[1]	94	1			T103	1		T204	5		T140	5
all_values[13]	auto[1]	auto[0]	auto[1]	96	1			T2	1		T87	1		T103	1
all_values[13]	auto[1]	auto[1]	auto[1]	85	1			T2	2		T87	1		T103	1
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T204	4		T140	4		T205	1
all_values[14]	auto[0]	auto[0]	auto[1]	110	1			T103	2		T203	6		T204	7
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T87	1		T203	1		T140	1
all_values[14]	auto[0]	auto[1]	auto[1]	96	1			T2	1		T87	1		T103	6
all_values[14]	auto[1]	auto[0]	auto[1]	105	1			T2	3		T87	2		T103	3
all_values[14]	auto[1]	auto[1]	auto[1]	86	1			T203	2		T204	1		T140	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal