Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.01	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	15	45	75.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	15	45	75.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	351	1			T1	1		T3	5		T6	1
all_values[1]	351	1			T1	1		T3	5		T6	1
all_values[2]	351	1			T1	1		T3	5		T6	1
all_values[3]	351	1			T1	1		T3	5		T6	1
all_values[4]	351	1			T1	1		T3	5		T6	1
all_values[5]	351	1			T1	1		T3	5		T6	1
all_values[6]	351	1			T1	1		T3	5		T6	1
all_values[7]	351	1			T1	1		T3	5		T6	1
all_values[8]	351	1			T1	1		T3	5		T6	1
all_values[9]	351	1			T1	1		T3	5		T6	1
all_values[10]	351	1			T1	1		T3	5		T6	1
all_values[11]	351	1			T1	1		T3	5		T6	1
all_values[12]	351	1			T1	1		T3	5		T6	1
all_values[13]	351	1			T1	1		T3	5		T6	1
all_values[14]	351	1			T1	1		T3	5		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3389

1

T1

15

T3

53

T6

15

auto[1]

1876

1

T3

22

T7

49

T8

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T1

15

T3

8

T6

15

auto[1]

4124

1

T3

67

T7

97

T8

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	15	45	75.00	15

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	[auto[0]]	--	--	15

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	76	1			T1	1		T3	1		T6	1
all_values[0]	auto[0]	auto[1]	159	1			T3	2		T7	6		T8	2
all_values[0]	auto[1]	auto[1]	116	1			T3	2		T7	2		T8	1
all_values[1]	auto[0]	auto[0]	69	1			T1	1		T6	1		T8	1
all_values[1]	auto[0]	auto[1]	169	1			T3	3		T7	4		T8	3
all_values[1]	auto[1]	auto[1]	113	1			T3	2		T7	4		T8	1
all_values[2]	auto[0]	auto[0]	86	1			T1	1		T6	1		T7	3
all_values[2]	auto[0]	auto[1]	151	1			T3	3		T7	3		T9	3
all_values[2]	auto[1]	auto[1]	114	1			T3	2		T7	2		T9	4
all_values[3]	auto[0]	auto[0]	82	1			T1	1		T3	5		T6	1
all_values[3]	auto[0]	auto[1]	135	1			T7	2		T8	3		T9	4
all_values[3]	auto[1]	auto[1]	134	1			T7	3		T8	2		T9	4
all_values[4]	auto[0]	auto[0]	91	1			T1	1		T6	1		T7	4
all_values[4]	auto[0]	auto[1]	148	1			T3	4		T7	3		T8	3
all_values[4]	auto[1]	auto[1]	112	1			T3	1		T7	1		T8	2
all_values[5]	auto[0]	auto[0]	74	1			T1	1		T6	1		T7	1
all_values[5]	auto[0]	auto[1]	164	1			T3	3		T7	3		T9	1
all_values[5]	auto[1]	auto[1]	113	1			T3	2		T7	4		T9	4
all_values[6]	auto[0]	auto[0]	84	1			T1	1		T6	1		T7	1
all_values[6]	auto[0]	auto[1]	131	1			T3	2		T7	3		T8	2
all_values[6]	auto[1]	auto[1]	136	1			T3	3		T7	4		T8	3
all_values[7]	auto[0]	auto[0]	64	1			T1	1		T3	1		T6	1
all_values[7]	auto[0]	auto[1]	141	1			T3	3		T7	1		T8	4
all_values[7]	auto[1]	auto[1]	146	1			T3	1		T7	6		T8	1
all_values[8]	auto[0]	auto[0]	71	1			T1	1		T3	1		T6	1
all_values[8]	auto[0]	auto[1]	154	1			T3	3		T7	1		T8	1
all_values[8]	auto[1]	auto[1]	126	1			T3	1		T7	4		T8	2
all_values[9]	auto[0]	auto[0]	77	1			T1	1		T6	1		T7	1
all_values[9]	auto[0]	auto[1]	131	1			T3	4		T7	2		T8	2
all_values[9]	auto[1]	auto[1]	143	1			T3	1		T7	5		T8	3
all_values[10]	auto[0]	auto[0]	47	1			T1	1		T6	1		T7	2
all_values[10]	auto[0]	auto[1]	174	1			T3	4		T7	3		T8	3
all_values[10]	auto[1]	auto[1]	130	1			T3	1		T7	3		T8	2
all_values[11]	auto[0]	auto[0]	78	1			T1	1		T6	1		T7	1
all_values[11]	auto[0]	auto[1]	154	1			T3	4		T7	4		T8	2
all_values[11]	auto[1]	auto[1]	119	1			T3	1		T7	3		T8	2
all_values[12]	auto[0]	auto[0]	83	1			T1	1		T6	1		T8	5
all_values[12]	auto[0]	auto[1]	153	1			T3	3		T7	5		T9	5
all_values[12]	auto[1]	auto[1]	115	1			T3	2		T7	3		T9	1
all_values[13]	auto[0]	auto[0]	98	1			T1	1		T6	1		T7	2
all_values[13]	auto[0]	auto[1]	137	1			T3	4		T7	4		T9	1
all_values[13]	auto[1]	auto[1]	116	1			T3	1		T7	2		T9	4
all_values[14]	auto[0]	auto[0]	61	1			T1	1		T6	1		T7	1
all_values[14]	auto[0]	auto[1]	147	1			T3	3		T7	4		T8	1
all_values[14]	auto[1]	auto[1]	143	1			T3	2		T7	3		T8	3