| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 52.82 | 40.66 | 40.72 | 91.14 | 0.00 | 42.98 | 99.68 | 54.53 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 45.65 | 45.65 | 38.85 | 38.85 | 36.17 | 36.17 | 91.77 | 91.77 | 0.00 | 0.00 | 41.35 | 41.35 | 96.50 | 96.50 | 14.95 | 14.95 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4012476103 |
| 50.75 | 5.10 | 40.13 | 1.29 | 38.50 | 2.33 | 95.26 | 3.49 | 0.00 | 0.00 | 42.77 | 1.42 | 96.50 | 0.00 | 42.11 | 27.16 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3527508491 |
| 52.08 | 1.33 | 40.17 | 0.03 | 39.78 | 1.28 | 96.26 | 1.00 | 0.00 | 0.00 | 42.91 | 0.14 | 97.77 | 1.27 | 47.68 | 5.58 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2015701870 |
| 52.53 | 0.44 | 40.17 | 0.00 | 39.78 | 0.00 | 96.63 | 0.37 | 0.00 | 0.00 | 42.91 | 0.00 | 97.77 | 0.00 | 50.42 | 2.74 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.2490807639 |
| 52.91 | 0.38 | 40.62 | 0.46 | 39.89 | 0.11 | 96.63 | 0.00 | 0.00 | 0.00 | 42.91 | 0.00 | 99.68 | 1.91 | 50.63 | 0.21 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1126149336 |
| 53.21 | 0.30 | 40.66 | 0.03 | 40.31 | 0.41 | 97.38 | 0.75 | 0.00 | 0.00 | 42.98 | 0.07 | 99.68 | 0.00 | 51.47 | 0.84 | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1964569842 |
| 53.36 | 0.15 | 40.66 | 0.00 | 40.31 | 0.00 | 97.38 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 52.53 | 1.05 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.2959658900 |
| 53.48 | 0.12 | 40.66 | 0.00 | 40.31 | 0.00 | 97.38 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.37 | 0.84 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3204328797 |
| 53.56 | 0.08 | 40.66 | 0.00 | 40.31 | 0.00 | 97.38 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 53.89 | 0.53 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.246959554 |
| 53.60 | 0.05 | 40.66 | 0.00 | 40.42 | 0.11 | 97.38 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.11 | 0.21 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2437525267 |
| 53.63 | 0.03 | 40.66 | 0.00 | 40.42 | 0.00 | 97.38 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.32 | 0.21 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1038738585 |
| 53.66 | 0.03 | 40.66 | 0.00 | 40.50 | 0.08 | 97.51 | 0.12 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.32 | 0.00 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1912914195 |
| 53.68 | 0.02 | 40.66 | 0.00 | 40.50 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.42 | 0.11 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3029526634 |
| 53.69 | 0.02 | 40.66 | 0.00 | 40.50 | 0.00 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.53 | 0.11 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2003096473 |
| 53.70 | 0.01 | 40.66 | 0.00 | 40.57 | 0.08 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.53 | 0.00 | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4292489222 |
| 53.71 | 0.01 | 40.66 | 0.00 | 40.65 | 0.08 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.53 | 0.00 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3007360456 |
| 53.72 | 0.01 | 40.66 | 0.00 | 40.68 | 0.04 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.53 | 0.00 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.388368723 |
| 53.72 | 0.01 | 40.66 | 0.00 | 40.72 | 0.04 | 97.51 | 0.00 | 0.00 | 0.00 | 42.98 | 0.00 | 99.68 | 0.00 | 54.53 | 0.00 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1511874512 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.741326996 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2497610376 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4183455621 |
| /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1149746074 |
| /workspace/coverage/cover_reg_top/0.i2c_intr_test.1456874835 |
| /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.557124965 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_errors.443746140 |
| /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2297867950 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4275856108 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.607216560 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4185809986 |
| /workspace/coverage/cover_reg_top/1.i2c_csr_rw.607773150 |
| /workspace/coverage/cover_reg_top/1.i2c_intr_test.4290984652 |
| /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2257265207 |
| /workspace/coverage/cover_reg_top/1.i2c_tl_errors.716662237 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.930537330 |
| /workspace/coverage/cover_reg_top/10.i2c_csr_rw.513551660 |
| /workspace/coverage/cover_reg_top/10.i2c_intr_test.433340750 |
| /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3170678346 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1730873696 |
| /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1875088669 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1177075030 |
| /workspace/coverage/cover_reg_top/11.i2c_csr_rw.645260249 |
| /workspace/coverage/cover_reg_top/11.i2c_intr_test.1104680566 |
| /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.761195678 |
| /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3345232781 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1043113228 |
| /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1507766695 |
| /workspace/coverage/cover_reg_top/12.i2c_intr_test.2098346632 |
| /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1276809725 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3873028283 |
| /workspace/coverage/cover_reg_top/13.i2c_csr_rw.643301155 |
| /workspace/coverage/cover_reg_top/13.i2c_intr_test.4140489278 |
| /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1870817511 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3753016916 |
| /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3704794651 |
| /workspace/coverage/cover_reg_top/14.i2c_intr_test.1534683346 |
| /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.408604367 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3331801508 |
| /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3757735116 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1899319249 |
| /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1553491297 |
| /workspace/coverage/cover_reg_top/15.i2c_intr_test.3493254238 |
| /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1502675518 |
| /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3171092572 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4006228166 |
| /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2729001266 |
| /workspace/coverage/cover_reg_top/16.i2c_intr_test.3002231035 |
| /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2354175355 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_errors.564418036 |
| /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.644039616 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3937172180 |
| /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3543674746 |
| /workspace/coverage/cover_reg_top/17.i2c_intr_test.1375096104 |
| /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.613309152 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2284920968 |
| /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1506850105 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4085922217 |
| /workspace/coverage/cover_reg_top/18.i2c_csr_rw.247066408 |
| /workspace/coverage/cover_reg_top/18.i2c_intr_test.3805826995 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2087959988 |
| /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2747768126 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2411325063 |
| /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2354102508 |
| /workspace/coverage/cover_reg_top/19.i2c_intr_test.1164107205 |
| /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3174598423 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_errors.657163118 |
| /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3495420846 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3105831405 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.494651357 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2678744875 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2696084599 |
| /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3351772752 |
| /workspace/coverage/cover_reg_top/2.i2c_intr_test.714413877 |
| /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.692290844 |
| /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3008804627 |
| /workspace/coverage/cover_reg_top/20.i2c_intr_test.357015619 |
| /workspace/coverage/cover_reg_top/21.i2c_intr_test.1580989141 |
| /workspace/coverage/cover_reg_top/22.i2c_intr_test.2401620305 |
| /workspace/coverage/cover_reg_top/23.i2c_intr_test.4038048226 |
| /workspace/coverage/cover_reg_top/24.i2c_intr_test.2172596770 |
| /workspace/coverage/cover_reg_top/25.i2c_intr_test.2833248663 |
| /workspace/coverage/cover_reg_top/26.i2c_intr_test.580677547 |
| /workspace/coverage/cover_reg_top/27.i2c_intr_test.4106481982 |
| /workspace/coverage/cover_reg_top/29.i2c_intr_test.953227227 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4047984927 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1259580990 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2323662936 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2038088883 |
| /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2764525281 |
| /workspace/coverage/cover_reg_top/3.i2c_intr_test.697235685 |
| /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1373055761 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1662982358 |
| /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.628310157 |
| /workspace/coverage/cover_reg_top/31.i2c_intr_test.1195283497 |
| /workspace/coverage/cover_reg_top/32.i2c_intr_test.1125644911 |
| /workspace/coverage/cover_reg_top/33.i2c_intr_test.2736641603 |
| /workspace/coverage/cover_reg_top/34.i2c_intr_test.1927775544 |
| /workspace/coverage/cover_reg_top/35.i2c_intr_test.877610203 |
| /workspace/coverage/cover_reg_top/36.i2c_intr_test.444267541 |
| /workspace/coverage/cover_reg_top/38.i2c_intr_test.1780415422 |
| /workspace/coverage/cover_reg_top/39.i2c_intr_test.652333033 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1555740002 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.957993322 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1466360322 |
| /workspace/coverage/cover_reg_top/4.i2c_csr_rw.734671907 |
| /workspace/coverage/cover_reg_top/4.i2c_intr_test.575285173 |
| /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2271735739 |
| /workspace/coverage/cover_reg_top/40.i2c_intr_test.3139549994 |
| /workspace/coverage/cover_reg_top/41.i2c_intr_test.1632858782 |
| /workspace/coverage/cover_reg_top/42.i2c_intr_test.178599970 |
| /workspace/coverage/cover_reg_top/43.i2c_intr_test.1777047263 |
| /workspace/coverage/cover_reg_top/44.i2c_intr_test.909681591 |
| /workspace/coverage/cover_reg_top/45.i2c_intr_test.350642762 |
| /workspace/coverage/cover_reg_top/46.i2c_intr_test.2990878162 |
| /workspace/coverage/cover_reg_top/47.i2c_intr_test.556614224 |
| /workspace/coverage/cover_reg_top/48.i2c_intr_test.3739598623 |
| /workspace/coverage/cover_reg_top/49.i2c_intr_test.3702344204 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.353143996 |
| /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2897718158 |
| /workspace/coverage/cover_reg_top/5.i2c_intr_test.484698598 |
| /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3764718561 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.381846672 |
| /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4190628796 |
| /workspace/coverage/cover_reg_top/6.i2c_intr_test.1721123376 |
| /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4156306356 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2658777692 |
| /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2790296068 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2480210888 |
| /workspace/coverage/cover_reg_top/7.i2c_csr_rw.511769106 |
| /workspace/coverage/cover_reg_top/7.i2c_intr_test.298605835 |
| /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1533970727 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_errors.17541723 |
| /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2412814166 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2082415048 |
| /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3367759005 |
| /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.819745596 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1022152658 |
| /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2663089069 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2133604071 |
| /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2105248936 |
| /workspace/coverage/cover_reg_top/9.i2c_intr_test.3250073227 |
| /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1908228457 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1472465953 |
| /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2585298043 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1472465953 | Jun 04 12:44:57 PM PDT 24 | Jun 04 12:45:01 PM PDT 24 | 225371965 ps | ||
| T2 | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3757735116 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 242755995 ps | ||
| T3 | /workspace/coverage/cover_reg_top/29.i2c_intr_test.953227227 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 18205219 ps | ||
| T4 | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4012476103 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:47 PM PDT 24 | 118248352 ps | ||
| T6 | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2015701870 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 155251643 ps | ||
| T5 | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2696084599 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 29352523 ps | ||
| T7 | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3139549994 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 31515098 ps | ||
| T10 | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2257265207 | Jun 04 12:44:38 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 27653063 ps | ||
| T8 | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3002231035 | Jun 04 12:44:50 PM PDT 24 | Jun 04 12:44:51 PM PDT 24 | 40561194 ps | ||
| T9 | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1780415422 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 32274352 ps | ||
| T11 | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4006228166 | Jun 04 12:44:56 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 31554680 ps | ||
| T17 | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3527508491 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 25962027 ps | ||
| T12 | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.657163118 | Jun 04 12:45:08 PM PDT 24 | Jun 04 12:45:11 PM PDT 24 | 99482898 ps | ||
| T13 | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.716662237 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 124747380 ps | ||
| T18 | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2585298043 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 306134100 ps | ||
| T14 | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4085922217 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:07 PM PDT 24 | 30672542 ps | ||
| T21 | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1553491297 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 89406413 ps | ||
| T15 | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2082415048 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 241401434 ps | ||
| T16 | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1899319249 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 196744784 ps | ||
| T19 | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2747768126 | Jun 04 12:45:05 PM PDT 24 | Jun 04 12:45:09 PM PDT 24 | 157420046 ps | ||
| T20 | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2271735739 | Jun 04 12:44:45 PM PDT 24 | Jun 04 12:44:47 PM PDT 24 | 292857786 ps | ||
| T54 | /workspace/coverage/cover_reg_top/28.i2c_intr_test.2959658900 | Jun 04 12:45:06 PM PDT 24 | Jun 04 12:45:08 PM PDT 24 | 29342582 ps | ||
| T55 | /workspace/coverage/cover_reg_top/42.i2c_intr_test.178599970 | Jun 04 12:45:08 PM PDT 24 | Jun 04 12:45:10 PM PDT 24 | 48338733 ps | ||
| T80 | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1912914195 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 135693437 ps | ||
| T58 | /workspace/coverage/cover_reg_top/43.i2c_intr_test.1777047263 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 48046321 ps | ||
| T81 | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1730873696 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 190285422 ps | ||
| T56 | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1466360322 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 36598167 ps | ||
| T57 | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2663089069 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 89582050 ps | ||
| T22 | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4275856108 | Jun 04 12:44:38 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 97324766 ps | ||
| T30 | /workspace/coverage/cover_reg_top/0.i2c_intr_test.1456874835 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 21349705 ps | ||
| T31 | /workspace/coverage/cover_reg_top/41.i2c_intr_test.1632858782 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 22928033 ps | ||
| T32 | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1177075030 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 41766363 ps | ||
| T33 | /workspace/coverage/cover_reg_top/32.i2c_intr_test.1125644911 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 56400016 ps | ||
| T34 | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1964569842 | Jun 04 12:44:47 PM PDT 24 | Jun 04 12:44:51 PM PDT 24 | 165681381 ps | ||
| T35 | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1038738585 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 60360091 ps | ||
| T23 | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2354175355 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 157885644 ps | ||
| T24 | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4047984927 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:48 PM PDT 24 | 82799896 ps | ||
| T25 | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2764525281 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:43 PM PDT 24 | 21009087 ps | ||
| T44 | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2284920968 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 45006400 ps | ||
| T45 | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1511874512 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:54 PM PDT 24 | 163105553 ps | ||
| T46 | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1506850105 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:57 PM PDT 24 | 427836867 ps | ||
| T47 | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3739598623 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 20722489 ps | ||
| T48 | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1662982358 | Jun 04 12:44:40 PM PDT 24 | Jun 04 12:44:43 PM PDT 24 | 147340166 ps | ||
| T49 | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.388368723 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 195627599 ps | ||
| T50 | /workspace/coverage/cover_reg_top/30.i2c_intr_test.2490807639 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 65045453 ps | ||
| T51 | /workspace/coverage/cover_reg_top/23.i2c_intr_test.4038048226 | Jun 04 12:45:02 PM PDT 24 | Jun 04 12:45:04 PM PDT 24 | 35582446 ps | ||
| T52 | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3008804627 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 239565035 ps | ||
| T82 | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3345232781 | Jun 04 12:44:57 PM PDT 24 | Jun 04 12:45:01 PM PDT 24 | 216127744 ps | ||
| T83 | /workspace/coverage/cover_reg_top/44.i2c_intr_test.909681591 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 16863278 ps | ||
| T72 | /workspace/coverage/cover_reg_top/2.i2c_intr_test.714413877 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 53270766 ps | ||
| T84 | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2133604071 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 68644194 ps | ||
| T85 | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4183455621 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 31490715 ps | ||
| T73 | /workspace/coverage/cover_reg_top/35.i2c_intr_test.877610203 | Jun 04 12:45:02 PM PDT 24 | Jun 04 12:45:04 PM PDT 24 | 25213635 ps | ||
| T26 | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1126149336 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 48173292 ps | ||
| T27 | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1149746074 | Jun 04 12:44:36 PM PDT 24 | Jun 04 12:44:38 PM PDT 24 | 17129533 ps | ||
| T86 | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2658777692 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:47 PM PDT 24 | 88444374 ps | ||
| T28 | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1908228457 | Jun 04 12:44:56 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 73637334 ps | ||
| T62 | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2437525267 | Jun 04 12:44:51 PM PDT 24 | Jun 04 12:44:54 PM PDT 24 | 382847949 ps | ||
| T29 | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.645260249 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:53 PM PDT 24 | 107829584 ps | ||
| T36 | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4190628796 | Jun 04 12:44:40 PM PDT 24 | Jun 04 12:44:42 PM PDT 24 | 375878212 ps | ||
| T53 | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1533970727 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 55725062 ps | ||
| T67 | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3029526634 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:53 PM PDT 24 | 59487168 ps | ||
| T78 | /workspace/coverage/cover_reg_top/1.i2c_intr_test.4290984652 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:37 PM PDT 24 | 23723853 ps | ||
| T87 | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.613309152 | Jun 04 12:44:56 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 59583294 ps | ||
| T88 | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3873028283 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 37556488 ps | ||
| T89 | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3764718561 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 115704879 ps | ||
| T90 | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4185809986 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:37 PM PDT 24 | 24905278 ps | ||
| T70 | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2003096473 | Jun 04 12:44:50 PM PDT 24 | Jun 04 12:44:52 PM PDT 24 | 219968416 ps | ||
| T91 | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3367759005 | Jun 04 12:44:49 PM PDT 24 | Jun 04 12:44:51 PM PDT 24 | 51555705 ps | ||
| T92 | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2087959988 | Jun 04 12:45:01 PM PDT 24 | Jun 04 12:45:04 PM PDT 24 | 374055522 ps | ||
| T61 | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3007360456 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 295699769 ps | ||
| T71 | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2323662936 | Jun 04 12:44:46 PM PDT 24 | Jun 04 12:44:48 PM PDT 24 | 96678064 ps | ||
| T37 | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.513551660 | Jun 04 12:44:51 PM PDT 24 | Jun 04 12:44:53 PM PDT 24 | 45732964 ps | ||
| T38 | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.957993322 | Jun 04 12:44:38 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 41257904 ps | ||
| T93 | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.443746140 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 50800915 ps | ||
| T94 | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2497610376 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 1272433596 ps | ||
| T95 | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.819745596 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 35421207 ps | ||
| T96 | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.17541723 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:43 PM PDT 24 | 43352129 ps | ||
| T97 | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.692290844 | Jun 04 12:44:40 PM PDT 24 | Jun 04 12:44:42 PM PDT 24 | 246949614 ps | ||
| T98 | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2412814166 | Jun 04 12:44:42 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 74990214 ps | ||
| T99 | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1022152658 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 140558764 ps | ||
| T41 | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.494651357 | Jun 04 12:44:34 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 639737213 ps | ||
| T76 | /workspace/coverage/cover_reg_top/36.i2c_intr_test.444267541 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 39040132 ps | ||
| T39 | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.607773150 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:40 PM PDT 24 | 80815211 ps | ||
| T74 | /workspace/coverage/cover_reg_top/37.i2c_intr_test.246959554 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 61237939 ps | ||
| T100 | /workspace/coverage/cover_reg_top/3.i2c_intr_test.697235685 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 24659231 ps | ||
| T63 | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.628310157 | Jun 04 12:44:46 PM PDT 24 | Jun 04 12:44:49 PM PDT 24 | 746329488 ps | ||
| T79 | /workspace/coverage/cover_reg_top/27.i2c_intr_test.4106481982 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 56704284 ps | ||
| T101 | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.734671907 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 36768749 ps | ||
| T102 | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.643301155 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 118282711 ps | ||
| T103 | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1373055761 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 97523216 ps | ||
| T104 | /workspace/coverage/cover_reg_top/5.i2c_intr_test.484698598 | Jun 04 12:44:40 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 24468974 ps | ||
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| T106 | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3331801508 | Jun 04 12:44:51 PM PDT 24 | Jun 04 12:44:54 PM PDT 24 | 460480850 ps | ||
| T40 | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.511769106 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 21236306 ps | ||
| T107 | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2038088883 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 441209755 ps | ||
| T108 | /workspace/coverage/cover_reg_top/6.i2c_intr_test.1721123376 | Jun 04 12:44:48 PM PDT 24 | Jun 04 12:44:49 PM PDT 24 | 43634636 ps | ||
| T109 | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1555740002 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 992171974 ps | ||
| T75 | /workspace/coverage/cover_reg_top/33.i2c_intr_test.2736641603 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 33850088 ps | ||
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| T111 | /workspace/coverage/cover_reg_top/13.i2c_intr_test.4140489278 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 16110267 ps | ||
| T112 | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.930537330 | Jun 04 12:44:51 PM PDT 24 | Jun 04 12:44:53 PM PDT 24 | 27362068 ps | ||
| T113 | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3753016916 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:54 PM PDT 24 | 139352008 ps | ||
| T114 | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1259580990 | Jun 04 12:44:40 PM PDT 24 | Jun 04 12:44:47 PM PDT 24 | 1690370898 ps | ||
| T64 | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2297867950 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:37 PM PDT 24 | 137719114 ps | ||
| T115 | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.761195678 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:57 PM PDT 24 | 21319588 ps | ||
| T42 | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.247066408 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 29650779 ps | ||
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| T66 | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3204328797 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 92405273 ps | ||
| T119 | /workspace/coverage/cover_reg_top/24.i2c_intr_test.2172596770 | Jun 04 12:45:09 PM PDT 24 | Jun 04 12:45:11 PM PDT 24 | 17414347 ps | ||
| T120 | /workspace/coverage/cover_reg_top/9.i2c_intr_test.3250073227 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 22392446 ps | ||
| T121 | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.644039616 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:56 PM PDT 24 | 132375744 ps | ||
| T122 | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1507766695 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 89352721 ps | ||
| T123 | /workspace/coverage/cover_reg_top/31.i2c_intr_test.1195283497 | Jun 04 12:45:08 PM PDT 24 | Jun 04 12:45:09 PM PDT 24 | 41197636 ps | ||
| T124 | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.353143996 | Jun 04 12:44:48 PM PDT 24 | Jun 04 12:44:50 PM PDT 24 | 47185846 ps | ||
| T125 | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2411325063 | Jun 04 12:45:08 PM PDT 24 | Jun 04 12:45:10 PM PDT 24 | 24418097 ps | ||
| T126 | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1276809725 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:57 PM PDT 24 | 49087397 ps | ||
| T43 | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3351772752 | Jun 04 12:44:37 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 22575426 ps | ||
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| T129 | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.564418036 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 23870263 ps | ||
| T130 | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3171092572 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:57 PM PDT 24 | 74281152 ps | ||
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| T132 | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.381846672 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 50458839 ps | ||
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| T135 | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2480210888 | Jun 04 12:44:46 PM PDT 24 | Jun 04 12:44:48 PM PDT 24 | 198222325 ps | ||
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| T138 | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1043113228 | Jun 04 12:44:55 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 341449357 ps | ||
| T139 | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3105831405 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 503872614 ps | ||
| T140 | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2678744875 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:37 PM PDT 24 | 27281407 ps | ||
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| T144 | /workspace/coverage/cover_reg_top/20.i2c_intr_test.357015619 | Jun 04 12:45:03 PM PDT 24 | Jun 04 12:45:05 PM PDT 24 | 98396976 ps | ||
| T145 | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2729001266 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:57 PM PDT 24 | 75053947 ps | ||
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| T148 | /workspace/coverage/cover_reg_top/18.i2c_intr_test.3805826995 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:07 PM PDT 24 | 17631069 ps | ||
| T149 | /workspace/coverage/cover_reg_top/47.i2c_intr_test.556614224 | Jun 04 12:45:02 PM PDT 24 | Jun 04 12:45:03 PM PDT 24 | 39246912 ps | ||
| T68 | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4156306356 | Jun 04 12:44:43 PM PDT 24 | Jun 04 12:44:45 PM PDT 24 | 70316082 ps | ||
| T150 | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3937172180 | Jun 04 12:45:10 PM PDT 24 | Jun 04 12:45:13 PM PDT 24 | 33035726 ps | ||
| T59 | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4292489222 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:58 PM PDT 24 | 169432483 ps | ||
| T151 | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2897718158 | Jun 04 12:44:44 PM PDT 24 | Jun 04 12:44:46 PM PDT 24 | 399096193 ps | ||
| T60 | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2790296068 | Jun 04 12:44:41 PM PDT 24 | Jun 04 12:44:44 PM PDT 24 | 604156481 ps | ||
| T152 | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2354102508 | Jun 04 12:45:08 PM PDT 24 | Jun 04 12:45:10 PM PDT 24 | 17860603 ps | ||
| T69 | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.408604367 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 151283727 ps | ||
| T153 | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.557124965 | Jun 04 12:44:34 PM PDT 24 | Jun 04 12:44:36 PM PDT 24 | 161917038 ps | ||
| T154 | /workspace/coverage/cover_reg_top/17.i2c_intr_test.1375096104 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 49104782 ps | ||
| T155 | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.741326996 | Jun 04 12:44:35 PM PDT 24 | Jun 04 12:44:39 PM PDT 24 | 426011044 ps | ||
| T156 | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1870817511 | Jun 04 12:44:54 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 284218110 ps | ||
| T157 | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3170678346 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 60008834 ps | ||
| T158 | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3174598423 | Jun 04 12:45:06 PM PDT 24 | Jun 04 12:45:08 PM PDT 24 | 172638359 ps | ||
| T159 | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2990878162 | Jun 04 12:45:04 PM PDT 24 | Jun 04 12:45:06 PM PDT 24 | 27729214 ps | ||
| T160 | /workspace/coverage/cover_reg_top/14.i2c_intr_test.1534683346 | Jun 04 12:44:56 PM PDT 24 | Jun 04 12:44:59 PM PDT 24 | 19032840 ps | ||
| T161 | /workspace/coverage/cover_reg_top/15.i2c_intr_test.3493254238 | Jun 04 12:44:53 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 15457849 ps | ||
| T162 | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1502675518 | Jun 04 12:44:52 PM PDT 24 | Jun 04 12:44:55 PM PDT 24 | 36314348 ps | ||
| T163 | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.607216560 | Jun 04 12:44:39 PM PDT 24 | Jun 04 12:44:41 PM PDT 24 | 31136379 ps |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4012476103 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 118248352 ps |
| CPU time | 1.21 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:47 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-6399c0d0-1209-4954-b7cd-f6ceb8f7645d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012476103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou tstanding.4012476103 |
| Directory | /workspace/4.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_intr_test.3527508491 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 25962027 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-14997eb4-a750-4546-a2df-852848512e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527508491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3527508491 |
| Directory | /workspace/8.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2015701870 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 155251643 ps |
| CPU time | 2.74 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-1e61c9e2-6df0-4dc6-b8d1-37782a3aecff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015701870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2015701870 |
| Directory | /workspace/15.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.i2c_intr_test.2490807639 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 65045453 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204296 kb |
| Host | smart-fc430927-187d-4212-91d6-d56debdbdd2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490807639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2490807639 |
| Directory | /workspace/30.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1126149336 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 48173292 ps |
| CPU time | 0.85 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204412 kb |
| Host | smart-59b930e1-6ff9-4d54-a654-5223dc8fe29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126149336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1126149336 |
| Directory | /workspace/0.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1964569842 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 165681381 ps |
| CPU time | 2.42 seconds |
| Started | Jun 04 12:44:47 PM PDT 24 |
| Finished | Jun 04 12:44:51 PM PDT 24 |
| Peak memory | 204688 kb |
| Host | smart-fd5122d3-c02b-4fa2-b0c8-1732ec48c996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964569842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1964569842 |
| Directory | /workspace/4.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/28.i2c_intr_test.2959658900 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 29342582 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:45:06 PM PDT 24 |
| Finished | Jun 04 12:45:08 PM PDT 24 |
| Peak memory | 204264 kb |
| Host | smart-c4cd0e4f-2c44-47a5-a912-94ffe0b14ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959658900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2959658900 |
| Directory | /workspace/28.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3204328797 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 92405273 ps |
| CPU time | 1.19 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-04ddb023-2e9f-4567-89c2-fdf9db6eb7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204328797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou tstanding.3204328797 |
| Directory | /workspace/5.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/37.i2c_intr_test.246959554 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 61237939 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204272 kb |
| Host | smart-acf6aba1-0ef3-4c80-8dcb-38816f81616c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246959554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.246959554 |
| Directory | /workspace/37.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2437525267 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 382847949 ps |
| CPU time | 2.27 seconds |
| Started | Jun 04 12:44:51 PM PDT 24 |
| Finished | Jun 04 12:44:54 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-fb19fd75-9a9b-4748-adfc-5c8849f19e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437525267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2437525267 |
| Directory | /workspace/12.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1038738585 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 60360091 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204208 kb |
| Host | smart-90f87c11-7e30-493d-bd35-0a0a5e099d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038738585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o utstanding.1038738585 |
| Directory | /workspace/12.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1912914195 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 135693437 ps |
| CPU time | 1.99 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-af3aea52-5190-4c05-9674-fc403590da12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912914195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1912914195 |
| Directory | /workspace/2.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3029526634 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 59487168 ps |
| CPU time | 1.21 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-9cbe9698-f3dd-43f8-8ed2-545f15b3c4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029526634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o utstanding.3029526634 |
| Directory | /workspace/13.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2003096473 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 219968416 ps |
| CPU time | 1.46 seconds |
| Started | Jun 04 12:44:50 PM PDT 24 |
| Finished | Jun 04 12:44:52 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-8bf09524-cf84-4fc4-9604-7ea313069267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003096473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2003096473 |
| Directory | /workspace/4.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4292489222 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 169432483 ps |
| CPU time | 2.64 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-31e311ef-666f-469f-b169-59633e7cd747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292489222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4292489222 |
| Directory | /workspace/13.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3007360456 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 295699769 ps |
| CPU time | 2.26 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 203368 kb |
| Host | smart-e964fa9a-a1ce-4848-ac6c-f291fdc1669f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007360456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3007360456 |
| Directory | /workspace/5.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.388368723 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 195627599 ps |
| CPU time | 2.54 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-126981b8-4a26-4941-981f-d9f5490f6039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388368723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.388368723 |
| Directory | /workspace/1.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1511874512 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 163105553 ps |
| CPU time | 1.6 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:54 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-3e620b7f-d8f8-4aec-861b-29a7f30d0738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511874512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1511874512 |
| Directory | /workspace/11.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.741326996 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 426011044 ps |
| CPU time | 2.05 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-ea27a1fd-48b4-43af-8d76-0e5cd424b33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741326996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.741326996 |
| Directory | /workspace/0.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2497610376 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1272433596 ps |
| CPU time | 3.31 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-ec85860b-a91c-4f48-8d0d-8b604314579e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497610376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2497610376 |
| Directory | /workspace/0.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4183455621 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 31490715 ps |
| CPU time | 0.86 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-bd820eb3-77da-4dd3-90bc-4487f67f2b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183455621 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4183455621 |
| Directory | /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1149746074 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 17129533 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:38 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-3eb55f32-3b1a-41d5-be38-bf69f63f6378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149746074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1149746074 |
| Directory | /workspace/0.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_intr_test.1456874835 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 21349705 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-83e17891-aed1-4bfb-aa89-a7bc12613452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456874835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1456874835 |
| Directory | /workspace/0.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.557124965 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 161917038 ps |
| CPU time | 0.95 seconds |
| Started | Jun 04 12:44:34 PM PDT 24 |
| Finished | Jun 04 12:44:36 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-cca3fa4b-8b65-4785-a218-b9cb6c2a352c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557124965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out standing.557124965 |
| Directory | /workspace/0.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_errors.443746140 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 50800915 ps |
| CPU time | 1.34 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 204464 kb |
| Host | smart-6e078e20-b93c-4cb8-bf89-172d88362ace |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443746140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.443746140 |
| Directory | /workspace/0.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2297867950 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 137719114 ps |
| CPU time | 1.5 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-207588fc-4dd7-4708-8e1c-3cb5f4c203b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297867950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2297867950 |
| Directory | /workspace/0.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4275856108 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 97324766 ps |
| CPU time | 1.4 seconds |
| Started | Jun 04 12:44:38 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-07d2de73-62a4-4b90-a68a-93baf5a4edd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275856108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.4275856108 |
| Directory | /workspace/1.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.607216560 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 31136379 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:44:39 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-f6fcddae-b25b-41ee-a6e7-d630daf581bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607216560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.607216560 |
| Directory | /workspace/1.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4185809986 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 24905278 ps |
| CPU time | 0.84 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-0d5988b9-c558-4203-9267-2c705a4ca713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185809986 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4185809986 |
| Directory | /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_csr_rw.607773150 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 80815211 ps |
| CPU time | 0.83 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-23eb6d5f-b460-4242-afae-72fbaa376c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607773150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.607773150 |
| Directory | /workspace/1.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_intr_test.4290984652 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 23723853 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 204240 kb |
| Host | smart-449f9bdf-af90-4591-8ce0-c7d0bab302aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290984652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.4290984652 |
| Directory | /workspace/1.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2257265207 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 27653063 ps |
| CPU time | 1.06 seconds |
| Started | Jun 04 12:44:38 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-2bca406e-5885-4e1c-8bb0-df6993bae3b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257265207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou tstanding.2257265207 |
| Directory | /workspace/1.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.i2c_tl_errors.716662237 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 124747380 ps |
| CPU time | 2.31 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-89f8bcb1-9a37-4b1c-8c9d-5fd003acba09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716662237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.716662237 |
| Directory | /workspace/1.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.930537330 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 27362068 ps |
| CPU time | 0.8 seconds |
| Started | Jun 04 12:44:51 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-b7e39a3e-3660-4760-a3b5-de0a56eb7fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930537330 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.930537330 |
| Directory | /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_csr_rw.513551660 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 45732964 ps |
| CPU time | 0.78 seconds |
| Started | Jun 04 12:44:51 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-e811412f-3495-4f9c-89c6-bcb02efd3e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513551660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.513551660 |
| Directory | /workspace/10.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_intr_test.433340750 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 16010089 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-cc5584f9-49e0-4311-a979-5bf8e2504c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433340750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.433340750 |
| Directory | /workspace/10.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3170678346 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 60008834 ps |
| CPU time | 0.88 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-f40e4f95-64f1-4dde-a30e-d40adbd8f424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170678346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o utstanding.3170678346 |
| Directory | /workspace/10.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1730873696 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 190285422 ps |
| CPU time | 2.21 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-39778564-9610-4c6d-8348-d580ff0d824f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730873696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1730873696 |
| Directory | /workspace/10.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1875088669 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 329311419 ps |
| CPU time | 2.05 seconds |
| Started | Jun 04 12:44:50 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-ac565fa5-f57f-4a71-ad54-58badf01a878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875088669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1875088669 |
| Directory | /workspace/10.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1177075030 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 41766363 ps |
| CPU time | 0.84 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-f02d916a-fc65-48bf-89c3-8c1c594fcb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177075030 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1177075030 |
| Directory | /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_csr_rw.645260249 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 107829584 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:53 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-8424df74-6516-44e5-936c-62a73fa99477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645260249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.645260249 |
| Directory | /workspace/11.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_intr_test.1104680566 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 44728593 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204244 kb |
| Host | smart-28e39f6f-2dde-4944-81ff-28537eef8271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104680566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1104680566 |
| Directory | /workspace/11.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.761195678 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 21319588 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-bbde9ba7-e551-4525-9d9a-c4586e02338a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761195678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou tstanding.761195678 |
| Directory | /workspace/11.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3345232781 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 216127744 ps |
| CPU time | 1.91 seconds |
| Started | Jun 04 12:44:57 PM PDT 24 |
| Finished | Jun 04 12:45:01 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-881f40f7-7098-41e8-b28d-0b9f87c16fdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345232781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3345232781 |
| Directory | /workspace/11.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1043113228 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 341449357 ps |
| CPU time | 1 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204104 kb |
| Host | smart-199cc2b9-6759-49c6-b6cd-b98afd29e4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043113228 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1043113228 |
| Directory | /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1507766695 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 89352721 ps |
| CPU time | 0.78 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-34bfa5d9-5baf-4682-b94d-d197b7d745d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507766695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1507766695 |
| Directory | /workspace/12.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_intr_test.2098346632 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 46035309 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-7e5ee9c4-8381-4023-93d2-5416660673ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098346632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2098346632 |
| Directory | /workspace/12.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1276809725 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49087397 ps |
| CPU time | 2.54 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-b9850645-65d4-42d3-8f36-2ead04680fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276809725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1276809725 |
| Directory | /workspace/12.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3873028283 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 37556488 ps |
| CPU time | 1.11 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-1f5fe10f-36fd-4021-9f74-917d89c56c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873028283 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3873028283 |
| Directory | /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_csr_rw.643301155 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 118282711 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-1592d677-3fec-4052-92e5-ed660363c7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643301155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.643301155 |
| Directory | /workspace/13.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_intr_test.4140489278 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 16110267 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-31d9bfb7-0b71-4a8c-b868-ce1090cff15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140489278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.4140489278 |
| Directory | /workspace/13.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1870817511 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 284218110 ps |
| CPU time | 2.72 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-f4fa1ea3-138d-4956-8a7d-39cdf619b7f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870817511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1870817511 |
| Directory | /workspace/13.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3753016916 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 139352008 ps |
| CPU time | 0.87 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:54 PM PDT 24 |
| Peak memory | 204312 kb |
| Host | smart-b8aed1d6-c4d1-4518-aec0-2d1878bf4eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753016916 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3753016916 |
| Directory | /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3704794651 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 22739337 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-26ddac9d-b0d6-4482-b24f-9fe0b0eb054a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704794651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3704794651 |
| Directory | /workspace/14.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_intr_test.1534683346 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 19032840 ps |
| CPU time | 0.75 seconds |
| Started | Jun 04 12:44:56 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-0711feac-cbab-4940-ae01-78ca9b2e526a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534683346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1534683346 |
| Directory | /workspace/14.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.408604367 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 151283727 ps |
| CPU time | 0.82 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-6c6f53f2-2122-472e-bdbc-cdefec200e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408604367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou tstanding.408604367 |
| Directory | /workspace/14.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3331801508 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 460480850 ps |
| CPU time | 2.19 seconds |
| Started | Jun 04 12:44:51 PM PDT 24 |
| Finished | Jun 04 12:44:54 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-cdf2ecfb-2309-4904-934a-1f75413d019b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331801508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3331801508 |
| Directory | /workspace/14.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3757735116 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 242755995 ps |
| CPU time | 1.52 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-b25da62e-6e11-4c96-aa09-a91bd81507c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757735116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3757735116 |
| Directory | /workspace/14.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1899319249 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 196744784 ps |
| CPU time | 1.02 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-6afceb74-9cb0-4a11-ae50-151081a60beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899319249 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1899319249 |
| Directory | /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1553491297 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 89406413 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-ae387394-788e-4443-8f13-18aa86f3a364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553491297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1553491297 |
| Directory | /workspace/15.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_intr_test.3493254238 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 15457849 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204276 kb |
| Host | smart-90ce38b8-a33f-4b69-964a-de392556ec49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493254238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3493254238 |
| Directory | /workspace/15.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1502675518 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 36314348 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-a51c9a1d-4015-4ff8-a3dc-60bd8ff500ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502675518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o utstanding.1502675518 |
| Directory | /workspace/15.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3171092572 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 74281152 ps |
| CPU time | 1.55 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-c6e8ee27-f99e-4767-9128-c30c14acf44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171092572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3171092572 |
| Directory | /workspace/15.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4006228166 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 31554680 ps |
| CPU time | 0.85 seconds |
| Started | Jun 04 12:44:56 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-5290674f-53de-48a5-929f-8a171bb44e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006228166 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4006228166 |
| Directory | /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2729001266 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 75053947 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-9ed504b4-d88a-48e1-b999-30b930e86344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729001266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2729001266 |
| Directory | /workspace/16.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_intr_test.3002231035 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 40561194 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:44:50 PM PDT 24 |
| Finished | Jun 04 12:44:51 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-9da5cdc1-d0ed-42f1-990c-fd7498aa6846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002231035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3002231035 |
| Directory | /workspace/16.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2354175355 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 157885644 ps |
| CPU time | 0.97 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-143c34e7-82e7-4fdc-9cf3-e05491744fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354175355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o utstanding.2354175355 |
| Directory | /workspace/16.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_errors.564418036 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 23870263 ps |
| CPU time | 1.06 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-bcbeb5c1-50e8-4c9d-baa1-59da5d138bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564418036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.564418036 |
| Directory | /workspace/16.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.644039616 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 132375744 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204640 kb |
| Host | smart-e1a2ade1-b9c1-456a-b020-2a311f1dceea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644039616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.644039616 |
| Directory | /workspace/16.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3937172180 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 33035726 ps |
| CPU time | 1.62 seconds |
| Started | Jun 04 12:45:10 PM PDT 24 |
| Finished | Jun 04 12:45:13 PM PDT 24 |
| Peak memory | 213116 kb |
| Host | smart-a9089c9f-fc12-4ace-8ad9-04846415b6c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937172180 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3937172180 |
| Directory | /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3543674746 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 55568313 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-3baa2dce-aec7-4adf-8101-8361efcc9102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543674746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3543674746 |
| Directory | /workspace/17.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_intr_test.1375096104 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 49104782 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:55 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-e2a74947-ecf6-4590-afa0-7db13775c653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375096104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1375096104 |
| Directory | /workspace/17.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.613309152 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 59583294 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 12:44:56 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204396 kb |
| Host | smart-50cc7ba5-2ed8-4edf-8891-969b1e3f781a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613309152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou tstanding.613309152 |
| Directory | /workspace/17.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2284920968 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 45006400 ps |
| CPU time | 2.17 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-175fd137-770a-4a4e-b331-a54bc52d831a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284920968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2284920968 |
| Directory | /workspace/17.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1506850105 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 427836867 ps |
| CPU time | 1.6 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:57 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-14676d4e-9d6d-4a28-82e3-8236afc9f06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506850105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1506850105 |
| Directory | /workspace/17.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4085922217 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 30672542 ps |
| CPU time | 1.25 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:07 PM PDT 24 |
| Peak memory | 212844 kb |
| Host | smart-e1ec6909-0293-4098-8e61-37b9d11a9a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085922217 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.4085922217 |
| Directory | /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_csr_rw.247066408 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29650779 ps |
| CPU time | 0.81 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-d95b784b-87d9-4940-aa56-0387b3833df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247066408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.247066408 |
| Directory | /workspace/18.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_intr_test.3805826995 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 17631069 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:07 PM PDT 24 |
| Peak memory | 204264 kb |
| Host | smart-bbb18983-9b99-46e4-bf26-ed3661a609f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805826995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3805826995 |
| Directory | /workspace/18.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2087959988 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 374055522 ps |
| CPU time | 2.22 seconds |
| Started | Jun 04 12:45:01 PM PDT 24 |
| Finished | Jun 04 12:45:04 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-4957ef88-2db0-476c-b5f5-6bbb49eeea1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087959988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2087959988 |
| Directory | /workspace/18.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2747768126 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 157420046 ps |
| CPU time | 2.31 seconds |
| Started | Jun 04 12:45:05 PM PDT 24 |
| Finished | Jun 04 12:45:09 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-c9ef6e62-9147-4df6-ab9c-d2d5e19cda2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747768126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2747768126 |
| Directory | /workspace/18.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2411325063 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 24418097 ps |
| CPU time | 1.1 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:10 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-d3e383b1-e8cb-40ce-94e1-3ef397e33c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411325063 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2411325063 |
| Directory | /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2354102508 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 17860603 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:10 PM PDT 24 |
| Peak memory | 204284 kb |
| Host | smart-819855a1-3090-4908-845c-09c6ad8e143d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354102508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2354102508 |
| Directory | /workspace/19.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_intr_test.1164107205 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 45337849 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204272 kb |
| Host | smart-bf2202c4-65f1-42c5-9a97-4d6feff7ef52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164107205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1164107205 |
| Directory | /workspace/19.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3174598423 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 172638359 ps |
| CPU time | 0.95 seconds |
| Started | Jun 04 12:45:06 PM PDT 24 |
| Finished | Jun 04 12:45:08 PM PDT 24 |
| Peak memory | 204352 kb |
| Host | smart-d8429963-6478-4e05-b837-801da929c153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174598423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o utstanding.3174598423 |
| Directory | /workspace/19.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_errors.657163118 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 99482898 ps |
| CPU time | 1.9 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:11 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-138fe235-a9d8-4fda-a064-df16f95cc0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657163118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.657163118 |
| Directory | /workspace/19.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3495420846 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 78506459 ps |
| CPU time | 1.45 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:10 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-819be715-b26e-4d07-b7f4-57d7f673fc1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495420846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3495420846 |
| Directory | /workspace/19.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3105831405 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 503872614 ps |
| CPU time | 1.4 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-d8231a18-1d91-4a0b-9e4e-889a1d4926d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105831405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3105831405 |
| Directory | /workspace/2.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.494651357 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 639737213 ps |
| CPU time | 3.57 seconds |
| Started | Jun 04 12:44:34 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-c8604b2a-51db-414d-8c32-80ba9d478e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494651357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.494651357 |
| Directory | /workspace/2.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2678744875 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 27281407 ps |
| CPU time | 0.78 seconds |
| Started | Jun 04 12:44:35 PM PDT 24 |
| Finished | Jun 04 12:44:37 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-364989da-89a5-420b-984b-b9dcd260b729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678744875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2678744875 |
| Directory | /workspace/2.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2696084599 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 29352523 ps |
| CPU time | 1.3 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-d7dbd583-c91a-497c-883b-a9651913a5ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696084599 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2696084599 |
| Directory | /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3351772752 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 22575426 ps |
| CPU time | 0.76 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-88e1f1f3-7462-417a-9727-1b881895de64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351772752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3351772752 |
| Directory | /workspace/2.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_intr_test.714413877 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 53270766 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204264 kb |
| Host | smart-9730df8c-f487-4529-b44c-3426200b6edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714413877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.714413877 |
| Directory | /workspace/2.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.692290844 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 246949614 ps |
| CPU time | 0.91 seconds |
| Started | Jun 04 12:44:40 PM PDT 24 |
| Finished | Jun 04 12:44:42 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-294330af-21c0-4e42-9420-57b0fb203cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692290844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out standing.692290844 |
| Directory | /workspace/2.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3008804627 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 239565035 ps |
| CPU time | 1.5 seconds |
| Started | Jun 04 12:44:36 PM PDT 24 |
| Finished | Jun 04 12:44:39 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-fdf00f0e-689c-474f-acd6-fafd47da29d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008804627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3008804627 |
| Directory | /workspace/2.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.i2c_intr_test.357015619 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 98396976 ps |
| CPU time | 0.76 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-9c2ccad8-615e-4788-ad94-ff56c5e16493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357015619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.357015619 |
| Directory | /workspace/20.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.i2c_intr_test.1580989141 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 27826210 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:09 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-5d4ca273-1d18-48f3-a640-3f5a4b5fe3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580989141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1580989141 |
| Directory | /workspace/21.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.i2c_intr_test.2401620305 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 37079898 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:45:01 PM PDT 24 |
| Finished | Jun 04 12:45:03 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-c959b6cf-c592-4bc9-aae3-6c5994b7e02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401620305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2401620305 |
| Directory | /workspace/22.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.i2c_intr_test.4038048226 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 35582446 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:45:02 PM PDT 24 |
| Finished | Jun 04 12:45:04 PM PDT 24 |
| Peak memory | 204284 kb |
| Host | smart-df922e46-b266-4ff1-bf22-97e7b9f074f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038048226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4038048226 |
| Directory | /workspace/23.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.i2c_intr_test.2172596770 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 17414347 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:45:09 PM PDT 24 |
| Finished | Jun 04 12:45:11 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-56b6798a-4a94-4a22-acd6-161a8cc42996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172596770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2172596770 |
| Directory | /workspace/24.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.i2c_intr_test.2833248663 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 51656372 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:45:05 PM PDT 24 |
| Finished | Jun 04 12:45:07 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-b6dc58b3-12d5-40a4-9025-5144bf7ea6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833248663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2833248663 |
| Directory | /workspace/25.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.i2c_intr_test.580677547 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 36441321 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:45:02 PM PDT 24 |
| Finished | Jun 04 12:45:03 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-386d7765-3c7c-428a-8a7c-388b3af07f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580677547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.580677547 |
| Directory | /workspace/26.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.i2c_intr_test.4106481982 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 56704284 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204188 kb |
| Host | smart-d92e4d02-772a-458e-a780-566c5f394e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106481982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.4106481982 |
| Directory | /workspace/27.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.i2c_intr_test.953227227 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 18205219 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204204 kb |
| Host | smart-93190887-8408-48b8-b80e-842fe63ca3ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953227227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.953227227 |
| Directory | /workspace/29.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4047984927 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 82799896 ps |
| CPU time | 2 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:48 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-5e0075ab-ef61-4f40-b465-fe2d5b2880ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047984927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4047984927 |
| Directory | /workspace/3.i2c_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1259580990 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1690370898 ps |
| CPU time | 5.99 seconds |
| Started | Jun 04 12:44:40 PM PDT 24 |
| Finished | Jun 04 12:44:47 PM PDT 24 |
| Peak memory | 204676 kb |
| Host | smart-392c867b-d7a4-44cf-9dcf-4530c81adc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259580990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1259580990 |
| Directory | /workspace/3.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2323662936 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 96678064 ps |
| CPU time | 0.8 seconds |
| Started | Jun 04 12:44:46 PM PDT 24 |
| Finished | Jun 04 12:44:48 PM PDT 24 |
| Peak memory | 204308 kb |
| Host | smart-9172de9a-a515-4e8e-b01c-7cf5e4294078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323662936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2323662936 |
| Directory | /workspace/3.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2038088883 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 441209755 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204672 kb |
| Host | smart-51278658-976a-49b5-8603-af6e5f544671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038088883 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2038088883 |
| Directory | /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2764525281 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 21009087 ps |
| CPU time | 0.78 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:43 PM PDT 24 |
| Peak memory | 204392 kb |
| Host | smart-1c198a95-70e2-4eb5-8600-2500cb9acf50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764525281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2764525281 |
| Directory | /workspace/3.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_intr_test.697235685 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 24659231 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-6bc8accd-124c-4117-a4c8-5ced02e7717d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697235685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.697235685 |
| Directory | /workspace/3.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1373055761 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 97523216 ps |
| CPU time | 1.16 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-36aa0da6-b910-4ac1-934d-701abb6ee96b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373055761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou tstanding.1373055761 |
| Directory | /workspace/3.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1662982358 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 147340166 ps |
| CPU time | 2.42 seconds |
| Started | Jun 04 12:44:40 PM PDT 24 |
| Finished | Jun 04 12:44:43 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-8492f76e-5e66-417e-a3aa-6bf829bb74b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662982358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1662982358 |
| Directory | /workspace/3.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.628310157 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 746329488 ps |
| CPU time | 2.36 seconds |
| Started | Jun 04 12:44:46 PM PDT 24 |
| Finished | Jun 04 12:44:49 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-d04d19f4-4a21-4414-8b64-ac94f5c4055a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628310157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.628310157 |
| Directory | /workspace/3.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/31.i2c_intr_test.1195283497 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 41197636 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:09 PM PDT 24 |
| Peak memory | 204292 kb |
| Host | smart-a4eef94f-6e01-4f25-a960-e3659d9148a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195283497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1195283497 |
| Directory | /workspace/31.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.i2c_intr_test.1125644911 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 56400016 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204360 kb |
| Host | smart-5f35d72d-7106-4b07-9e4a-08788157be3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125644911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1125644911 |
| Directory | /workspace/32.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.i2c_intr_test.2736641603 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 33850088 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204288 kb |
| Host | smart-f7b5722b-0d2a-488d-8d8f-3b1b42dd76ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736641603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2736641603 |
| Directory | /workspace/33.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.i2c_intr_test.1927775544 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 20000555 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 12:45:02 PM PDT 24 |
| Finished | Jun 04 12:45:03 PM PDT 24 |
| Peak memory | 204328 kb |
| Host | smart-67208178-c694-4e4a-bbf0-4ef369c339d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927775544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1927775544 |
| Directory | /workspace/34.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.i2c_intr_test.877610203 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 25213635 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:02 PM PDT 24 |
| Finished | Jun 04 12:45:04 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-7741d681-e840-4220-b4b9-143ccc997080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877610203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.877610203 |
| Directory | /workspace/35.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.i2c_intr_test.444267541 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 39040132 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204216 kb |
| Host | smart-a128144b-cc2f-4e47-b5ed-ddef60149c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444267541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.444267541 |
| Directory | /workspace/36.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.i2c_intr_test.1780415422 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 32274352 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-8e527272-7687-47ae-8a7c-8af7b782c650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780415422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1780415422 |
| Directory | /workspace/38.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.i2c_intr_test.652333033 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 18057290 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-662ad0ba-86b9-42ea-b63a-4417063555f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652333033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.652333033 |
| Directory | /workspace/39.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1555740002 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 992171974 ps |
| CPU time | 6.26 seconds |
| Started | Jun 04 12:44:37 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-7a185c4c-1da9-4e4b-85d5-8757fb834d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555740002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1555740002 |
| Directory | /workspace/4.i2c_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.957993322 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 41257904 ps |
| CPU time | 0.77 seconds |
| Started | Jun 04 12:44:38 PM PDT 24 |
| Finished | Jun 04 12:44:40 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-dfae5612-698d-4280-b099-a0033f7d1a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957993322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.957993322 |
| Directory | /workspace/4.i2c_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1466360322 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 36598167 ps |
| CPU time | 0.93 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204420 kb |
| Host | smart-63ebf96d-af90-4e1b-8d01-fc39d4a729d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466360322 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1466360322 |
| Directory | /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_csr_rw.734671907 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 36768749 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204252 kb |
| Host | smart-73226e74-7819-4d36-a8ad-d6d99e8bcc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734671907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.734671907 |
| Directory | /workspace/4.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_intr_test.575285173 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 56047787 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:46 PM PDT 24 |
| Finished | Jun 04 12:44:47 PM PDT 24 |
| Peak memory | 204324 kb |
| Host | smart-6253beb4-92e2-4e82-9e9a-ca40ad5f37f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575285173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.575285173 |
| Directory | /workspace/4.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2271735739 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 292857786 ps |
| CPU time | 1.53 seconds |
| Started | Jun 04 12:44:45 PM PDT 24 |
| Finished | Jun 04 12:44:47 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-4f6e037b-8c35-48c4-8260-77a3aae910f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271735739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2271735739 |
| Directory | /workspace/4.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/40.i2c_intr_test.3139549994 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 31515098 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-f74bf1fe-d6ae-4218-9dca-0bfc30452d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139549994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3139549994 |
| Directory | /workspace/40.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.i2c_intr_test.1632858782 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 22928033 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204216 kb |
| Host | smart-4aae2d48-0086-49fa-9bac-cc522bb4332d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632858782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1632858782 |
| Directory | /workspace/41.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.i2c_intr_test.178599970 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 48338733 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 12:45:08 PM PDT 24 |
| Finished | Jun 04 12:45:10 PM PDT 24 |
| Peak memory | 204348 kb |
| Host | smart-ee49ac23-d84f-4bd1-bb8e-f7e51f6f7cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178599970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.178599970 |
| Directory | /workspace/42.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.i2c_intr_test.1777047263 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 48046321 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:45:03 PM PDT 24 |
| Finished | Jun 04 12:45:05 PM PDT 24 |
| Peak memory | 204220 kb |
| Host | smart-11cbae12-d316-4b1a-818e-cb2344285ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777047263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1777047263 |
| Directory | /workspace/43.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.i2c_intr_test.909681591 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 16863278 ps |
| CPU time | 0.63 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204276 kb |
| Host | smart-4e5ab187-9b68-4e8d-a7f9-db2986a7e7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909681591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.909681591 |
| Directory | /workspace/44.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.i2c_intr_test.350642762 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 83072195 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-011a5b39-c28b-42b6-91ea-982a406c8130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350642762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.350642762 |
| Directory | /workspace/45.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.i2c_intr_test.2990878162 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 27729214 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204220 kb |
| Host | smart-0a732c1e-d72c-46fd-a299-9014ced458a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990878162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2990878162 |
| Directory | /workspace/46.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.i2c_intr_test.556614224 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 39246912 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 12:45:02 PM PDT 24 |
| Finished | Jun 04 12:45:03 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-acce0f57-0fb1-4c75-83ff-ab99c551ff41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556614224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.556614224 |
| Directory | /workspace/47.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.i2c_intr_test.3739598623 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 20722489 ps |
| CPU time | 0.76 seconds |
| Started | Jun 04 12:45:04 PM PDT 24 |
| Finished | Jun 04 12:45:06 PM PDT 24 |
| Peak memory | 204272 kb |
| Host | smart-419ac078-db40-40fc-b3a1-113fb574c59a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739598623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3739598623 |
| Directory | /workspace/48.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.i2c_intr_test.3702344204 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 22632792 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:45:10 PM PDT 24 |
| Finished | Jun 04 12:45:11 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-337ca5c4-232d-4881-81d4-299b2f9bd3e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702344204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3702344204 |
| Directory | /workspace/49.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.353143996 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 47185846 ps |
| CPU time | 0.84 seconds |
| Started | Jun 04 12:44:48 PM PDT 24 |
| Finished | Jun 04 12:44:50 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-112100d7-85fb-4924-a92d-633e69580764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353143996 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.353143996 |
| Directory | /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2897718158 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 399096193 ps |
| CPU time | 0.78 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-5e53a79f-ed25-4a8f-aeed-0429645e5445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897718158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2897718158 |
| Directory | /workspace/5.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_intr_test.484698598 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 24468974 ps |
| CPU time | 0.64 seconds |
| Started | Jun 04 12:44:40 PM PDT 24 |
| Finished | Jun 04 12:44:41 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-5d66b2a5-3209-44ec-96e4-d074b2df2281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484698598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.484698598 |
| Directory | /workspace/5.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3764718561 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 115704879 ps |
| CPU time | 2.53 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-fc98a2be-48fb-4359-bd19-dd90f77c162a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764718561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3764718561 |
| Directory | /workspace/5.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.381846672 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 50458839 ps |
| CPU time | 0.86 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-f06ea0ca-d05e-434e-9aae-91dd258b9002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381846672 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.381846672 |
| Directory | /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4190628796 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 375878212 ps |
| CPU time | 0.83 seconds |
| Started | Jun 04 12:44:40 PM PDT 24 |
| Finished | Jun 04 12:44:42 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-b710c6e0-0f74-43d5-a54b-3847de9dcbfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190628796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4190628796 |
| Directory | /workspace/6.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_intr_test.1721123376 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 43634636 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:48 PM PDT 24 |
| Finished | Jun 04 12:44:49 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-508e71f6-725f-47e5-b9ba-2b78385f4577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721123376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1721123376 |
| Directory | /workspace/6.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4156306356 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 70316082 ps |
| CPU time | 1.16 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-6ed81a07-e0b0-40d1-9f8b-b42a574560f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156306356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou tstanding.4156306356 |
| Directory | /workspace/6.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2658777692 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 88444374 ps |
| CPU time | 2.41 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:47 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-c134b76c-2dbd-488e-a9cc-c3f820fddbb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658777692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2658777692 |
| Directory | /workspace/6.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2790296068 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 604156481 ps |
| CPU time | 2.4 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:44 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-4779e2e9-d8c1-43a9-bccf-7a7491ff752a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790296068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2790296068 |
| Directory | /workspace/6.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2480210888 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 198222325 ps |
| CPU time | 1.14 seconds |
| Started | Jun 04 12:44:46 PM PDT 24 |
| Finished | Jun 04 12:44:48 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-36296dbd-28e4-4e26-87dd-8044d7bbb51f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480210888 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2480210888 |
| Directory | /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_csr_rw.511769106 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 21236306 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204356 kb |
| Host | smart-5351350f-8e8f-481f-929d-5b30a2134262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511769106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.511769106 |
| Directory | /workspace/7.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_intr_test.298605835 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 18005631 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-3872442c-1099-4ff0-b18a-0c9fb62489bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298605835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.298605835 |
| Directory | /workspace/7.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1533970727 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 55725062 ps |
| CPU time | 1.22 seconds |
| Started | Jun 04 12:44:44 PM PDT 24 |
| Finished | Jun 04 12:44:46 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-067c9032-732b-4ff4-a68f-d9a266b1f5a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533970727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou tstanding.1533970727 |
| Directory | /workspace/7.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_errors.17541723 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 43352129 ps |
| CPU time | 1.2 seconds |
| Started | Jun 04 12:44:41 PM PDT 24 |
| Finished | Jun 04 12:44:43 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-911a2c26-4716-40a1-928a-a95e56df37cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.17541723 |
| Directory | /workspace/7.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2412814166 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 74990214 ps |
| CPU time | 1.7 seconds |
| Started | Jun 04 12:44:42 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-2aa9713e-4985-4661-861a-bab76bc11a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412814166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2412814166 |
| Directory | /workspace/7.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2082415048 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 241401434 ps |
| CPU time | 1.05 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204700 kb |
| Host | smart-ae974528-d790-4dfa-bb83-d21adbc53d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082415048 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2082415048 |
| Directory | /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3367759005 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 51555705 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 12:44:49 PM PDT 24 |
| Finished | Jun 04 12:44:51 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-0890f713-484c-4e28-9e28-af32d7080833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367759005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3367759005 |
| Directory | /workspace/8.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.819745596 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 35421207 ps |
| CPU time | 0.94 seconds |
| Started | Jun 04 12:44:54 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204344 kb |
| Host | smart-6e88cff1-69b6-455c-afff-ee6b5377b31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819745596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out standing.819745596 |
| Directory | /workspace/8.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1022152658 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 140558764 ps |
| CPU time | 2.06 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 203316 kb |
| Host | smart-31c011f5-f741-4a50-9f4c-c9460e55e9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022152658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1022152658 |
| Directory | /workspace/8.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2663089069 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 89582050 ps |
| CPU time | 1.57 seconds |
| Started | Jun 04 12:44:43 PM PDT 24 |
| Finished | Jun 04 12:44:45 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-73409388-dfad-4165-b21e-969217a4ac7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663089069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2663089069 |
| Directory | /workspace/8.i2c_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2133604071 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 68644194 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-e9e30bb3-3481-4747-a91c-ddfb61f71811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133604071 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2133604071 |
| Directory | /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2105248936 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 121246624 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 12:44:55 PM PDT 24 |
| Finished | Jun 04 12:44:58 PM PDT 24 |
| Peak memory | 204304 kb |
| Host | smart-250fb56e-c3a7-4432-b1a0-8392916663f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105248936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2105248936 |
| Directory | /workspace/9.i2c_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_intr_test.3250073227 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 22392446 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 12:44:53 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204316 kb |
| Host | smart-8e415cc1-cb8b-46ed-8ece-b403f2968c2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250073227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3250073227 |
| Directory | /workspace/9.i2c_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1908228457 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 73637334 ps |
| CPU time | 1.3 seconds |
| Started | Jun 04 12:44:56 PM PDT 24 |
| Finished | Jun 04 12:44:59 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-d723d8c4-f6d6-419f-a1a6-0eb638cb126c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908228457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou tstanding.1908228457 |
| Directory | /workspace/9.i2c_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1472465953 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 225371965 ps |
| CPU time | 2.06 seconds |
| Started | Jun 04 12:44:57 PM PDT 24 |
| Finished | Jun 04 12:45:01 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-b3581e67-6baf-4999-9c1f-57255e8f4504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472465953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1472465953 |
| Directory | /workspace/9.i2c_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2585298043 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 306134100 ps |
| CPU time | 2.27 seconds |
| Started | Jun 04 12:44:52 PM PDT 24 |
| Finished | Jun 04 12:44:56 PM PDT 24 |
| Peak memory | 204668 kb |
| Host | smart-2ed3c0c1-fa82-4be1-b081-94d411fe6422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585298043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2585298043 |
| Directory | /workspace/9.i2c_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |