Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	351	1			T1	1		T3	5		T6	1
all_pins[1]	351	1			T1	1		T3	5		T6	1
all_pins[2]	351	1			T1	1		T3	5		T6	1
all_pins[3]	351	1			T1	1		T3	5		T6	1
all_pins[4]	351	1			T1	1		T3	5		T6	1
all_pins[5]	351	1			T1	1		T3	5		T6	1
all_pins[6]	351	1			T1	1		T3	5		T6	1
all_pins[7]	351	1			T1	1		T3	5		T6	1
all_pins[8]	351	1			T1	1		T3	5		T6	1
all_pins[9]	351	1			T1	1		T3	5		T6	1
all_pins[10]	351	1			T1	1		T3	5		T6	1
all_pins[11]	351	1			T1	1		T3	5		T6	1
all_pins[12]	351	1			T1	1		T3	5		T6	1
all_pins[13]	351	1			T1	1		T3	5		T6	1
all_pins[14]	351	1			T1	1		T3	5		T6	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4286	1			T1	15		T3	61		T6	15
values[0x1]	979	1			T3	14		T7	21		T8	11
transitions[0x0=>0x1]	724	1			T3	11		T7	12		T8	9
transitions[0x1=>0x0]	734	1			T3	11		T7	12		T8	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289	1			T1	1		T3	4		T6	1
all_pins[0]	values[0x1]	62	1			T3	1		T54	1		T55	2
all_pins[0]	transitions[0x0=>0x1]	47	1			T3	1		T54	1		T55	1
all_pins[0]	transitions[0x1=>0x0]	52	1			T7	3		T8	1		T9	2
all_pins[1]	values[0x0]	284	1			T1	1		T3	5		T6	1
all_pins[1]	values[0x1]	67	1			T7	3		T8	1		T9	2
all_pins[1]	transitions[0x0=>0x1]	52	1			T7	2		T8	1		T9	1
all_pins[1]	transitions[0x1=>0x0]	34	1			T3	2		T17	1		T55	2
all_pins[2]	values[0x0]	302	1			T1	1		T3	3		T6	1
all_pins[2]	values[0x1]	49	1			T3	2		T7	1		T9	1
all_pins[2]	transitions[0x0=>0x1]	41	1			T3	2		T7	1		T9	1
all_pins[2]	transitions[0x1=>0x0]	57	1			T8	2		T9	3		T17	1
all_pins[3]	values[0x0]	286	1			T1	1		T3	5		T6	1
all_pins[3]	values[0x1]	65	1			T8	2		T9	3		T17	1
all_pins[3]	transitions[0x0=>0x1]	47	1			T8	2		T9	3		T17	1
all_pins[3]	transitions[0x1=>0x0]	43	1			T7	1		T17	3		T54	1
all_pins[4]	values[0x0]	290	1			T1	1		T3	5		T6	1
all_pins[4]	values[0x1]	61	1			T7	1		T17	3		T54	1
all_pins[4]	transitions[0x0=>0x1]	52	1			T17	2		T54	1		T55	1
all_pins[4]	transitions[0x1=>0x0]	42	1			T3	1		T9	4		T17	1
all_pins[5]	values[0x0]	300	1			T1	1		T3	4		T6	1
all_pins[5]	values[0x1]	51	1			T3	1		T7	1		T9	4
all_pins[5]	transitions[0x0=>0x1]	32	1			T9	2		T17	1		T30	1
all_pins[5]	transitions[0x1=>0x0]	52	1			T3	2		T7	1		T9	1
all_pins[6]	values[0x0]	280	1			T1	1		T3	2		T6	1
all_pins[6]	values[0x1]	71	1			T3	3		T7	2		T9	3
all_pins[6]	transitions[0x0=>0x1]	47	1			T3	3		T7	1		T9	1
all_pins[6]	transitions[0x1=>0x0]	62	1			T3	1		T7	3		T8	1
all_pins[7]	values[0x0]	265	1			T1	1		T3	4		T6	1
all_pins[7]	values[0x1]	86	1			T3	1		T7	4		T8	1
all_pins[7]	transitions[0x0=>0x1]	60	1			T3	1		T7	3		T8	1
all_pins[7]	transitions[0x1=>0x0]	41	1			T8	2		T17	3		T55	1
all_pins[8]	values[0x0]	284	1			T1	1		T3	5		T6	1
all_pins[8]	values[0x1]	67	1			T7	1		T8	2		T9	2
all_pins[8]	transitions[0x0=>0x1]	51	1			T7	1		T17	2		T55	3
all_pins[8]	transitions[0x1=>0x0]	59	1			T3	1		T7	1		T9	2
all_pins[9]	values[0x0]	276	1			T1	1		T3	4		T6	1
all_pins[9]	values[0x1]	75	1			T3	1		T7	1		T8	2
all_pins[9]	transitions[0x0=>0x1]	54	1			T8	2		T9	1		T17	2
all_pins[9]	transitions[0x1=>0x0]	53	1			T7	2		T9	2		T17	1
all_pins[10]	values[0x0]	277	1			T1	1		T3	4		T6	1
all_pins[10]	values[0x1]	74	1			T3	1		T7	3		T9	5
all_pins[10]	transitions[0x0=>0x1]	52	1			T7	1		T9	3		T17	1
all_pins[10]	transitions[0x1=>0x0]	45	1			T8	1		T9	1		T17	3
all_pins[11]	values[0x0]	284	1			T1	1		T3	4		T6	1
all_pins[11]	values[0x1]	67	1			T3	1		T7	2		T8	1
all_pins[11]	transitions[0x0=>0x1]	52	1			T3	1		T7	1		T8	1
all_pins[11]	transitions[0x1=>0x0]	45	1			T3	1		T9	1		T17	2
all_pins[12]	values[0x0]	291	1			T1	1		T3	4		T6	1
all_pins[12]	values[0x1]	60	1			T3	1		T7	1		T9	1
all_pins[12]	transitions[0x0=>0x1]	47	1			T3	1		T7	1		T9	1
all_pins[12]	transitions[0x1=>0x0]	41	1			T3	1		T9	3		T54	1
all_pins[13]	values[0x0]	297	1			T1	1		T3	4		T6	1
all_pins[13]	values[0x1]	54	1			T3	1		T9	3		T54	2
all_pins[13]	transitions[0x0=>0x1]	45	1			T3	1		T9	3		T54	2
all_pins[13]	transitions[0x1=>0x0]	61	1			T3	1		T7	1		T8	2
all_pins[14]	values[0x0]	281	1			T1	1		T3	4		T6	1
all_pins[14]	values[0x1]	70	1			T3	1		T7	1		T8	2
all_pins[14]	transitions[0x0=>0x1]	45	1			T3	1		T7	1		T8	2
all_pins[14]	transitions[0x1=>0x0]	47	1			T3	1		T54	1		T55	2