Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T3	4		T7	7		T8	4
all_values[1]	281	1			T3	4		T7	7		T8	4
all_values[2]	281	1			T3	4		T7	7		T8	4
all_values[3]	281	1			T3	4		T7	7		T8	4
all_values[4]	281	1			T3	4		T7	7		T8	4
all_values[5]	281	1			T3	4		T7	7		T8	4
all_values[6]	281	1			T3	4		T7	7		T8	4
all_values[7]	281	1			T3	4		T7	7		T8	4
all_values[8]	281	1			T3	4		T7	7		T8	4
all_values[9]	281	1			T3	4		T7	7		T8	4
all_values[10]	281	1			T3	4		T7	7		T8	4
all_values[11]	281	1			T3	4		T7	7		T8	4
all_values[12]	281	1			T3	4		T7	7		T8	4
all_values[13]	281	1			T3	4		T7	7		T8	4
all_values[14]	281	1			T3	4		T7	7		T8	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2319

1

T3

25

T7

63

T8

35

auto[1]

1896

1

T3

35

T7

42

T8

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

788

1

T3

7

T7

23

T8

23

auto[1]

3427

1

T3

53

T7

82

T8

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T3

37

T7

61

T8

40

auto[1]

1742

1

T3

23

T7

44

T8

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	38	1			T3	1		T8	2		T9	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T7	5		T8	1		T9	4
all_values[0]	auto[0]	auto[1]	auto[0]	15	1			T17	2		T72	1		T73	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T3	1		T54	1		T55	1
all_values[0]	auto[1]	auto[0]	auto[1]	64	1			T3	1		T7	2		T8	1
all_values[0]	auto[1]	auto[1]	auto[1]	52	1			T3	1		T17	1		T54	1
all_values[1]	auto[0]	auto[0]	auto[0]	25	1			T8	1		T9	1		T58	1
all_values[1]	auto[0]	auto[0]	auto[1]	59	1			T3	1		T7	2		T55	2
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T58	3		T33	1		T50	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T3	1		T7	1		T8	2
all_values[1]	auto[1]	auto[0]	auto[1]	64	1			T3	2		T7	1		T9	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1			T7	3		T8	1		T9	1
all_values[2]	auto[0]	auto[0]	auto[0]	47	1			T7	3		T8	4		T9	1
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T7	2		T9	2		T17	2
all_values[2]	auto[0]	auto[1]	auto[0]	15	1			T72	1		T74	1		T75	1
all_values[2]	auto[0]	auto[1]	auto[1]	37	1			T3	2		T17	2		T54	1
all_values[2]	auto[1]	auto[0]	auto[1]	62	1			T9	2		T17	1		T54	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T3	2		T7	2		T9	2
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T3	4		T7	1		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	52	1			T7	1		T54	2		T58	3
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T7	2		T76	2		T74	2
all_values[3]	auto[0]	auto[1]	auto[1]	57	1			T8	2		T9	2		T17	3
all_values[3]	auto[1]	auto[0]	auto[1]	76	1			T7	3		T8	1		T9	4
all_values[3]	auto[1]	auto[1]	auto[1]	40	1			T8	1		T9	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T7	2		T9	2		T54	1
all_values[4]	auto[0]	auto[0]	auto[1]	39	1			T3	2		T8	1		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	26	1			T7	2		T9	1		T54	1
all_values[4]	auto[0]	auto[1]	auto[1]	64	1			T3	1		T7	2		T8	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1			T3	1		T7	1		T8	2
all_values[4]	auto[1]	auto[1]	auto[1]	54	1			T17	3		T30	1		T31	1
all_values[5]	auto[0]	auto[0]	auto[0]	34	1			T7	1		T8	1		T9	1
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T17	1		T54	1		T55	4
all_values[5]	auto[0]	auto[1]	auto[0]	18	1			T8	3		T9	2		T50	4
all_values[5]	auto[0]	auto[1]	auto[1]	52	1			T3	2		T7	2		T9	2
all_values[5]	auto[1]	auto[0]	auto[1]	58	1			T3	1		T7	4		T17	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1			T3	1		T9	2		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T7	1		T9	1		T17	2
all_values[6]	auto[0]	auto[0]	auto[1]	51	1			T7	1		T8	1		T9	1
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T54	1		T55	1		T47	3
all_values[6]	auto[0]	auto[1]	auto[1]	60	1			T3	1		T7	2		T9	2
all_values[6]	auto[1]	auto[0]	auto[1]	73	1			T7	3		T8	3		T9	1
all_values[6]	auto[1]	auto[1]	auto[1]	38	1			T3	3		T9	2		T17	1
all_values[7]	auto[0]	auto[0]	auto[0]	37	1			T3	1		T7	1		T54	2
all_values[7]	auto[0]	auto[0]	auto[1]	46	1			T3	1		T8	3		T9	3
all_values[7]	auto[0]	auto[1]	auto[0]	5	1			T54	2		T30	1		T77	1
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T7	3		T9	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	65	1			T3	1		T7	3		T8	1
all_values[7]	auto[1]	auto[1]	auto[1]	58	1			T3	1		T9	2		T17	1
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T3	1		T8	1		T9	5
all_values[8]	auto[0]	auto[0]	auto[1]	59	1			T3	2		T7	1		T17	2
all_values[8]	auto[0]	auto[1]	auto[0]	10	1			T7	3		T8	1		T73	1
all_values[8]	auto[0]	auto[1]	auto[1]	57	1			T8	1		T9	1		T17	3
all_values[8]	auto[1]	auto[0]	auto[1]	60	1			T3	1		T7	3		T58	2
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T8	1		T9	1		T17	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T9	1		T54	3		T58	1
all_values[9]	auto[0]	auto[0]	auto[1]	44	1			T7	1		T9	1		T17	1
all_values[9]	auto[0]	auto[1]	auto[0]	22	1			T7	1		T17	1		T54	1
all_values[9]	auto[0]	auto[1]	auto[1]	63	1			T3	3		T8	1		T9	1
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T7	2		T8	2		T17	1
all_values[9]	auto[1]	auto[1]	auto[1]	57	1			T3	1		T7	3		T8	1
all_values[10]	auto[0]	auto[0]	auto[0]	15	1			T50	1		T51	2		T72	1
all_values[10]	auto[0]	auto[0]	auto[1]	56	1			T3	1		T17	3		T54	1
all_values[10]	auto[0]	auto[1]	auto[0]	12	1			T7	2		T55	1		T47	4
all_values[10]	auto[0]	auto[1]	auto[1]	68	1			T3	2		T7	2		T8	2
all_values[10]	auto[1]	auto[0]	auto[1]	76	1			T8	2		T9	1		T17	2
all_values[10]	auto[1]	auto[1]	auto[1]	54	1			T3	1		T7	3		T9	4
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T7	1		T8	1		T55	2
all_values[11]	auto[0]	auto[0]	auto[1]	41	1			T7	2		T8	1		T54	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T50	1		T78	1		T79	1
all_values[11]	auto[0]	auto[1]	auto[1]	67	1			T3	3		T7	1		T9	2
all_values[11]	auto[1]	auto[0]	auto[1]	64	1			T7	1		T8	1		T9	2
all_values[11]	auto[1]	auto[1]	auto[1]	55	1			T3	1		T7	2		T8	1
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T8	2		T9	2		T54	2
all_values[12]	auto[0]	auto[0]	auto[1]	56	1			T3	2		T7	4		T9	2
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T8	2		T55	1		T31	1
all_values[12]	auto[0]	auto[1]	auto[1]	52	1			T9	2		T17	1		T54	1
all_values[12]	auto[1]	auto[0]	auto[1]	67	1			T3	1		T7	2		T9	1
all_values[12]	auto[1]	auto[1]	auto[1]	48	1			T3	1		T7	1		T17	2
all_values[13]	auto[0]	auto[0]	auto[0]	44	1			T7	2		T8	1		T9	2
all_values[13]	auto[0]	auto[0]	auto[1]	59	1			T7	3		T17	4		T55	2
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T8	3		T9	1		T73	1
all_values[13]	auto[0]	auto[1]	auto[1]	41	1			T3	3		T9	1		T54	1
all_values[13]	auto[1]	auto[0]	auto[1]	59	1			T7	2		T17	2		T55	3
all_values[13]	auto[1]	auto[1]	auto[1]	50	1			T3	1		T9	3		T54	1
all_values[14]	auto[0]	auto[0]	auto[0]	25	1			T8	1		T9	1		T54	1
all_values[14]	auto[0]	auto[0]	auto[1]	59	1			T7	2		T9	4		T17	2
all_values[14]	auto[0]	auto[1]	auto[0]	14	1			T7	1		T54	1		T51	1
all_values[14]	auto[0]	auto[1]	auto[1]	59	1			T3	2		T7	1		T8	1
all_values[14]	auto[1]	auto[0]	auto[1]	62	1			T3	1		T8	1		T9	1
all_values[14]	auto[1]	auto[1]	auto[1]	62	1			T3	1		T7	3		T8	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal