Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fmt_fifo_cg

Group : i2c_env_pkg::i2c_fmt_fifo_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.30	96.30	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
i2c_env_pkg.fmt_fifo_cg	96.30	1	100	1	64	64

---

Group Instance : i2c_env_pkg.fmt_fifo_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

---

Summary for Group Instance i2c_env_pkg.fmt_fifo_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	27	2	25	92.59

Variables for Group Instance i2c_env_pkg.fmt_fifo_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ack	2	0	2	100.00	100	1	1	0
cp_fbyte	5	0	5	100.00	100	1	1	0
cp_nakok	2	0	2	100.00	100	1	1	2
cp_rcont	2	0	2	100.00	100	1	1	2
cp_read	2	0	2	100.00	100	1	1	2
cp_start	2	0	2	100.00	100	1	1	2
cp_stop	2	0	2	100.00	100	1	1	2
nakok	2	0	2	100.00	100	1	1	2
rcont	2	0	2	100.00	100	1	1	2
read	2	0	2	100.00	100	1	1	2
start	2	0	2	100.00	100	1	1	2
stop	2	0	2	100.00	100	1	1	2

Crosses for Group Instance i2c_env_pkg.fmt_fifo_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack	27	2	25	92.59	100	1	1	0

Summary for Variable cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_ack

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

nack

163010

1

T4

108

T7

95

T8

431

ack

14489

1

T3

28

T4

24

T5

43

---

Summary for Variable cp_fbyte

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_fbyte

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_ones	625	1			T3	1		T7	1		T8	3
high	36361	1			T4	35		T7	31		T8	88
med	65939	1			T3	3		T4	50		T5	6
sml	73888	1			T3	24		T4	46		T5	37
all_zero	686	1			T4	1		T8	2		T39	1

---

Summary for Variable cp_nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88393

1

T3

16

T4

66

T5

14

auto[1]

89106

1

T3

12

T4

66

T5

29

---

Summary for Variable cp_rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121669

1

T3

17

T4

98

T5

31

auto[1]

55830

1

T3

11

T4

34

T5

12

---

Summary for Variable cp_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169779

1

T3

9

T4

122

T5

16

auto[1]

7720

1

T3

19

T4

10

T5

27

---

Summary for Variable cp_start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167688

1

T3

19

T4

111

T5

27

auto[1]

9811

1

T3

9

T4

21

T5

16

---

Summary for Variable cp_stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168658

1

T3

20

T4

112

T5

28

auto[1]

8841

1

T3

8

T4

20

T5

15

---

Summary for Variable nakok

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for nakok

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88393

1

T3

16

T4

66

T5

14

auto[1]

89106

1

T3

12

T4

66

T5

29

---

Summary for Variable rcont

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rcont

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

121669

1

T3

17

T4

98

T5

31

auto[1]

55830

1

T3

11

T4

34

T5

12

---

Summary for Variable read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169779

1

T3

9

T4

122

T5

16

auto[1]

7720

1

T3

19

T4

10

T5

27

---

Summary for Variable start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for start

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167688

1

T3

19

T4

111

T5

27

auto[1]

9811

1

T3

9

T4

21

T5

16

---

Summary for Variable stop

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for stop

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168658

1

T3

20

T4

112

T5

28

auto[1]

8841

1

T3

8

T4

20

T5

15

---

Summary for Cross cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Samples crossed: cp_fbyte start stop read rcont nakok cp_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	27	2	25	92.59
Automatically Generated Cross Bins	15	0	15	100.00
User Defined Cross Bins	12	2	10	83.33

Automatically Generated Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Bins

cp_fbyte

start

stop

read

rcont

nakok

cp_ack

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_ones

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

4

1

T47

1

T267

1

T126

1

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

2

1

T84

1

T268

1

-

-

all_ones

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

4

1

T81

1

T269

1

T270

1

high

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

317

1

T4

2

T117

2

T118

2

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

116

1

T46

1

T183

2

T271

1

high

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

121

1

T9

1

T118

1

T183

1

med

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

526

1

T4

1

T81

2

T117

1

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

249

1

T4

1

T8

1

T81

5

med

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

280

1

T4

4

T8

1

T81

1

sml

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

542

1

T4

1

T8

1

T39

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

235

1

T8

1

T81

3

T117

1

sml

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

275

1

T81

3

T183

2

T272

4

all_zero

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

ack

7

1

T110

1

T273

1

T115

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

ack

4

1

T274

1

T275

1

T276

1

all_zero

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

ack

2

1

T277

1

T278

1

-

-

User Defined Cross Bins for cp_fbyte_X_start_X_stop_X_read_X_rcont_X_nakok_X_ack

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
read_address_byte	0	1	1
stop_after_start	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
data_byte	51828	1			T4	34		T7	23		T8	149
write_address_byte	9811	1			T3	9		T4	21		T5	16
read_with_ack	2305	1			T3	11		T5	12		T8	4
read_with_nack	5415	1			T3	8		T4	10		T5	15
stop_byte	8841	1			T3	8		T4	20		T5	15
write_address_byte_nak	4845	1			T4	16		T8	9		T9	4
data_byte_nack	163010	1			T4	108		T7	95		T8	431
stop_byte_nack	5250	1			T4	16		T7	13		T8	6
nakok_byte_nack	81738	1			T4	50		T7	51		T8	200
nakok_addr_byte_nack	2408	1			T4	8		T8	6		T9	2