Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_i2c_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39958591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10140876

1

T1

330

T2

2794

T3

13963

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49165825	1			T1	21398		T2	5584		T3	53343
values[0x0]	466693	1			T1	149		T2	10		T3	323
values[0x1]	466949	1			T1	175		T2	7		T3	322

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28552251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21547216

1

T1

9333

T2

3328

T3

25472

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	184350	1			T2	38		T3	504		T4	15
valid_sources[0x01]	183634	1			T2	19		T3	7		T4	30
valid_sources[0x02]	193491	1			T2	23		T3	1		T4	44
valid_sources[0x03]	182978	1			T2	23		T3	3		T4	43
valid_sources[0x04]	186728	1			T2	30		T3	502		T4	34
valid_sources[0x05]	210733	1			T2	20		T3	504		T4	48
valid_sources[0x06]	198825	1			T2	18		T3	2		T4	38
valid_sources[0x07]	179684	1			T2	22		T3	1523		T4	35
valid_sources[0x08]	182140	1			T2	18		T3	2		T4	33
valid_sources[0x09]	186111	1			T2	21		T3	498		T4	39
valid_sources[0x0a]	188367	1			T2	16		T3	5		T4	29
valid_sources[0x0b]	187797	1			T2	23		T3	10		T4	44
valid_sources[0x0c]	220387	1			T2	38		T3	524		T4	37
valid_sources[0x0d]	181738	1			T2	26		T3	7		T4	42
valid_sources[0x0e]	185403	1			T2	22		T3	490		T4	26
valid_sources[0x0f]	197553	1			T2	23		T3	503		T4	38
valid_sources[0x10]	179766	1			T2	18		T3	494		T4	38
valid_sources[0x11]	186187	1			T2	16		T3	511		T4	40
valid_sources[0x12]	206403	1			T2	14		T3	11		T4	37
valid_sources[0x13]	182426	1			T2	13		T3	2		T4	36
valid_sources[0x14]	275859	1			T2	21		T3	4		T4	40
valid_sources[0x15]	179037	1			T2	19		T3	6		T4	29
valid_sources[0x16]	210469	1			T2	28		T3	11		T4	29
valid_sources[0x17]	171851	1			T2	18		T3	1015		T4	40
valid_sources[0x18]	174942	1			T2	21		T3	3		T4	42
valid_sources[0x19]	203762	1			T2	24		T3	1001		T4	36
valid_sources[0x1a]	198462	1			T2	14		T3	491		T4	27
valid_sources[0x1b]	178586	1			T2	23		T3	13		T4	37
valid_sources[0x1c]	191637	1			T2	21		T3	5		T4	41
valid_sources[0x1d]	188657	1			T2	24		T3	500		T4	28
valid_sources[0x1e]	190904	1			T2	21		T3	519		T4	45
valid_sources[0x1f]	179580	1			T2	28		T3	1		T4	36
valid_sources[0x20]	215659	1			T2	15		T3	507		T4	37
valid_sources[0x21]	180690	1			T2	18		T3	507		T4	27
valid_sources[0x22]	208744	1			T2	20		T3	513		T4	28
valid_sources[0x23]	189198	1			T2	19		T3	3		T4	34
valid_sources[0x24]	278386	1			T2	17		T3	2		T4	50
valid_sources[0x25]	182861	1			T2	36		T3	3		T4	28
valid_sources[0x26]	170309	1			T2	15		T3	500		T4	31
valid_sources[0x27]	206736	1			T2	34		T3	2		T4	45
valid_sources[0x28]	189036	1			T2	20		T3	511		T4	38
valid_sources[0x29]	182124	1			T2	16		T3	4		T4	45
valid_sources[0x2a]	209537	1			T2	11		T3	7		T4	36
valid_sources[0x2b]	175794	1			T2	15		T3	2		T4	43
valid_sources[0x2c]	188442	1			T2	26		T3	503		T4	24
valid_sources[0x2d]	174665	1			T2	20		T3	7		T4	31
valid_sources[0x2e]	186273	1			T2	20		T3	3		T4	39
valid_sources[0x2f]	334917	1			T2	22		T3	1		T4	38
valid_sources[0x30]	179855	1			T2	20		T3	10		T4	26
valid_sources[0x31]	194790	1			T2	26		T4	42		T5	444
valid_sources[0x32]	185430	1			T2	20		T3	4		T4	37
valid_sources[0x33]	195670	1			T2	25		T3	502		T4	36
valid_sources[0x34]	176120	1			T2	25		T3	506		T4	35
valid_sources[0x35]	307062	1			T2	31		T3	11		T4	38
valid_sources[0x36]	176513	1			T2	11		T3	509		T4	35
valid_sources[0x37]	168517	1			T2	25		T3	503		T4	21
valid_sources[0x38]	188154	1			T2	16		T3	2		T4	34
valid_sources[0x39]	186548	1			T2	9		T3	11		T4	42
valid_sources[0x3a]	180071	1			T2	14		T3	492		T4	30
valid_sources[0x3b]	207818	1			T1	64		T2	6		T3	2
valid_sources[0x3c]	288208	1			T2	17		T3	4		T4	34
valid_sources[0x3d]	189570	1			T2	15		T3	502		T4	39
valid_sources[0x3e]	177072	1			T2	29		T3	481		T4	35
valid_sources[0x3f]	172285	1			T2	15		T3	2		T4	45
valid_sources[0x40]	181125	1			T2	21		T3	507		T4	33
valid_sources[0x41]	206613	1			T2	23		T3	13		T4	32
valid_sources[0x42]	195098	1			T1	9338		T2	33		T3	7
valid_sources[0x43]	184387	1			T2	25		T3	3		T4	46
valid_sources[0x44]	184662	1			T2	17		T3	11		T4	31
valid_sources[0x45]	193750	1			T2	12		T3	1		T4	50
valid_sources[0x46]	175507	1			T2	28		T3	1008		T4	33
valid_sources[0x47]	186896	1			T2	26		T3	501		T4	33
valid_sources[0x48]	188831	1			T2	27		T3	502		T4	37
valid_sources[0x49]	180087	1			T2	24		T3	5		T4	44
valid_sources[0x4a]	220288	1			T2	34		T3	499		T4	36
valid_sources[0x4b]	191762	1			T2	13		T3	501		T4	34
valid_sources[0x4c]	196014	1			T2	23		T3	5		T4	37
valid_sources[0x4d]	173829	1			T2	27		T3	3		T4	28
valid_sources[0x4e]	176399	1			T2	13		T3	3		T4	30
valid_sources[0x4f]	234229	1			T2	30		T3	516		T4	32
valid_sources[0x50]	186244	1			T2	25		T3	4		T4	29
valid_sources[0x51]	190353	1			T2	20		T3	4		T4	30
valid_sources[0x52]	186849	1			T2	10		T3	5		T4	41
valid_sources[0x53]	173289	1			T2	16		T3	4		T4	38
valid_sources[0x54]	180855	1			T2	25		T3	20		T4	34
valid_sources[0x55]	180846	1			T2	16		T3	2		T4	35
valid_sources[0x56]	187361	1			T2	19		T3	13		T4	44
valid_sources[0x57]	177769	1			T2	19		T3	13		T4	27
valid_sources[0x58]	183553	1			T2	39		T3	1		T4	29
valid_sources[0x59]	191809	1			T2	23		T3	2		T4	34
valid_sources[0x5a]	174822	1			T2	29		T3	9		T4	51
valid_sources[0x5b]	190573	1			T2	28		T3	520		T4	26
valid_sources[0x5c]	182721	1			T2	35		T3	4		T4	38
valid_sources[0x5d]	197995	1			T2	20		T3	10		T4	40
valid_sources[0x5e]	191614	1			T2	28		T3	10		T4	39
valid_sources[0x5f]	183099	1			T2	33		T3	10		T4	40
valid_sources[0x60]	194277	1			T2	19		T3	501		T4	27
valid_sources[0x61]	184917	1			T2	21		T3	1004		T4	38
valid_sources[0x62]	195163	1			T2	30		T3	1		T4	47
valid_sources[0x63]	202455	1			T2	14		T3	494		T4	50
valid_sources[0x64]	200966	1			T2	27		T3	497		T4	33
valid_sources[0x65]	169563	1			T2	32		T3	5		T4	47
valid_sources[0x66]	186787	1			T2	27		T3	506		T4	32
valid_sources[0x67]	177911	1			T2	19		T3	15		T4	46
valid_sources[0x68]	198597	1			T2	10		T3	6		T4	40
valid_sources[0x69]	215736	1			T2	17		T3	502		T4	38
valid_sources[0x6a]	186666	1			T1	102		T2	24		T3	2
valid_sources[0x6b]	182362	1			T2	25		T3	509		T4	38
valid_sources[0x6c]	204285	1			T2	15		T3	504		T4	21
valid_sources[0x6d]	188723	1			T2	27		T3	2		T4	42
valid_sources[0x6e]	285859	1			T2	14		T3	6		T4	40
valid_sources[0x6f]	195155	1			T2	27		T3	504		T4	28
valid_sources[0x70]	176839	1			T2	22		T3	3		T4	30
valid_sources[0x71]	197734	1			T2	11		T3	2		T4	29
valid_sources[0x72]	185398	1			T2	17		T3	501		T4	29
valid_sources[0x73]	173486	1			T2	11		T3	3		T4	49
valid_sources[0x74]	186427	1			T2	9		T3	522		T4	28
valid_sources[0x75]	181355	1			T2	23		T3	6		T4	37
valid_sources[0x76]	192432	1			T2	20		T3	12		T4	36
valid_sources[0x77]	195802	1			T2	21		T3	3		T4	39
valid_sources[0x78]	178176	1			T2	17		T3	500		T4	53
valid_sources[0x79]	184122	1			T2	29		T3	509		T4	48
valid_sources[0x7a]	191801	1			T2	28		T3	505		T4	27
valid_sources[0x7b]	212410	1			T2	30		T3	24		T4	38
valid_sources[0x7c]	194141	1			T2	11		T3	7		T4	33
valid_sources[0x7d]	179858	1			T2	28		T3	3		T4	43
valid_sources[0x7e]	183648	1			T2	34		T3	2		T4	37
valid_sources[0x7f]	181829	1			T2	15		T3	506		T4	21
valid_sources[0x80]	221816	1			T2	24		T3	500		T4	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9727392

1

T1

248

T2

2785

T3

13573

values[0x0]

all_enables

biggest_size

242720

1

T1

57

T2

5

T3

207

values[0x1]

all_enables

biggest_size

170764

1

T1

25

T2

4

T3

183