Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
92.86 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[i2c_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[i2c_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[i2c_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[i2c_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 50112955 0 T1 21722 T2 5601 T3 53988



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 50112765 1 T1 21722 T2 5601 T3 53988
values[1] 19 1 T154 2 T197 1 T198 2
values[2] 3 1 T193 1 T102 1 T206 1
values[3] 93 1 T154 2 T192 3 T193 3



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 50112771 1 T1 21722 T2 5601 T3 53988
values[1] 25 1 T154 1 T102 2 T197 2
values[2] 3 1 T261 1 T209 1 T205 1
values[3] 80 1 T154 2 T192 3 T193 1



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 50112675 1 T1 21722 T2 5601 T3 53988
auto[TlIntgErrCmd] 96 1 T154 4 T192 4 T193 7
auto[TlIntgErrData] 90 1 T154 3 T192 6 T102 8
auto[TlIntgErrBoth] 94 1 T154 3 T193 3 T102 6

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